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authorLinus Torvalds <torvalds@linux-foundation.org>2019-03-15 17:32:59 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2019-03-15 17:32:59 -0400
commite8a71a38668919c53e6ca9dd1bfa977e5690523f (patch)
treee04a7b81eb8d6a2d0f03f45dfbbf0d8378ce874c /drivers/ntb/hw
parent2b9c272cf5cd81708e51b4ce3e432ce9566cfa47 (diff)
parentebb09b33c60c46fd4f7ffa0af9e693eebe765d1b (diff)
Merge tag 'ntb-5.1' of git://github.com/jonmason/ntb
Pull NTB updates from Jon Mason: - fixes for switchtec debugability and mapping table entries - NTB transport improvements - a reworking of the peer_db_addr for better abstraction * tag 'ntb-5.1' of git://github.com/jonmason/ntb: NTB: add new parameter to peer_db_addr() db_bit and db_data NTB: ntb_transport: Ensure the destination buffer is mapped for TX DMA NTB: ntb_transport: Free MWs in ntb_transport_link_cleanup() ntb_hw_switchtec: Added support of >=4G memory windows ntb_hw_switchtec: NT req id mapping table register entry number should be 512 ntb_hw_switchtec: debug print 64bit aligned crosslink BAR Numbers
Diffstat (limited to 'drivers/ntb/hw')
-rw-r--r--drivers/ntb/hw/intel/ntb_hw_gen1.c25
-rw-r--r--drivers/ntb/hw/intel/ntb_hw_gen1.h5
-rw-r--r--drivers/ntb/hw/intel/ntb_hw_gen3.c33
-rw-r--r--drivers/ntb/hw/mscc/ntb_hw_switchtec.c20
4 files changed, 70 insertions, 13 deletions
diff --git a/drivers/ntb/hw/intel/ntb_hw_gen1.c b/drivers/ntb/hw/intel/ntb_hw_gen1.c
index 2ad263f708da..bb57ec239029 100644
--- a/drivers/ntb/hw/intel/ntb_hw_gen1.c
+++ b/drivers/ntb/hw/intel/ntb_hw_gen1.c
@@ -180,7 +180,7 @@ int ndev_mw_to_bar(struct intel_ntb_dev *ndev, int idx)
180 return ndev->reg->mw_bar[idx]; 180 return ndev->reg->mw_bar[idx];
181} 181}
182 182
183static inline int ndev_db_addr(struct intel_ntb_dev *ndev, 183void ndev_db_addr(struct intel_ntb_dev *ndev,
184 phys_addr_t *db_addr, resource_size_t *db_size, 184 phys_addr_t *db_addr, resource_size_t *db_size,
185 phys_addr_t reg_addr, unsigned long reg) 185 phys_addr_t reg_addr, unsigned long reg)
186{ 186{
@@ -196,8 +196,6 @@ static inline int ndev_db_addr(struct intel_ntb_dev *ndev,
196 *db_size = ndev->reg->db_size; 196 *db_size = ndev->reg->db_size;
197 dev_dbg(&ndev->ntb.pdev->dev, "Peer db size %llx\n", *db_size); 197 dev_dbg(&ndev->ntb.pdev->dev, "Peer db size %llx\n", *db_size);
198 } 198 }
199
200 return 0;
201} 199}
202 200
203u64 ndev_db_read(struct intel_ntb_dev *ndev, 201u64 ndev_db_read(struct intel_ntb_dev *ndev,
@@ -1111,13 +1109,28 @@ int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits)
1111 ndev->self_reg->db_mask); 1109 ndev->self_reg->db_mask);
1112} 1110}
1113 1111
1114int intel_ntb_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr, 1112static int intel_ntb_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
1115 resource_size_t *db_size) 1113 resource_size_t *db_size, u64 *db_data, int db_bit)
1116{ 1114{
1115 u64 db_bits;
1117 struct intel_ntb_dev *ndev = ntb_ndev(ntb); 1116 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
1118 1117
1119 return ndev_db_addr(ndev, db_addr, db_size, ndev->peer_addr, 1118 if (unlikely(db_bit >= BITS_PER_LONG_LONG))
1119 return -EINVAL;
1120
1121 db_bits = BIT_ULL(db_bit);
1122
1123 if (unlikely(db_bits & ~ntb_ndev(ntb)->db_valid_mask))
1124 return -EINVAL;
1125
1126 ndev_db_addr(ndev, db_addr, db_size, ndev->peer_addr,
1120 ndev->peer_reg->db_bell); 1127 ndev->peer_reg->db_bell);
1128
1129 if (db_data)
1130 *db_data = db_bits;
1131
1132
1133 return 0;
1121} 1134}
1122 1135
1123static int intel_ntb_peer_db_set(struct ntb_dev *ntb, u64 db_bits) 1136static int intel_ntb_peer_db_set(struct ntb_dev *ntb, u64 db_bits)
diff --git a/drivers/ntb/hw/intel/ntb_hw_gen1.h b/drivers/ntb/hw/intel/ntb_hw_gen1.h
index ad8ec1444436..544cf5c06f4d 100644
--- a/drivers/ntb/hw/intel/ntb_hw_gen1.h
+++ b/drivers/ntb/hw/intel/ntb_hw_gen1.h
@@ -147,6 +147,9 @@ extern struct intel_b2b_addr xeon_b2b_dsd_addr;
147int ndev_init_isr(struct intel_ntb_dev *ndev, int msix_min, int msix_max, 147int ndev_init_isr(struct intel_ntb_dev *ndev, int msix_min, int msix_max,
148 int msix_shift, int total_shift); 148 int msix_shift, int total_shift);
149enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd); 149enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd);
150void ndev_db_addr(struct intel_ntb_dev *ndev,
151 phys_addr_t *db_addr, resource_size_t *db_size,
152 phys_addr_t reg_addr, unsigned long reg);
150u64 ndev_db_read(struct intel_ntb_dev *ndev, void __iomem *mmio); 153u64 ndev_db_read(struct intel_ntb_dev *ndev, void __iomem *mmio);
151int ndev_db_write(struct intel_ntb_dev *ndev, u64 db_bits, 154int ndev_db_write(struct intel_ntb_dev *ndev, u64 db_bits,
152 void __iomem *mmio); 155 void __iomem *mmio);
@@ -166,8 +169,6 @@ int intel_ntb_db_vector_count(struct ntb_dev *ntb);
166u64 intel_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector); 169u64 intel_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector);
167int intel_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits); 170int intel_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits);
168int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits); 171int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits);
169int intel_ntb_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
170 resource_size_t *db_size);
171int intel_ntb_spad_is_unsafe(struct ntb_dev *ntb); 172int intel_ntb_spad_is_unsafe(struct ntb_dev *ntb);
172int intel_ntb_spad_count(struct ntb_dev *ntb); 173int intel_ntb_spad_count(struct ntb_dev *ntb);
173u32 intel_ntb_spad_read(struct ntb_dev *ntb, int idx); 174u32 intel_ntb_spad_read(struct ntb_dev *ntb, int idx);
diff --git a/drivers/ntb/hw/intel/ntb_hw_gen3.c b/drivers/ntb/hw/intel/ntb_hw_gen3.c
index b3fa24778f94..f475b56a3f49 100644
--- a/drivers/ntb/hw/intel/ntb_hw_gen3.c
+++ b/drivers/ntb/hw/intel/ntb_hw_gen3.c
@@ -532,6 +532,37 @@ static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
532 return 0; 532 return 0;
533} 533}
534 534
535int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
536 resource_size_t *db_size,
537 u64 *db_data, int db_bit)
538{
539 phys_addr_t db_addr_base;
540 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
541
542 if (unlikely(db_bit >= BITS_PER_LONG_LONG))
543 return -EINVAL;
544
545 if (unlikely(BIT_ULL(db_bit) & ~ntb_ndev(ntb)->db_valid_mask))
546 return -EINVAL;
547
548 ndev_db_addr(ndev, &db_addr_base, db_size, ndev->peer_addr,
549 ndev->peer_reg->db_bell);
550
551 if (db_addr) {
552 *db_addr = db_addr_base + (db_bit * 4);
553 dev_dbg(&ndev->ntb.pdev->dev, "Peer db addr %llx db bit %d\n",
554 *db_addr, db_bit);
555 }
556
557 if (db_data) {
558 *db_data = 1;
559 dev_dbg(&ndev->ntb.pdev->dev, "Peer db data %llx db bit %d\n",
560 *db_data, db_bit);
561 }
562
563 return 0;
564}
565
535static int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits) 566static int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits)
536{ 567{
537 struct intel_ntb_dev *ndev = ntb_ndev(ntb); 568 struct intel_ntb_dev *ndev = ntb_ndev(ntb);
@@ -584,7 +615,7 @@ const struct ntb_dev_ops intel_ntb3_ops = {
584 .db_clear = intel_ntb3_db_clear, 615 .db_clear = intel_ntb3_db_clear,
585 .db_set_mask = intel_ntb_db_set_mask, 616 .db_set_mask = intel_ntb_db_set_mask,
586 .db_clear_mask = intel_ntb_db_clear_mask, 617 .db_clear_mask = intel_ntb_db_clear_mask,
587 .peer_db_addr = intel_ntb_peer_db_addr, 618 .peer_db_addr = intel_ntb3_peer_db_addr,
588 .peer_db_set = intel_ntb3_peer_db_set, 619 .peer_db_set = intel_ntb3_peer_db_set,
589 .spad_is_unsafe = intel_ntb_spad_is_unsafe, 620 .spad_is_unsafe = intel_ntb_spad_is_unsafe,
590 .spad_count = intel_ntb_spad_count, 621 .spad_count = intel_ntb_spad_count,
diff --git a/drivers/ntb/hw/mscc/ntb_hw_switchtec.c b/drivers/ntb/hw/mscc/ntb_hw_switchtec.c
index f2df2d39c65b..d905d368d28c 100644
--- a/drivers/ntb/hw/mscc/ntb_hw_switchtec.c
+++ b/drivers/ntb/hw/mscc/ntb_hw_switchtec.c
@@ -236,6 +236,7 @@ static void switchtec_ntb_mw_clr_direct(struct switchtec_ntb *sndev, int idx)
236 ctl_val &= ~NTB_CTRL_BAR_DIR_WIN_EN; 236 ctl_val &= ~NTB_CTRL_BAR_DIR_WIN_EN;
237 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl); 237 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl);
238 iowrite32(0, &ctl->bar_entry[bar].win_size); 238 iowrite32(0, &ctl->bar_entry[bar].win_size);
239 iowrite32(0, &ctl->bar_ext_entry[bar].win_size);
239 iowrite64(sndev->self_partition, &ctl->bar_entry[bar].xlate_addr); 240 iowrite64(sndev->self_partition, &ctl->bar_entry[bar].xlate_addr);
240} 241}
241 242
@@ -258,7 +259,9 @@ static void switchtec_ntb_mw_set_direct(struct switchtec_ntb *sndev, int idx,
258 ctl_val |= NTB_CTRL_BAR_DIR_WIN_EN; 259 ctl_val |= NTB_CTRL_BAR_DIR_WIN_EN;
259 260
260 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl); 261 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl);
261 iowrite32(xlate_pos | size, &ctl->bar_entry[bar].win_size); 262 iowrite32(xlate_pos | (lower_32_bits(size) & 0xFFFFF000),
263 &ctl->bar_entry[bar].win_size);
264 iowrite32(upper_32_bits(size), &ctl->bar_ext_entry[bar].win_size);
262 iowrite64(sndev->self_partition | addr, 265 iowrite64(sndev->self_partition | addr,
263 &ctl->bar_entry[bar].xlate_addr); 266 &ctl->bar_entry[bar].xlate_addr);
264} 267}
@@ -679,11 +682,16 @@ static u64 switchtec_ntb_db_read_mask(struct ntb_dev *ntb)
679 682
680static int switchtec_ntb_peer_db_addr(struct ntb_dev *ntb, 683static int switchtec_ntb_peer_db_addr(struct ntb_dev *ntb,
681 phys_addr_t *db_addr, 684 phys_addr_t *db_addr,
682 resource_size_t *db_size) 685 resource_size_t *db_size,
686 u64 *db_data,
687 int db_bit)
683{ 688{
684 struct switchtec_ntb *sndev = ntb_sndev(ntb); 689 struct switchtec_ntb *sndev = ntb_sndev(ntb);
685 unsigned long offset; 690 unsigned long offset;
686 691
692 if (unlikely(db_bit >= BITS_PER_LONG_LONG))
693 return -EINVAL;
694
687 offset = (unsigned long)sndev->mmio_peer_dbmsg->odb - 695 offset = (unsigned long)sndev->mmio_peer_dbmsg->odb -
688 (unsigned long)sndev->stdev->mmio; 696 (unsigned long)sndev->stdev->mmio;
689 697
@@ -693,6 +701,8 @@ static int switchtec_ntb_peer_db_addr(struct ntb_dev *ntb,
693 *db_addr = pci_resource_start(ntb->pdev, 0) + offset; 701 *db_addr = pci_resource_start(ntb->pdev, 0) + offset;
694 if (db_size) 702 if (db_size)
695 *db_size = sizeof(u32); 703 *db_size = sizeof(u32);
704 if (db_data)
705 *db_data = BIT_ULL(db_bit) << sndev->db_peer_shift;
696 706
697 return 0; 707 return 0;
698} 708}
@@ -1025,7 +1035,9 @@ static int crosslink_setup_mws(struct switchtec_ntb *sndev, int ntb_lut_idx,
1025 ctl_val |= NTB_CTRL_BAR_DIR_WIN_EN; 1035 ctl_val |= NTB_CTRL_BAR_DIR_WIN_EN;
1026 1036
1027 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl); 1037 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl);
1028 iowrite32(xlate_pos | size, &ctl->bar_entry[bar].win_size); 1038 iowrite32(xlate_pos | (lower_32_bits(size) & 0xFFFFF000),
1039 &ctl->bar_entry[bar].win_size);
1040 iowrite32(upper_32_bits(size), &ctl->bar_ext_entry[bar].win_size);
1029 iowrite64(sndev->peer_partition | addr, 1041 iowrite64(sndev->peer_partition | addr,
1030 &ctl->bar_entry[bar].xlate_addr); 1042 &ctl->bar_entry[bar].xlate_addr);
1031 } 1043 }
@@ -1092,7 +1104,7 @@ static int crosslink_enum_partition(struct switchtec_ntb *sndev,
1092 1104
1093 dev_dbg(&sndev->stdev->dev, 1105 dev_dbg(&sndev->stdev->dev,
1094 "Crosslink BAR%d addr: %llx\n", 1106 "Crosslink BAR%d addr: %llx\n",
1095 i, bar_addr); 1107 i*2, bar_addr);
1096 1108
1097 if (bar_addr != bar_space * i) 1109 if (bar_addr != bar_space * i)
1098 continue; 1110 continue;