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authorPaul Selles <paul.selles@microchip.com>2018-12-06 08:30:52 -0500
committerJon Mason <jdmason@kudzu.us>2019-02-11 07:36:13 -0500
commita2585cdc9e4cda6afaea5f5687eaabce3bebbb2c (patch)
tree69265e8485e481e84ec481e0922321eef7ebe21a /drivers/ntb/hw
parentd123fab71f63aae129aebe052664fda73131921a (diff)
ntb_hw_switchtec: Added support of >=4G memory windows
Current Switchtec's BAR setup registers are limited to 32bits, corresponding to the maximum MW (memory window) size is <4G. Increase the MW sizes with the addition of the BAR Setup Extension Register for the upper 32bits of a 64bits MW size. This increases the MW range to between 4K and 2^63. Reported-by: Boris Glimcher <boris.glimcher@emc.com> Signed-off-by: Paul Selles <paul.selles@microchip.com> Signed-off-by: Wesley Sheng <wesley.sheng@microchip.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
Diffstat (limited to 'drivers/ntb/hw')
-rw-r--r--drivers/ntb/hw/mscc/ntb_hw_switchtec.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/ntb/hw/mscc/ntb_hw_switchtec.c b/drivers/ntb/hw/mscc/ntb_hw_switchtec.c
index 9916bc5b6759..f6f00354047b 100644
--- a/drivers/ntb/hw/mscc/ntb_hw_switchtec.c
+++ b/drivers/ntb/hw/mscc/ntb_hw_switchtec.c
@@ -264,6 +264,7 @@ static void switchtec_ntb_mw_clr_direct(struct switchtec_ntb *sndev, int idx)
264 ctl_val &= ~NTB_CTRL_BAR_DIR_WIN_EN; 264 ctl_val &= ~NTB_CTRL_BAR_DIR_WIN_EN;
265 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl); 265 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl);
266 iowrite32(0, &ctl->bar_entry[bar].win_size); 266 iowrite32(0, &ctl->bar_entry[bar].win_size);
267 iowrite32(0, &ctl->bar_ext_entry[bar].win_size);
267 iowrite64(sndev->self_partition, &ctl->bar_entry[bar].xlate_addr); 268 iowrite64(sndev->self_partition, &ctl->bar_entry[bar].xlate_addr);
268} 269}
269 270
@@ -286,7 +287,9 @@ static void switchtec_ntb_mw_set_direct(struct switchtec_ntb *sndev, int idx,
286 ctl_val |= NTB_CTRL_BAR_DIR_WIN_EN; 287 ctl_val |= NTB_CTRL_BAR_DIR_WIN_EN;
287 288
288 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl); 289 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl);
289 iowrite32(xlate_pos | size, &ctl->bar_entry[bar].win_size); 290 iowrite32(xlate_pos | (lower_32_bits(size) & 0xFFFFF000),
291 &ctl->bar_entry[bar].win_size);
292 iowrite32(upper_32_bits(size), &ctl->bar_ext_entry[bar].win_size);
290 iowrite64(sndev->self_partition | addr, 293 iowrite64(sndev->self_partition | addr,
291 &ctl->bar_entry[bar].xlate_addr); 294 &ctl->bar_entry[bar].xlate_addr);
292} 295}
@@ -1053,7 +1056,9 @@ static int crosslink_setup_mws(struct switchtec_ntb *sndev, int ntb_lut_idx,
1053 ctl_val |= NTB_CTRL_BAR_DIR_WIN_EN; 1056 ctl_val |= NTB_CTRL_BAR_DIR_WIN_EN;
1054 1057
1055 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl); 1058 iowrite32(ctl_val, &ctl->bar_entry[bar].ctl);
1056 iowrite32(xlate_pos | size, &ctl->bar_entry[bar].win_size); 1059 iowrite32(xlate_pos | (lower_32_bits(size) & 0xFFFFF000),
1060 &ctl->bar_entry[bar].win_size);
1061 iowrite32(upper_32_bits(size), &ctl->bar_ext_entry[bar].win_size);
1057 iowrite64(sndev->peer_partition | addr, 1062 iowrite64(sndev->peer_partition | addr,
1058 &ctl->bar_entry[bar].xlate_addr); 1063 &ctl->bar_entry[bar].xlate_addr);
1059 } 1064 }