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authorBoris Brezillon <boris.brezillon@free-electrons.com>2017-03-16 04:02:40 -0400
committerBoris Brezillon <boris.brezillon@free-electrons.com>2017-04-25 08:18:29 -0400
commitf88fc122cc34c2545dec9562eaab121494e401ef (patch)
tree67d2b937fbd76a958ec8ca0562ba7a4d67fdb08d /drivers/mtd/nand
parentef980cf8b05bc862f4533fcdeae2911e6ff7027a (diff)
mtd: nand: Cleanup/rework the atmel_nand driver
This is a complete rewrite of the driver whose main purpose is to support the new DT representation where the NAND controller node is now really visible in the DT and appears under the EBI bus. With this new representation, we can add other devices under the EBI bus without risking pinmuxing conflicts (the NAND controller is under the EBI bus logic and as such, share some of its pins with other devices connected on this bus). Even though the goal of this rework was not necessarily to add new features, the new driver has been designed with this in mind. With a clearer separation between the different blocks and different IP revisions, adding new functionalities should be easier (we already have plans to support SMC timing configuration so that we no longer have to rely on the configuration done by the bootloader/bootstrap). Also note that we no longer have a custom ->cmdfunc() implementation, which means we can now benefit from new features added in the core implementation for free (support for new NAND operations for example). The last thing that we gain with this rework is support for multi-chips and multi-dies chips, thanks to the clean NAND controller <-> NAND devices representation. During this transition we also dropped support for AVR32 SoCs which should soon disappear from mainline (removal of the AVR32 arch is planned for 4.12). This new driver has been tested on several platforms (at91sam9261, at91sam9g45, at91sam9x5, sama5d3 and sama5d4) to make sure it did not introduce regressions, and it's worth mentioning that old bindings are still supported (which partly explain the positive diffstat). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Diffstat (limited to 'drivers/mtd/nand')
-rw-r--r--drivers/mtd/nand/Kconfig6
-rw-r--r--drivers/mtd/nand/Makefile2
-rw-r--r--drivers/mtd/nand/atmel/Makefile4
-rw-r--r--drivers/mtd/nand/atmel/nand-controller.c2196
-rw-r--r--drivers/mtd/nand/atmel/pmecc.c1020
-rw-r--r--drivers/mtd/nand/atmel/pmecc.h73
-rw-r--r--drivers/mtd/nand/atmel_nand.c2479
-rw-r--r--drivers/mtd/nand/atmel_nand_ecc.h163
-rw-r--r--drivers/mtd/nand/atmel_nand_nfc.h103
9 files changed, 3297 insertions, 2749 deletions
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index aa44fb0a1b18..c3029528063b 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -306,11 +306,11 @@ config MTD_NAND_CS553X
306 If you say "m", the module will be called cs553x_nand. 306 If you say "m", the module will be called cs553x_nand.
307 307
308config MTD_NAND_ATMEL 308config MTD_NAND_ATMEL
309 tristate "Support for NAND Flash / SmartMedia on AT91 and AVR32" 309 tristate "Support for NAND Flash / SmartMedia on AT91"
310 depends on ARCH_AT91 || AVR32 310 depends on ARCH_AT91
311 help 311 help
312 Enables support for NAND Flash / Smart Media Card interface 312 Enables support for NAND Flash / Smart Media Card interface
313 on Atmel AT91 and AVR32 processors. 313 on Atmel AT91 processors.
314 314
315config MTD_NAND_PXA3xx 315config MTD_NAND_PXA3xx
316 tristate "NAND support on PXA3xx and Armada 370/XP" 316 tristate "NAND support on PXA3xx and Armada 370/XP"
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 098b8791f10a..ade5fc4c3819 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -24,7 +24,7 @@ obj-$(CONFIG_MTD_NAND_SHARPSL) += sharpsl.o
24obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o 24obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o
25obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o 25obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o
26obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o 26obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o
27obj-$(CONFIG_MTD_NAND_ATMEL) += atmel_nand.o 27obj-$(CONFIG_MTD_NAND_ATMEL) += atmel/
28obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o 28obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o
29omap2_nand-objs := omap2.o 29omap2_nand-objs := omap2.o
30obj-$(CONFIG_MTD_NAND_OMAP2) += omap2_nand.o 30obj-$(CONFIG_MTD_NAND_OMAP2) += omap2_nand.o
diff --git a/drivers/mtd/nand/atmel/Makefile b/drivers/mtd/nand/atmel/Makefile
new file mode 100644
index 000000000000..288db4f38a8f
--- /dev/null
+++ b/drivers/mtd/nand/atmel/Makefile
@@ -0,0 +1,4 @@
1obj-$(CONFIG_MTD_NAND_ATMEL) += atmel-nand-controller.o atmel-pmecc.o
2
3atmel-nand-controller-objs := nand-controller.o
4atmel-pmecc-objs := pmecc.o
diff --git a/drivers/mtd/nand/atmel/nand-controller.c b/drivers/mtd/nand/atmel/nand-controller.c
new file mode 100644
index 000000000000..80e2459f92f8
--- /dev/null
+++ b/drivers/mtd/nand/atmel/nand-controller.c
@@ -0,0 +1,2196 @@
1/*
2 * Copyright 2017 ATMEL
3 * Copyright 2017 Free Electrons
4 *
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
6 *
7 * Derived from the atmel_nand.c driver which contained the following
8 * copyrights:
9 *
10 * Copyright 2003 Rick Bronson
11 *
12 * Derived from drivers/mtd/nand/autcpu12.c
13 * Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
14 *
15 * Derived from drivers/mtd/spia.c
16 * Copyright 2000 Steven J. Hill (sjhill@cotw.com)
17 *
18 *
19 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
20 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
21 *
22 * Derived from Das U-Boot source code
23 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
24 * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
25 *
26 * Add Programmable Multibit ECC support for various AT91 SoC
27 * Copyright 2012 ATMEL, Hong Xu
28 *
29 * Add Nand Flash Controller support for SAMA5 SoC
30 * Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
31 *
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License version 2 as
34 * published by the Free Software Foundation.
35 *
36 * A few words about the naming convention in this file. This convention
37 * applies to structure and function names.
38 *
39 * Prefixes:
40 *
41 * - atmel_nand_: all generic structures/functions
42 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
43 * (at91sam9 and avr32 SoCs)
44 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
45 * (sama5 SoCs and later)
46 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
47 * that is available in the HSMC block
48 * - <soc>_nand_: all SoC specific structures/functions
49 */
50
51#include <linux/clk.h>
52#include <linux/dma-mapping.h>
53#include <linux/dmaengine.h>
54#include <linux/genalloc.h>
55#include <linux/gpio.h>
56#include <linux/gpio/consumer.h>
57#include <linux/interrupt.h>
58#include <linux/mfd/syscon.h>
59#include <linux/mfd/syscon/atmel-matrix.h>
60#include <linux/module.h>
61#include <linux/mtd/nand.h>
62#include <linux/of_address.h>
63#include <linux/of_irq.h>
64#include <linux/of_platform.h>
65#include <linux/iopoll.h>
66#include <linux/platform_device.h>
67#include <linux/platform_data/atmel.h>
68#include <linux/regmap.h>
69
70#include "pmecc.h"
71
72#define ATMEL_HSMC_NFC_CFG 0x0
73#define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24)
74#define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24)
75#define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul) (((cyc) << 16) | ((mul) << 20))
76#define ATMEL_HSMC_NFC_CFG_DTO_MAX GENMASK(22, 16)
77#define ATMEL_HSMC_NFC_CFG_RBEDGE BIT(13)
78#define ATMEL_HSMC_NFC_CFG_FALLING_EDGE BIT(12)
79#define ATMEL_HSMC_NFC_CFG_RSPARE BIT(9)
80#define ATMEL_HSMC_NFC_CFG_WSPARE BIT(8)
81#define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK GENMASK(2, 0)
82#define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1)
83
84#define ATMEL_HSMC_NFC_CTRL 0x4
85#define ATMEL_HSMC_NFC_CTRL_EN BIT(0)
86#define ATMEL_HSMC_NFC_CTRL_DIS BIT(1)
87
88#define ATMEL_HSMC_NFC_SR 0x8
89#define ATMEL_HSMC_NFC_IER 0xc
90#define ATMEL_HSMC_NFC_IDR 0x10
91#define ATMEL_HSMC_NFC_IMR 0x14
92#define ATMEL_HSMC_NFC_SR_ENABLED BIT(1)
93#define ATMEL_HSMC_NFC_SR_RB_RISE BIT(4)
94#define ATMEL_HSMC_NFC_SR_RB_FALL BIT(5)
95#define ATMEL_HSMC_NFC_SR_BUSY BIT(8)
96#define ATMEL_HSMC_NFC_SR_WR BIT(11)
97#define ATMEL_HSMC_NFC_SR_CSID GENMASK(14, 12)
98#define ATMEL_HSMC_NFC_SR_XFRDONE BIT(16)
99#define ATMEL_HSMC_NFC_SR_CMDDONE BIT(17)
100#define ATMEL_HSMC_NFC_SR_DTOE BIT(20)
101#define ATMEL_HSMC_NFC_SR_UNDEF BIT(21)
102#define ATMEL_HSMC_NFC_SR_AWB BIT(22)
103#define ATMEL_HSMC_NFC_SR_NFCASE BIT(23)
104#define ATMEL_HSMC_NFC_SR_ERRORS (ATMEL_HSMC_NFC_SR_DTOE | \
105 ATMEL_HSMC_NFC_SR_UNDEF | \
106 ATMEL_HSMC_NFC_SR_AWB | \
107 ATMEL_HSMC_NFC_SR_NFCASE)
108#define ATMEL_HSMC_NFC_SR_RBEDGE(x) BIT((x) + 24)
109
110#define ATMEL_HSMC_NFC_ADDR 0x18
111#define ATMEL_HSMC_NFC_BANK 0x1c
112
113#define ATMEL_NFC_MAX_RB_ID 7
114
115#define ATMEL_NFC_SRAM_SIZE 0x2400
116
117#define ATMEL_NFC_CMD(pos, cmd) ((cmd) << (((pos) * 8) + 2))
118#define ATMEL_NFC_VCMD2 BIT(18)
119#define ATMEL_NFC_ACYCLE(naddrs) ((naddrs) << 19)
120#define ATMEL_NFC_CSID(cs) ((cs) << 22)
121#define ATMEL_NFC_DATAEN BIT(25)
122#define ATMEL_NFC_NFCWR BIT(26)
123
124#define ATMEL_NFC_MAX_ADDR_CYCLES 5
125
126#define ATMEL_NAND_ALE_OFFSET BIT(21)
127#define ATMEL_NAND_CLE_OFFSET BIT(22)
128
129#define DEFAULT_TIMEOUT_MS 1000
130#define MIN_DMA_LEN 128
131
132enum atmel_nand_rb_type {
133 ATMEL_NAND_NO_RB,
134 ATMEL_NAND_NATIVE_RB,
135 ATMEL_NAND_GPIO_RB,
136};
137
138struct atmel_nand_rb {
139 enum atmel_nand_rb_type type;
140 union {
141 struct gpio_desc *gpio;
142 int id;
143 };
144};
145
146struct atmel_nand_cs {
147 int id;
148 struct atmel_nand_rb rb;
149 struct gpio_desc *csgpio;
150 struct {
151 void __iomem *virt;
152 dma_addr_t dma;
153 } io;
154};
155
156struct atmel_nand {
157 struct list_head node;
158 struct device *dev;
159 struct nand_chip base;
160 struct atmel_nand_cs *activecs;
161 struct atmel_pmecc_user *pmecc;
162 struct gpio_desc *cdgpio;
163 int numcs;
164 struct atmel_nand_cs cs[];
165};
166
167static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
168{
169 return container_of(chip, struct atmel_nand, base);
170}
171
172enum atmel_nfc_data_xfer {
173 ATMEL_NFC_NO_DATA,
174 ATMEL_NFC_READ_DATA,
175 ATMEL_NFC_WRITE_DATA,
176};
177
178struct atmel_nfc_op {
179 u8 cs;
180 u8 ncmds;
181 u8 cmds[2];
182 u8 naddrs;
183 u8 addrs[5];
184 enum atmel_nfc_data_xfer data;
185 u32 wait;
186 u32 errors;
187};
188
189struct atmel_nand_controller;
190struct atmel_nand_controller_caps;
191
192struct atmel_nand_controller_ops {
193 int (*probe)(struct platform_device *pdev,
194 const struct atmel_nand_controller_caps *caps);
195 int (*remove)(struct atmel_nand_controller *nc);
196 void (*nand_init)(struct atmel_nand_controller *nc,
197 struct atmel_nand *nand);
198 int (*ecc_init)(struct atmel_nand *nand);
199};
200
201struct atmel_nand_controller_caps {
202 bool has_dma;
203 bool legacy_of_bindings;
204 u32 ale_offs;
205 u32 cle_offs;
206 const struct atmel_nand_controller_ops *ops;
207};
208
209struct atmel_nand_controller {
210 struct nand_hw_control base;
211 const struct atmel_nand_controller_caps *caps;
212 struct device *dev;
213 struct regmap *smc;
214 struct dma_chan *dmac;
215 struct atmel_pmecc *pmecc;
216 struct list_head chips;
217 struct clk *mck;
218};
219
220static inline struct atmel_nand_controller *
221to_nand_controller(struct nand_hw_control *ctl)
222{
223 return container_of(ctl, struct atmel_nand_controller, base);
224}
225
226struct atmel_smc_nand_controller {
227 struct atmel_nand_controller base;
228 struct regmap *matrix;
229 unsigned int ebi_csa_offs;
230};
231
232static inline struct atmel_smc_nand_controller *
233to_smc_nand_controller(struct nand_hw_control *ctl)
234{
235 return container_of(to_nand_controller(ctl),
236 struct atmel_smc_nand_controller, base);
237}
238
239struct atmel_hsmc_nand_controller {
240 struct atmel_nand_controller base;
241 struct {
242 struct gen_pool *pool;
243 void __iomem *virt;
244 dma_addr_t dma;
245 } sram;
246 struct regmap *io;
247 struct atmel_nfc_op op;
248 struct completion complete;
249 int irq;
250
251 /* Only used when instantiating from legacy DT bindings. */
252 struct clk *clk;
253};
254
255static inline struct atmel_hsmc_nand_controller *
256to_hsmc_nand_controller(struct nand_hw_control *ctl)
257{
258 return container_of(to_nand_controller(ctl),
259 struct atmel_hsmc_nand_controller, base);
260}
261
262static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
263{
264 op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
265 op->wait ^= status & op->wait;
266
267 return !op->wait || op->errors;
268}
269
270static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
271{
272 struct atmel_hsmc_nand_controller *nc = data;
273 u32 sr, rcvd;
274 bool done;
275
276 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
277
278 rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
279 done = atmel_nfc_op_done(&nc->op, sr);
280
281 if (rcvd)
282 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
283
284 if (done)
285 complete(&nc->complete);
286
287 return rcvd ? IRQ_HANDLED : IRQ_NONE;
288}
289
290static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
291 unsigned int timeout_ms)
292{
293 int ret;
294
295 if (!timeout_ms)
296 timeout_ms = DEFAULT_TIMEOUT_MS;
297
298 if (poll) {
299 u32 status;
300
301 ret = regmap_read_poll_timeout(nc->base.smc,
302 ATMEL_HSMC_NFC_SR, status,
303 atmel_nfc_op_done(&nc->op,
304 status),
305 0, timeout_ms * 1000);
306 } else {
307 init_completion(&nc->complete);
308 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
309 nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
310 ret = wait_for_completion_timeout(&nc->complete,
311 msecs_to_jiffies(timeout_ms));
312 if (!ret)
313 ret = -ETIMEDOUT;
314 else
315 ret = 0;
316
317 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
318 }
319
320 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
321 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
322 ret = -ETIMEDOUT;
323 }
324
325 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
326 dev_err(nc->base.dev, "Access to an undefined area\n");
327 ret = -EIO;
328 }
329
330 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
331 dev_err(nc->base.dev, "Access while busy\n");
332 ret = -EIO;
333 }
334
335 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
336 dev_err(nc->base.dev, "Wrong access size\n");
337 ret = -EIO;
338 }
339
340 return ret;
341}
342
343static void atmel_nand_dma_transfer_finished(void *data)
344{
345 struct completion *finished = data;
346
347 complete(finished);
348}
349
350static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
351 void *buf, dma_addr_t dev_dma, size_t len,
352 enum dma_data_direction dir)
353{
354 DECLARE_COMPLETION_ONSTACK(finished);
355 dma_addr_t src_dma, dst_dma, buf_dma;
356 struct dma_async_tx_descriptor *tx;
357 dma_cookie_t cookie;
358
359 buf_dma = dma_map_single(nc->dev, buf, len, dir);
360 if (dma_mapping_error(nc->dev, dev_dma)) {
361 dev_err(nc->dev,
362 "Failed to prepare a buffer for DMA access\n");
363 goto err;
364 }
365
366 if (dir == DMA_FROM_DEVICE) {
367 src_dma = dev_dma;
368 dst_dma = buf_dma;
369 } else {
370 src_dma = buf_dma;
371 dst_dma = dev_dma;
372 }
373
374 tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
375 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
376 if (!tx) {
377 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
378 goto err_unmap;
379 }
380
381 tx->callback = atmel_nand_dma_transfer_finished;
382 tx->callback_param = &finished;
383
384 cookie = dmaengine_submit(tx);
385 if (dma_submit_error(cookie)) {
386 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
387 goto err_unmap;
388 }
389
390 dma_async_issue_pending(nc->dmac);
391 wait_for_completion(&finished);
392
393 return 0;
394
395err_unmap:
396 dma_unmap_single(nc->dev, buf_dma, len, dir);
397
398err:
399 dev_dbg(nc->dev, "Fall back to CPU I/O\n");
400
401 return -EIO;
402}
403
404static u8 atmel_nand_read_byte(struct mtd_info *mtd)
405{
406 struct nand_chip *chip = mtd_to_nand(mtd);
407 struct atmel_nand *nand = to_atmel_nand(chip);
408
409 return ioread8(nand->activecs->io.virt);
410}
411
412static u16 atmel_nand_read_word(struct mtd_info *mtd)
413{
414 struct nand_chip *chip = mtd_to_nand(mtd);
415 struct atmel_nand *nand = to_atmel_nand(chip);
416
417 return ioread16(nand->activecs->io.virt);
418}
419
420static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
421{
422 struct nand_chip *chip = mtd_to_nand(mtd);
423 struct atmel_nand *nand = to_atmel_nand(chip);
424
425 if (chip->options & NAND_BUSWIDTH_16)
426 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
427 else
428 iowrite8(byte, nand->activecs->io.virt);
429}
430
431static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
432{
433 struct nand_chip *chip = mtd_to_nand(mtd);
434 struct atmel_nand *nand = to_atmel_nand(chip);
435 struct atmel_nand_controller *nc;
436
437 nc = to_nand_controller(chip->controller);
438
439 /*
440 * If the controller supports DMA, the buffer address is DMA-able and
441 * len is long enough to make DMA transfers profitable, let's trigger
442 * a DMA transfer. If it fails, fallback to PIO mode.
443 */
444 if (nc->dmac && virt_addr_valid(buf) &&
445 len >= MIN_DMA_LEN &&
446 !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
447 DMA_FROM_DEVICE))
448 return;
449
450 if (chip->options & NAND_BUSWIDTH_16)
451 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
452 else
453 ioread8_rep(nand->activecs->io.virt, buf, len);
454}
455
456static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
457{
458 struct nand_chip *chip = mtd_to_nand(mtd);
459 struct atmel_nand *nand = to_atmel_nand(chip);
460 struct atmel_nand_controller *nc;
461
462 nc = to_nand_controller(chip->controller);
463
464 /*
465 * If the controller supports DMA, the buffer address is DMA-able and
466 * len is long enough to make DMA transfers profitable, let's trigger
467 * a DMA transfer. If it fails, fallback to PIO mode.
468 */
469 if (nc->dmac && virt_addr_valid(buf) &&
470 len >= MIN_DMA_LEN &&
471 !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
472 len, DMA_TO_DEVICE))
473 return;
474
475 if (chip->options & NAND_BUSWIDTH_16)
476 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
477 else
478 iowrite8_rep(nand->activecs->io.virt, buf, len);
479}
480
481static int atmel_nand_dev_ready(struct mtd_info *mtd)
482{
483 struct nand_chip *chip = mtd_to_nand(mtd);
484 struct atmel_nand *nand = to_atmel_nand(chip);
485
486 return gpiod_get_value(nand->activecs->rb.gpio);
487}
488
489static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
490{
491 struct nand_chip *chip = mtd_to_nand(mtd);
492 struct atmel_nand *nand = to_atmel_nand(chip);
493
494 if (cs < 0 || cs >= nand->numcs) {
495 nand->activecs = NULL;
496 chip->dev_ready = NULL;
497 return;
498 }
499
500 nand->activecs = &nand->cs[cs];
501
502 if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
503 chip->dev_ready = atmel_nand_dev_ready;
504}
505
506static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
507{
508 struct nand_chip *chip = mtd_to_nand(mtd);
509 struct atmel_nand *nand = to_atmel_nand(chip);
510 struct atmel_hsmc_nand_controller *nc;
511 u32 status;
512
513 nc = to_hsmc_nand_controller(chip->controller);
514
515 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
516
517 return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
518}
519
520static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
521{
522 struct nand_chip *chip = mtd_to_nand(mtd);
523 struct atmel_nand *nand = to_atmel_nand(chip);
524 struct atmel_hsmc_nand_controller *nc;
525
526 nc = to_hsmc_nand_controller(chip->controller);
527
528 atmel_nand_select_chip(mtd, cs);
529
530 if (!nand->activecs) {
531 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
532 ATMEL_HSMC_NFC_CTRL_DIS);
533 return;
534 }
535
536 if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
537 chip->dev_ready = atmel_hsmc_nand_dev_ready;
538
539 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
540 ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
541 ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
542 ATMEL_HSMC_NFC_CFG_RSPARE |
543 ATMEL_HSMC_NFC_CFG_WSPARE,
544 ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
545 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
546 ATMEL_HSMC_NFC_CFG_RSPARE);
547 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
548 ATMEL_HSMC_NFC_CTRL_EN);
549}
550
551static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
552{
553 u8 *addrs = nc->op.addrs;
554 unsigned int op = 0;
555 u32 addr, val;
556 int i, ret;
557
558 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
559
560 for (i = 0; i < nc->op.ncmds; i++)
561 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
562
563 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
564 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
565
566 op |= ATMEL_NFC_CSID(nc->op.cs) |
567 ATMEL_NFC_ACYCLE(nc->op.naddrs);
568
569 if (nc->op.ncmds > 1)
570 op |= ATMEL_NFC_VCMD2;
571
572 addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
573 (addrs[3] << 24);
574
575 if (nc->op.data != ATMEL_NFC_NO_DATA) {
576 op |= ATMEL_NFC_DATAEN;
577 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
578
579 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
580 op |= ATMEL_NFC_NFCWR;
581 }
582
583 /* Clear all flags. */
584 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
585
586 /* Send the command. */
587 regmap_write(nc->io, op, addr);
588
589 ret = atmel_nfc_wait(nc, poll, 0);
590 if (ret)
591 dev_err(nc->base.dev,
592 "Failed to send NAND command (err = %d)!",
593 ret);
594
595 /* Reset the op state. */
596 memset(&nc->op, 0, sizeof(nc->op));
597
598 return ret;
599}
600
601static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
602 unsigned int ctrl)
603{
604 struct nand_chip *chip = mtd_to_nand(mtd);
605 struct atmel_nand *nand = to_atmel_nand(chip);
606 struct atmel_hsmc_nand_controller *nc;
607
608 nc = to_hsmc_nand_controller(chip->controller);
609
610 if (ctrl & NAND_ALE) {
611 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
612 return;
613
614 nc->op.addrs[nc->op.naddrs++] = dat;
615 } else if (ctrl & NAND_CLE) {
616 if (nc->op.ncmds > 1)
617 return;
618
619 nc->op.cmds[nc->op.ncmds++] = dat;
620 }
621
622 if (dat == NAND_CMD_NONE) {
623 nc->op.cs = nand->activecs->id;
624 atmel_nfc_exec_op(nc, true);
625 }
626}
627
628static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
629 unsigned int ctrl)
630{
631 struct nand_chip *chip = mtd_to_nand(mtd);
632 struct atmel_nand *nand = to_atmel_nand(chip);
633 struct atmel_nand_controller *nc;
634
635 nc = to_nand_controller(chip->controller);
636
637 if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) {
638 if (ctrl & NAND_NCE)
639 gpiod_set_value(nand->activecs->csgpio, 0);
640 else
641 gpiod_set_value(nand->activecs->csgpio, 1);
642 }
643
644 if (ctrl & NAND_ALE)
645 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
646 else if (ctrl & NAND_CLE)
647 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
648}
649
650static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
651 bool oob_required)
652{
653 struct mtd_info *mtd = nand_to_mtd(chip);
654 struct atmel_hsmc_nand_controller *nc;
655 int ret = -EIO;
656
657 nc = to_hsmc_nand_controller(chip->controller);
658
659 if (nc->base.dmac)
660 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
661 nc->sram.dma, mtd->writesize,
662 DMA_TO_DEVICE);
663
664 /* Falling back to CPU copy. */
665 if (ret)
666 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
667
668 if (oob_required)
669 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
670 mtd->oobsize);
671}
672
673static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
674 bool oob_required)
675{
676 struct mtd_info *mtd = nand_to_mtd(chip);
677 struct atmel_hsmc_nand_controller *nc;
678 int ret = -EIO;
679
680 nc = to_hsmc_nand_controller(chip->controller);
681
682 if (nc->base.dmac)
683 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
684 mtd->writesize, DMA_FROM_DEVICE);
685
686 /* Falling back to CPU copy. */
687 if (ret)
688 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
689
690 if (oob_required)
691 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
692 mtd->oobsize);
693}
694
695static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
696{
697 struct mtd_info *mtd = nand_to_mtd(chip);
698 struct atmel_hsmc_nand_controller *nc;
699
700 nc = to_hsmc_nand_controller(chip->controller);
701
702 if (column >= 0) {
703 nc->op.addrs[nc->op.naddrs++] = column;
704
705 /*
706 * 2 address cycles for the column offset on large page NANDs.
707 */
708 if (mtd->writesize > 512)
709 nc->op.addrs[nc->op.naddrs++] = column >> 8;
710 }
711
712 if (page >= 0) {
713 nc->op.addrs[nc->op.naddrs++] = page;
714 nc->op.addrs[nc->op.naddrs++] = page >> 8;
715
716 if ((mtd->writesize > 512 && chip->chipsize > SZ_128M) ||
717 (mtd->writesize <= 512 && chip->chipsize > SZ_32M))
718 nc->op.addrs[nc->op.naddrs++] = page >> 16;
719 }
720}
721
722static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
723{
724 struct atmel_nand *nand = to_atmel_nand(chip);
725 struct atmel_nand_controller *nc;
726 int ret;
727
728 nc = to_nand_controller(chip->controller);
729
730 if (raw)
731 return 0;
732
733 ret = atmel_pmecc_enable(nand->pmecc, op);
734 if (ret)
735 dev_err(nc->dev,
736 "Failed to enable ECC engine (err = %d)\n", ret);
737
738 return ret;
739}
740
741static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
742{
743 struct atmel_nand *nand = to_atmel_nand(chip);
744
745 if (!raw)
746 atmel_pmecc_disable(nand->pmecc);
747}
748
749static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
750{
751 struct atmel_nand *nand = to_atmel_nand(chip);
752 struct mtd_info *mtd = nand_to_mtd(chip);
753 struct atmel_nand_controller *nc;
754 struct mtd_oob_region oobregion;
755 void *eccbuf;
756 int ret, i;
757
758 nc = to_nand_controller(chip->controller);
759
760 if (raw)
761 return 0;
762
763 ret = atmel_pmecc_wait_rdy(nand->pmecc);
764 if (ret) {
765 dev_err(nc->dev,
766 "Failed to transfer NAND page data (err = %d)\n",
767 ret);
768 return ret;
769 }
770
771 mtd_ooblayout_ecc(mtd, 0, &oobregion);
772 eccbuf = chip->oob_poi + oobregion.offset;
773
774 for (i = 0; i < chip->ecc.steps; i++) {
775 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
776 eccbuf);
777 eccbuf += chip->ecc.bytes;
778 }
779
780 return 0;
781}
782
783static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
784 bool raw)
785{
786 struct atmel_nand *nand = to_atmel_nand(chip);
787 struct mtd_info *mtd = nand_to_mtd(chip);
788 struct atmel_nand_controller *nc;
789 struct mtd_oob_region oobregion;
790 int ret, i, max_bitflips = 0;
791 void *databuf, *eccbuf;
792
793 nc = to_nand_controller(chip->controller);
794
795 if (raw)
796 return 0;
797
798 ret = atmel_pmecc_wait_rdy(nand->pmecc);
799 if (ret) {
800 dev_err(nc->dev,
801 "Failed to read NAND page data (err = %d)\n",
802 ret);
803 return ret;
804 }
805
806 mtd_ooblayout_ecc(mtd, 0, &oobregion);
807 eccbuf = chip->oob_poi + oobregion.offset;
808 databuf = buf;
809
810 for (i = 0; i < chip->ecc.steps; i++) {
811 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
812 eccbuf);
813 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
814 ret = nand_check_erased_ecc_chunk(databuf,
815 chip->ecc.size,
816 eccbuf,
817 chip->ecc.bytes,
818 NULL, 0,
819 chip->ecc.strength);
820
821 if (ret >= 0)
822 max_bitflips = max(ret, max_bitflips);
823 else
824 mtd->ecc_stats.failed++;
825
826 databuf += chip->ecc.size;
827 eccbuf += chip->ecc.bytes;
828 }
829
830 return max_bitflips;
831}
832
833static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
834 bool oob_required, int page, bool raw)
835{
836 struct mtd_info *mtd = nand_to_mtd(chip);
837 struct atmel_nand *nand = to_atmel_nand(chip);
838 int ret;
839
840 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
841 if (ret)
842 return ret;
843
844 atmel_nand_write_buf(mtd, buf, mtd->writesize);
845
846 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
847 if (ret) {
848 atmel_pmecc_disable(nand->pmecc);
849 return ret;
850 }
851
852 atmel_nand_pmecc_disable(chip, raw);
853
854 atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
855
856 return 0;
857}
858
859static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
860 struct nand_chip *chip, const u8 *buf,
861 int oob_required, int page)
862{
863 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
864}
865
866static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
867 struct nand_chip *chip,
868 const u8 *buf, int oob_required,
869 int page)
870{
871 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
872}
873
874static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
875 bool oob_required, int page, bool raw)
876{
877 struct mtd_info *mtd = nand_to_mtd(chip);
878 int ret;
879
880 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
881 if (ret)
882 return ret;
883
884 atmel_nand_read_buf(mtd, buf, mtd->writesize);
885 atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
886
887 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
888
889 atmel_nand_pmecc_disable(chip, raw);
890
891 return ret;
892}
893
894static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
895 struct nand_chip *chip, u8 *buf,
896 int oob_required, int page)
897{
898 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
899}
900
901static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
902 struct nand_chip *chip, u8 *buf,
903 int oob_required, int page)
904{
905 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
906}
907
908static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
909 const u8 *buf, bool oob_required,
910 int page, bool raw)
911{
912 struct mtd_info *mtd = nand_to_mtd(chip);
913 struct atmel_nand *nand = to_atmel_nand(chip);
914 struct atmel_hsmc_nand_controller *nc;
915 int ret;
916
917 nc = to_hsmc_nand_controller(chip->controller);
918
919 atmel_nfc_copy_to_sram(chip, buf, false);
920
921 nc->op.cmds[0] = NAND_CMD_SEQIN;
922 nc->op.ncmds = 1;
923 atmel_nfc_set_op_addr(chip, page, 0x0);
924 nc->op.cs = nand->activecs->id;
925 nc->op.data = ATMEL_NFC_WRITE_DATA;
926
927 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
928 if (ret)
929 return ret;
930
931 ret = atmel_nfc_exec_op(nc, false);
932 if (ret) {
933 atmel_nand_pmecc_disable(chip, raw);
934 dev_err(nc->base.dev,
935 "Failed to transfer NAND page data (err = %d)\n",
936 ret);
937 return ret;
938 }
939
940 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
941
942 atmel_nand_pmecc_disable(chip, raw);
943
944 if (ret)
945 return ret;
946
947 atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
948
949 nc->op.cmds[0] = NAND_CMD_PAGEPROG;
950 nc->op.ncmds = 1;
951 nc->op.cs = nand->activecs->id;
952 ret = atmel_nfc_exec_op(nc, false);
953 if (ret)
954 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
955 ret);
956
957 return ret;
958}
959
960static int atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd,
961 struct nand_chip *chip,
962 const u8 *buf, int oob_required,
963 int page)
964{
965 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
966 false);
967}
968
969static int atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd,
970 struct nand_chip *chip,
971 const u8 *buf,
972 int oob_required, int page)
973{
974 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
975 true);
976}
977
978static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
979 bool oob_required, int page,
980 bool raw)
981{
982 struct mtd_info *mtd = nand_to_mtd(chip);
983 struct atmel_nand *nand = to_atmel_nand(chip);
984 struct atmel_hsmc_nand_controller *nc;
985 int ret;
986
987 nc = to_hsmc_nand_controller(chip->controller);
988
989 /*
990 * Optimized read page accessors only work when the NAND R/B pin is
991 * connected to a native SoC R/B pin. If that's not the case, fallback
992 * to the non-optimized one.
993 */
994 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
995 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
996
997 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
998 raw);
999 }
1000
1001 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1002
1003 if (mtd->writesize > 512)
1004 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1005
1006 atmel_nfc_set_op_addr(chip, page, 0x0);
1007 nc->op.cs = nand->activecs->id;
1008 nc->op.data = ATMEL_NFC_READ_DATA;
1009
1010 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1011 if (ret)
1012 return ret;
1013
1014 ret = atmel_nfc_exec_op(nc, false);
1015 if (ret) {
1016 atmel_nand_pmecc_disable(chip, raw);
1017 dev_err(nc->base.dev,
1018 "Failed to load NAND page data (err = %d)\n",
1019 ret);
1020 return ret;
1021 }
1022
1023 atmel_nfc_copy_from_sram(chip, buf, true);
1024
1025 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1026
1027 atmel_nand_pmecc_disable(chip, raw);
1028
1029 return ret;
1030}
1031
1032static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
1033 struct nand_chip *chip, u8 *buf,
1034 int oob_required, int page)
1035{
1036 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1037 false);
1038}
1039
1040static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
1041 struct nand_chip *chip,
1042 u8 *buf, int oob_required,
1043 int page)
1044{
1045 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1046 true);
1047}
1048
1049static int atmel_nand_pmecc_init(struct nand_chip *chip)
1050{
1051 struct mtd_info *mtd = nand_to_mtd(chip);
1052 struct atmel_nand *nand = to_atmel_nand(chip);
1053 struct atmel_nand_controller *nc;
1054 struct atmel_pmecc_user_req req;
1055
1056 nc = to_nand_controller(chip->controller);
1057
1058 if (!nc->pmecc) {
1059 dev_err(nc->dev, "HW ECC not supported\n");
1060 return -ENOTSUPP;
1061 }
1062
1063 if (nc->caps->legacy_of_bindings) {
1064 u32 val;
1065
1066 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1067 &val))
1068 chip->ecc.strength = val;
1069
1070 if (!of_property_read_u32(nc->dev->of_node,
1071 "atmel,pmecc-sector-size",
1072 &val))
1073 chip->ecc.size = val;
1074 }
1075
1076 if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1077 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1078 else if (chip->ecc.strength)
1079 req.ecc.strength = chip->ecc.strength;
1080 else if (chip->ecc_strength_ds)
1081 req.ecc.strength = chip->ecc_strength_ds;
1082 else
1083 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1084
1085 if (chip->ecc.size)
1086 req.ecc.sectorsize = chip->ecc.size;
1087 else if (chip->ecc_step_ds)
1088 req.ecc.sectorsize = chip->ecc_step_ds;
1089 else
1090 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1091
1092 req.pagesize = mtd->writesize;
1093 req.oobsize = mtd->oobsize;
1094
1095 if (mtd->writesize <= 512) {
1096 req.ecc.bytes = 4;
1097 req.ecc.ooboffset = 0;
1098 } else {
1099 req.ecc.bytes = mtd->oobsize - 2;
1100 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1101 }
1102
1103 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1104 if (IS_ERR(nand->pmecc))
1105 return PTR_ERR(nand->pmecc);
1106
1107 chip->ecc.algo = NAND_ECC_BCH;
1108 chip->ecc.size = req.ecc.sectorsize;
1109 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1110 chip->ecc.strength = req.ecc.strength;
1111
1112 chip->options |= NAND_NO_SUBPAGE_WRITE;
1113
1114 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1115
1116 return 0;
1117}
1118
1119static int atmel_nand_ecc_init(struct atmel_nand *nand)
1120{
1121 struct nand_chip *chip = &nand->base;
1122 struct atmel_nand_controller *nc;
1123 int ret;
1124
1125 nc = to_nand_controller(chip->controller);
1126
1127 switch (chip->ecc.mode) {
1128 case NAND_ECC_NONE:
1129 case NAND_ECC_SOFT:
1130 /*
1131 * Nothing to do, the core will initialize everything for us.
1132 */
1133 break;
1134
1135 case NAND_ECC_HW:
1136 ret = atmel_nand_pmecc_init(chip);
1137 if (ret)
1138 return ret;
1139
1140 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1141 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1142 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1143 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1144 break;
1145
1146 default:
1147 /* Other modes are not supported. */
1148 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1149 chip->ecc.mode);
1150 return -ENOTSUPP;
1151 }
1152
1153 return 0;
1154}
1155
1156static int atmel_hsmc_nand_ecc_init(struct atmel_nand *nand)
1157{
1158 struct nand_chip *chip = &nand->base;
1159 int ret;
1160
1161 ret = atmel_nand_ecc_init(nand);
1162 if (ret)
1163 return ret;
1164
1165 if (chip->ecc.mode != NAND_ECC_HW)
1166 return 0;
1167
1168 /* Adjust the ECC operations for the HSMC IP. */
1169 chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1170 chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1171 chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1172 chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1173 chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
1174
1175 return 0;
1176}
1177
1178static void atmel_nand_init(struct atmel_nand_controller *nc,
1179 struct atmel_nand *nand)
1180{
1181 struct nand_chip *chip = &nand->base;
1182 struct mtd_info *mtd = nand_to_mtd(chip);
1183
1184 mtd->dev.parent = nc->dev;
1185 nand->base.controller = &nc->base;
1186
1187 chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1188 chip->read_byte = atmel_nand_read_byte;
1189 chip->read_word = atmel_nand_read_word;
1190 chip->write_byte = atmel_nand_write_byte;
1191 chip->read_buf = atmel_nand_read_buf;
1192 chip->write_buf = atmel_nand_write_buf;
1193 chip->select_chip = atmel_nand_select_chip;
1194
1195 /* Some NANDs require a longer delay than the default one (20us). */
1196 chip->chip_delay = 40;
1197
1198 /*
1199 * Use a bounce buffer when the buffer passed by the MTD user is not
1200 * suitable for DMA.
1201 */
1202 if (nc->dmac)
1203 chip->options |= NAND_USE_BOUNCE_BUFFER;
1204
1205 /* Default to HW ECC if pmecc is available. */
1206 if (nc->pmecc)
1207 chip->ecc.mode = NAND_ECC_HW;
1208}
1209
1210static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1211 struct atmel_nand *nand)
1212{
1213 struct nand_chip *chip = &nand->base;
1214 struct atmel_smc_nand_controller *smc_nc;
1215 int i;
1216
1217 atmel_nand_init(nc, nand);
1218
1219 smc_nc = to_smc_nand_controller(chip->controller);
1220 if (!smc_nc->matrix)
1221 return;
1222
1223 /* Attach the CS to the NAND Flash logic. */
1224 for (i = 0; i < nand->numcs; i++)
1225 regmap_update_bits(smc_nc->matrix, smc_nc->ebi_csa_offs,
1226 BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1227}
1228
1229static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1230 struct atmel_nand *nand)
1231{
1232 struct nand_chip *chip = &nand->base;
1233
1234 atmel_nand_init(nc, nand);
1235
1236 /* Overload some methods for the HSMC controller. */
1237 chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1238 chip->select_chip = atmel_hsmc_nand_select_chip;
1239}
1240
1241static int atmel_nand_detect(struct atmel_nand *nand)
1242{
1243 struct nand_chip *chip = &nand->base;
1244 struct mtd_info *mtd = nand_to_mtd(chip);
1245 struct atmel_nand_controller *nc;
1246 int ret;
1247
1248 nc = to_nand_controller(chip->controller);
1249
1250 ret = nand_scan_ident(mtd, nand->numcs, NULL);
1251 if (ret)
1252 dev_err(nc->dev, "nand_scan_ident() failed: %d\n", ret);
1253
1254 return ret;
1255}
1256
1257static int atmel_nand_unregister(struct atmel_nand *nand)
1258{
1259 struct nand_chip *chip = &nand->base;
1260 struct mtd_info *mtd = nand_to_mtd(chip);
1261 int ret;
1262
1263 ret = mtd_device_unregister(mtd);
1264 if (ret)
1265 return ret;
1266
1267 nand_cleanup(chip);
1268 list_del(&nand->node);
1269
1270 return 0;
1271}
1272
1273static int atmel_nand_register(struct atmel_nand *nand)
1274{
1275 struct nand_chip *chip = &nand->base;
1276 struct mtd_info *mtd = nand_to_mtd(chip);
1277 struct atmel_nand_controller *nc;
1278 int ret;
1279
1280 nc = to_nand_controller(chip->controller);
1281
1282 if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1283 /*
1284 * We keep the MTD name unchanged to avoid breaking platforms
1285 * where the MTD cmdline parser is used and the bootloader
1286 * has not been updated to use the new naming scheme.
1287 */
1288 mtd->name = "atmel_nand";
1289 } else if (!mtd->name) {
1290 /*
1291 * If the new bindings are used and the bootloader has not been
1292 * updated to pass a new mtdparts parameter on the cmdline, you
1293 * should define the following property in your nand node:
1294 *
1295 * label = "atmel_nand";
1296 *
1297 * This way, mtd->name will be set by the core when
1298 * nand_set_flash_node() is called.
1299 */
1300 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
1301 "%s:nand.%d", dev_name(nc->dev),
1302 nand->cs[0].id);
1303 if (!mtd->name) {
1304 dev_err(nc->dev, "Failed to allocate mtd->name\n");
1305 return -ENOMEM;
1306 }
1307 }
1308
1309 ret = nand_scan_tail(mtd);
1310 if (ret) {
1311 dev_err(nc->dev, "nand_scan_tail() failed: %d\n", ret);
1312 return ret;
1313 }
1314
1315 ret = mtd_device_register(mtd, NULL, 0);
1316 if (ret) {
1317 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1318 nand_cleanup(chip);
1319 return ret;
1320 }
1321
1322 list_add_tail(&nand->node, &nc->chips);
1323
1324 return 0;
1325}
1326
1327static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1328 struct device_node *np,
1329 int reg_cells)
1330{
1331 struct atmel_nand *nand;
1332 struct gpio_desc *gpio;
1333 int numcs, ret, i;
1334
1335 numcs = of_property_count_elems_of_size(np, "reg",
1336 reg_cells * sizeof(u32));
1337 if (numcs < 1) {
1338 dev_err(nc->dev, "Missing or invalid reg property\n");
1339 return ERR_PTR(-EINVAL);
1340 }
1341
1342 nand = devm_kzalloc(nc->dev,
1343 sizeof(*nand) + (numcs * sizeof(*nand->cs)),
1344 GFP_KERNEL);
1345 if (!nand) {
1346 dev_err(nc->dev, "Failed to allocate NAND object\n");
1347 return ERR_PTR(-ENOMEM);
1348 }
1349
1350 nand->numcs = numcs;
1351
1352 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "det", 0,
1353 &np->fwnode, GPIOD_IN,
1354 "nand-det");
1355 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1356 dev_err(nc->dev,
1357 "Failed to get detect gpio (err = %ld)\n",
1358 PTR_ERR(gpio));
1359 return ERR_CAST(gpio);
1360 }
1361
1362 if (!IS_ERR(gpio))
1363 nand->cdgpio = gpio;
1364
1365 for (i = 0; i < numcs; i++) {
1366 struct resource res;
1367 u32 val;
1368
1369 ret = of_address_to_resource(np, 0, &res);
1370 if (ret) {
1371 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1372 ret);
1373 return ERR_PTR(ret);
1374 }
1375
1376 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1377 &val);
1378 if (ret) {
1379 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1380 ret);
1381 return ERR_PTR(ret);
1382 }
1383
1384 nand->cs[i].id = val;
1385
1386 nand->cs[i].io.dma = res.start;
1387 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1388 if (IS_ERR(nand->cs[i].io.virt))
1389 return ERR_CAST(nand->cs[i].io.virt);
1390
1391 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1392 if (val > ATMEL_NFC_MAX_RB_ID)
1393 return ERR_PTR(-EINVAL);
1394
1395 nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1396 nand->cs[i].rb.id = val;
1397 } else {
1398 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev,
1399 "rb", i, &np->fwnode,
1400 GPIOD_IN, "nand-rb");
1401 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1402 dev_err(nc->dev,
1403 "Failed to get R/B gpio (err = %ld)\n",
1404 PTR_ERR(gpio));
1405 return ERR_CAST(gpio);
1406 }
1407
1408 if (!IS_ERR(gpio)) {
1409 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1410 nand->cs[i].rb.gpio = gpio;
1411 }
1412 }
1413
1414 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "cs",
1415 i, &np->fwnode,
1416 GPIOD_OUT_HIGH,
1417 "nand-cs");
1418 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1419 dev_err(nc->dev,
1420 "Failed to get CS gpio (err = %ld)\n",
1421 PTR_ERR(gpio));
1422 return ERR_CAST(gpio);
1423 }
1424
1425 if (!IS_ERR(gpio))
1426 nand->cs[i].csgpio = gpio;
1427 }
1428
1429 nand_set_flash_node(&nand->base, np);
1430
1431 return nand;
1432}
1433
1434static int
1435atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1436 struct atmel_nand *nand)
1437{
1438 int ret;
1439
1440 /* No card inserted, skip this NAND. */
1441 if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1442 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1443 return 0;
1444 }
1445
1446 nc->caps->ops->nand_init(nc, nand);
1447
1448 ret = atmel_nand_detect(nand);
1449 if (ret)
1450 return ret;
1451
1452 ret = nc->caps->ops->ecc_init(nand);
1453 if (ret)
1454 return ret;
1455
1456 return atmel_nand_register(nand);
1457}
1458
1459static int
1460atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1461{
1462 struct atmel_nand *nand, *tmp;
1463 int ret;
1464
1465 list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1466 ret = atmel_nand_unregister(nand);
1467 if (ret)
1468 return ret;
1469 }
1470
1471 return 0;
1472}
1473
1474static int
1475atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1476{
1477 struct device *dev = nc->dev;
1478 struct platform_device *pdev = to_platform_device(dev);
1479 struct atmel_nand *nand;
1480 struct gpio_desc *gpio;
1481 struct resource *res;
1482
1483 /*
1484 * Legacy bindings only allow connecting a single NAND with a unique CS
1485 * line to the controller.
1486 */
1487 nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1488 GFP_KERNEL);
1489 if (!nand)
1490 return -ENOMEM;
1491
1492 nand->numcs = 1;
1493
1494 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1495 nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1496 if (IS_ERR(nand->cs[0].io.virt))
1497 return PTR_ERR(nand->cs[0].io.virt);
1498
1499 nand->cs[0].io.dma = res->start;
1500
1501 /*
1502 * The old driver was hardcoding the CS id to 3 for all sama5
1503 * controllers. Since this id is only meaningful for the sama5
1504 * controller we can safely assign this id to 3 no matter the
1505 * controller.
1506 * If one wants to connect a NAND to a different CS line, he will
1507 * have to use the new bindings.
1508 */
1509 nand->cs[0].id = 3;
1510
1511 /* R/B GPIO. */
1512 gpio = devm_gpiod_get_index_optional(dev, NULL, 0, GPIOD_IN);
1513 if (IS_ERR(gpio)) {
1514 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1515 PTR_ERR(gpio));
1516 return PTR_ERR(gpio);
1517 }
1518
1519 if (gpio) {
1520 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1521 nand->cs[0].rb.gpio = gpio;
1522 }
1523
1524 /* CS GPIO. */
1525 gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1526 if (IS_ERR(gpio)) {
1527 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1528 PTR_ERR(gpio));
1529 return PTR_ERR(gpio);
1530 }
1531
1532 nand->cs[0].csgpio = gpio;
1533
1534 /* Card detect GPIO. */
1535 gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1536 if (IS_ERR(gpio)) {
1537 dev_err(dev,
1538 "Failed to get detect gpio (err = %ld)\n",
1539 PTR_ERR(gpio));
1540 return PTR_ERR(gpio);
1541 }
1542
1543 nand->cdgpio = gpio;
1544
1545 nand_set_flash_node(&nand->base, nc->dev->of_node);
1546
1547 return atmel_nand_controller_add_nand(nc, nand);
1548}
1549
1550static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1551{
1552 struct device_node *np, *nand_np;
1553 struct device *dev = nc->dev;
1554 int ret, reg_cells;
1555 u32 val;
1556
1557 /* We do not retrieve the SMC syscon when parsing old DTs. */
1558 if (nc->caps->legacy_of_bindings)
1559 return atmel_nand_controller_legacy_add_nands(nc);
1560
1561 np = dev->of_node;
1562
1563 ret = of_property_read_u32(np, "#address-cells", &val);
1564 if (ret) {
1565 dev_err(dev, "missing #address-cells property\n");
1566 return ret;
1567 }
1568
1569 reg_cells = val;
1570
1571 ret = of_property_read_u32(np, "#size-cells", &val);
1572 if (ret) {
1573 dev_err(dev, "missing #address-cells property\n");
1574 return ret;
1575 }
1576
1577 reg_cells += val;
1578
1579 for_each_child_of_node(np, nand_np) {
1580 struct atmel_nand *nand;
1581
1582 nand = atmel_nand_create(nc, nand_np, reg_cells);
1583 if (IS_ERR(nand)) {
1584 ret = PTR_ERR(nand);
1585 goto err;
1586 }
1587
1588 ret = atmel_nand_controller_add_nand(nc, nand);
1589 if (ret)
1590 goto err;
1591 }
1592
1593 return 0;
1594
1595err:
1596 atmel_nand_controller_remove_nands(nc);
1597
1598 return ret;
1599}
1600
1601static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1602{
1603 if (nc->dmac)
1604 dma_release_channel(nc->dmac);
1605
1606 clk_put(nc->mck);
1607}
1608
1609static const struct of_device_id atmel_matrix_of_ids[] = {
1610 {
1611 .compatible = "atmel,at91sam9260-matrix",
1612 .data = (void *)AT91SAM9260_MATRIX_EBICSA,
1613 },
1614 {
1615 .compatible = "atmel,at91sam9261-matrix",
1616 .data = (void *)AT91SAM9261_MATRIX_EBICSA,
1617 },
1618 {
1619 .compatible = "atmel,at91sam9263-matrix",
1620 .data = (void *)AT91SAM9263_MATRIX_EBI0CSA,
1621 },
1622 {
1623 .compatible = "atmel,at91sam9rl-matrix",
1624 .data = (void *)AT91SAM9RL_MATRIX_EBICSA,
1625 },
1626 {
1627 .compatible = "atmel,at91sam9g45-matrix",
1628 .data = (void *)AT91SAM9G45_MATRIX_EBICSA,
1629 },
1630 {
1631 .compatible = "atmel,at91sam9n12-matrix",
1632 .data = (void *)AT91SAM9N12_MATRIX_EBICSA,
1633 },
1634 {
1635 .compatible = "atmel,at91sam9x5-matrix",
1636 .data = (void *)AT91SAM9X5_MATRIX_EBICSA,
1637 },
1638};
1639
1640static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
1641 struct platform_device *pdev,
1642 const struct atmel_nand_controller_caps *caps)
1643{
1644 struct device *dev = &pdev->dev;
1645 struct device_node *np = dev->of_node;
1646 int ret;
1647
1648 nand_hw_control_init(&nc->base);
1649 INIT_LIST_HEAD(&nc->chips);
1650 nc->dev = dev;
1651 nc->caps = caps;
1652
1653 platform_set_drvdata(pdev, nc);
1654
1655 nc->pmecc = devm_atmel_pmecc_get(dev);
1656 if (IS_ERR(nc->pmecc)) {
1657 ret = PTR_ERR(nc->pmecc);
1658 if (ret != -EPROBE_DEFER)
1659 dev_err(dev, "Could not get PMECC object (err = %d)\n",
1660 ret);
1661 return ret;
1662 }
1663
1664 if (nc->caps->has_dma) {
1665 dma_cap_mask_t mask;
1666
1667 dma_cap_zero(mask);
1668 dma_cap_set(DMA_MEMCPY, mask);
1669
1670 nc->dmac = dma_request_channel(mask, NULL, NULL);
1671 if (!nc->dmac)
1672 dev_err(nc->dev, "Failed to request DMA channel\n");
1673 }
1674
1675 /* We do not retrieve the SMC syscon when parsing old DTs. */
1676 if (nc->caps->legacy_of_bindings)
1677 return 0;
1678
1679 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
1680 if (!np) {
1681 dev_err(dev, "Missing or invalid atmel,smc property\n");
1682 return -EINVAL;
1683 }
1684
1685 nc->smc = syscon_node_to_regmap(np);
1686 of_node_put(np);
1687 if (IS_ERR(nc->smc)) {
1688 ret = IS_ERR(nc->smc);
1689 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
1690 return ret;
1691 }
1692
1693 return 0;
1694}
1695
1696static int
1697atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
1698{
1699 struct device *dev = nc->base.dev;
1700 const struct of_device_id *match;
1701 struct device_node *np;
1702 int ret;
1703
1704 /* We do not retrieve the matrix syscon when parsing old DTs. */
1705 if (nc->base.caps->legacy_of_bindings)
1706 return 0;
1707
1708 np = of_parse_phandle(dev->parent->of_node, "atmel,matrix", 0);
1709 if (!np)
1710 return 0;
1711
1712 match = of_match_node(atmel_matrix_of_ids, np);
1713 if (!match) {
1714 of_node_put(np);
1715 return 0;
1716 }
1717
1718 nc->matrix = syscon_node_to_regmap(np);
1719 of_node_put(np);
1720 if (IS_ERR(nc->matrix)) {
1721 ret = IS_ERR(nc->matrix);
1722 dev_err(dev, "Could not get Matrix regmap (err = %d)\n", ret);
1723 return ret;
1724 }
1725
1726 nc->ebi_csa_offs = (unsigned int)match->data;
1727
1728 /*
1729 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
1730 * add 4 to ->ebi_csa_offs.
1731 */
1732 if (of_device_is_compatible(dev->parent->of_node,
1733 "atmel,at91sam9263-ebi1"))
1734 nc->ebi_csa_offs += 4;
1735
1736 return 0;
1737}
1738
1739static int
1740atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
1741{
1742 struct regmap_config regmap_conf = {
1743 .reg_bits = 32,
1744 .val_bits = 32,
1745 .reg_stride = 4,
1746 };
1747
1748 struct device *dev = nc->base.dev;
1749 struct device_node *nand_np, *nfc_np;
1750 void __iomem *iomem;
1751 struct resource res;
1752 int ret;
1753
1754 nand_np = dev->of_node;
1755 nfc_np = of_find_compatible_node(dev->of_node, NULL,
1756 "atmel,sama5d3-nfc");
1757
1758 nc->clk = of_clk_get(nfc_np, 0);
1759 if (IS_ERR(nc->clk)) {
1760 ret = PTR_ERR(nc->clk);
1761 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
1762 ret);
1763 goto out;
1764 }
1765
1766 ret = clk_prepare_enable(nc->clk);
1767 if (ret) {
1768 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
1769 ret);
1770 goto out;
1771 }
1772
1773 nc->irq = of_irq_get(nand_np, 0);
1774 if (nc->irq < 0) {
1775 ret = nc->irq;
1776 if (ret != -EPROBE_DEFER)
1777 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
1778 ret);
1779 goto out;
1780 }
1781
1782 ret = of_address_to_resource(nfc_np, 0, &res);
1783 if (ret) {
1784 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
1785 ret);
1786 goto out;
1787 }
1788
1789 iomem = devm_ioremap_resource(dev, &res);
1790 if (IS_ERR(iomem)) {
1791 ret = PTR_ERR(iomem);
1792 goto out;
1793 }
1794
1795 regmap_conf.name = "nfc-io";
1796 regmap_conf.max_register = resource_size(&res) - 4;
1797 nc->io = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
1798 if (IS_ERR(nc->io)) {
1799 ret = PTR_ERR(nc->io);
1800 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
1801 ret);
1802 goto out;
1803 }
1804
1805 ret = of_address_to_resource(nfc_np, 1, &res);
1806 if (ret) {
1807 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
1808 ret);
1809 goto out;
1810 }
1811
1812 iomem = devm_ioremap_resource(dev, &res);
1813 if (IS_ERR(iomem)) {
1814 ret = PTR_ERR(iomem);
1815 goto out;
1816 }
1817
1818 regmap_conf.name = "smc";
1819 regmap_conf.max_register = resource_size(&res) - 4;
1820 nc->base.smc = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
1821 if (IS_ERR(nc->base.smc)) {
1822 ret = PTR_ERR(nc->base.smc);
1823 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
1824 ret);
1825 goto out;
1826 }
1827
1828 ret = of_address_to_resource(nfc_np, 2, &res);
1829 if (ret) {
1830 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
1831 ret);
1832 goto out;
1833 }
1834
1835 nc->sram.virt = devm_ioremap_resource(dev, &res);
1836 if (IS_ERR(nc->sram.virt)) {
1837 ret = PTR_ERR(nc->sram.virt);
1838 goto out;
1839 }
1840
1841 nc->sram.dma = res.start;
1842
1843out:
1844 of_node_put(nfc_np);
1845
1846 return ret;
1847}
1848
1849static int
1850atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
1851{
1852 struct device *dev = nc->base.dev;
1853 struct device_node *np;
1854 int ret;
1855
1856 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
1857 if (!np) {
1858 dev_err(dev, "Missing or invalid atmel,smc property\n");
1859 return -EINVAL;
1860 }
1861
1862 nc->irq = of_irq_get(np, 0);
1863 of_node_put(np);
1864 if (nc->irq < 0) {
1865 if (nc->irq != -EPROBE_DEFER)
1866 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
1867 nc->irq);
1868 return nc->irq;
1869 }
1870
1871 np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
1872 if (!np) {
1873 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
1874 return -EINVAL;
1875 }
1876
1877 nc->io = syscon_node_to_regmap(np);
1878 of_node_put(np);
1879 if (IS_ERR(nc->io)) {
1880 ret = PTR_ERR(nc->io);
1881 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
1882 return ret;
1883 }
1884
1885 nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
1886 "atmel,nfc-sram", 0);
1887 if (!nc->sram.pool) {
1888 dev_err(nc->base.dev, "Missing SRAM\n");
1889 return -ENOMEM;
1890 }
1891
1892 nc->sram.virt = gen_pool_dma_alloc(nc->sram.pool,
1893 ATMEL_NFC_SRAM_SIZE,
1894 &nc->sram.dma);
1895 if (!nc->sram.virt) {
1896 dev_err(nc->base.dev,
1897 "Could not allocate memory from the NFC SRAM pool\n");
1898 return -ENOMEM;
1899 }
1900
1901 return 0;
1902}
1903
1904static int
1905atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
1906{
1907 struct atmel_hsmc_nand_controller *hsmc_nc;
1908 int ret;
1909
1910 ret = atmel_nand_controller_remove_nands(nc);
1911 if (ret)
1912 return ret;
1913
1914 hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
1915 if (hsmc_nc->sram.pool)
1916 gen_pool_free(hsmc_nc->sram.pool,
1917 (unsigned long)hsmc_nc->sram.virt,
1918 ATMEL_NFC_SRAM_SIZE);
1919
1920 if (hsmc_nc->clk) {
1921 clk_disable_unprepare(hsmc_nc->clk);
1922 clk_put(hsmc_nc->clk);
1923 }
1924
1925 atmel_nand_controller_cleanup(nc);
1926
1927 return 0;
1928}
1929
1930static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
1931 const struct atmel_nand_controller_caps *caps)
1932{
1933 struct device *dev = &pdev->dev;
1934 struct atmel_hsmc_nand_controller *nc;
1935 int ret;
1936
1937 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
1938 if (!nc)
1939 return -ENOMEM;
1940
1941 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
1942 if (ret)
1943 return ret;
1944
1945 if (caps->legacy_of_bindings)
1946 ret = atmel_hsmc_nand_controller_legacy_init(nc);
1947 else
1948 ret = atmel_hsmc_nand_controller_init(nc);
1949
1950 if (ret)
1951 return ret;
1952
1953 /* Make sure all irqs are masked before registering our IRQ handler. */
1954 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
1955 ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
1956 IRQF_SHARED, "nfc", nc);
1957 if (ret) {
1958 dev_err(dev,
1959 "Could not get register NFC interrupt handler (err = %d)\n",
1960 ret);
1961 goto err;
1962 }
1963
1964 /* Initial NFC configuration. */
1965 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
1966 ATMEL_HSMC_NFC_CFG_DTO_MAX);
1967
1968 ret = atmel_nand_controller_add_nands(&nc->base);
1969 if (ret)
1970 goto err;
1971
1972 return 0;
1973
1974err:
1975 atmel_hsmc_nand_controller_remove(&nc->base);
1976
1977 return ret;
1978}
1979
1980static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
1981 .probe = atmel_hsmc_nand_controller_probe,
1982 .remove = atmel_hsmc_nand_controller_remove,
1983 .ecc_init = atmel_hsmc_nand_ecc_init,
1984 .nand_init = atmel_hsmc_nand_init,
1985};
1986
1987static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
1988 .has_dma = true,
1989 .ale_offs = BIT(21),
1990 .cle_offs = BIT(22),
1991 .ops = &atmel_hsmc_nc_ops,
1992};
1993
1994/* Only used to parse old bindings. */
1995static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
1996 .has_dma = true,
1997 .ale_offs = BIT(21),
1998 .cle_offs = BIT(22),
1999 .ops = &atmel_hsmc_nc_ops,
2000 .legacy_of_bindings = true,
2001};
2002
2003static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2004 const struct atmel_nand_controller_caps *caps)
2005{
2006 struct device *dev = &pdev->dev;
2007 struct atmel_smc_nand_controller *nc;
2008 int ret;
2009
2010 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2011 if (!nc)
2012 return -ENOMEM;
2013
2014 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2015 if (ret)
2016 return ret;
2017
2018 ret = atmel_smc_nand_controller_init(nc);
2019 if (ret)
2020 return ret;
2021
2022 return atmel_nand_controller_add_nands(&nc->base);
2023}
2024
2025static int
2026atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2027{
2028 int ret;
2029
2030 ret = atmel_nand_controller_remove_nands(nc);
2031 if (ret)
2032 return ret;
2033
2034 atmel_nand_controller_cleanup(nc);
2035
2036 return 0;
2037}
2038
2039static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2040 .probe = atmel_smc_nand_controller_probe,
2041 .remove = atmel_smc_nand_controller_remove,
2042 .ecc_init = atmel_nand_ecc_init,
2043 .nand_init = atmel_smc_nand_init,
2044};
2045
2046static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2047 .ale_offs = BIT(21),
2048 .cle_offs = BIT(22),
2049 .ops = &atmel_smc_nc_ops,
2050};
2051
2052static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2053 .ale_offs = BIT(22),
2054 .cle_offs = BIT(21),
2055 .ops = &atmel_smc_nc_ops,
2056};
2057
2058static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2059 .has_dma = true,
2060 .ale_offs = BIT(21),
2061 .cle_offs = BIT(22),
2062 .ops = &atmel_smc_nc_ops,
2063};
2064
2065/* Only used to parse old bindings. */
2066static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2067 .ale_offs = BIT(21),
2068 .cle_offs = BIT(22),
2069 .ops = &atmel_smc_nc_ops,
2070 .legacy_of_bindings = true,
2071};
2072
2073static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2074 .ale_offs = BIT(22),
2075 .cle_offs = BIT(21),
2076 .ops = &atmel_smc_nc_ops,
2077 .legacy_of_bindings = true,
2078};
2079
2080static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2081 .has_dma = true,
2082 .ale_offs = BIT(21),
2083 .cle_offs = BIT(22),
2084 .ops = &atmel_smc_nc_ops,
2085 .legacy_of_bindings = true,
2086};
2087
2088static const struct of_device_id atmel_nand_controller_of_ids[] = {
2089 {
2090 .compatible = "atmel,at91rm9200-nand-controller",
2091 .data = &atmel_rm9200_nc_caps,
2092 },
2093 {
2094 .compatible = "atmel,at91sam9260-nand-controller",
2095 .data = &atmel_rm9200_nc_caps,
2096 },
2097 {
2098 .compatible = "atmel,at91sam9261-nand-controller",
2099 .data = &atmel_sam9261_nc_caps,
2100 },
2101 {
2102 .compatible = "atmel,at91sam9g45-nand-controller",
2103 .data = &atmel_sam9g45_nc_caps,
2104 },
2105 {
2106 .compatible = "atmel,sama5d3-nand-controller",
2107 .data = &atmel_sama5_nc_caps,
2108 },
2109 /* Support for old/deprecated bindings: */
2110 {
2111 .compatible = "atmel,at91rm9200-nand",
2112 .data = &atmel_rm9200_nand_caps,
2113 },
2114 {
2115 .compatible = "atmel,sama5d4-nand",
2116 .data = &atmel_rm9200_nand_caps,
2117 },
2118 {
2119 .compatible = "atmel,sama5d2-nand",
2120 .data = &atmel_rm9200_nand_caps,
2121 },
2122 { /* sentinel */ },
2123};
2124MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2125
2126static int atmel_nand_controller_probe(struct platform_device *pdev)
2127{
2128 const struct atmel_nand_controller_caps *caps;
2129
2130 if (pdev->id_entry)
2131 caps = (void *)pdev->id_entry->driver_data;
2132 else
2133 caps = of_device_get_match_data(&pdev->dev);
2134
2135 if (!caps) {
2136 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2137 return -EINVAL;
2138 }
2139
2140 if (caps->legacy_of_bindings) {
2141 u32 ale_offs = 21;
2142
2143 /*
2144 * If we are parsing legacy DT props and the DT contains a
2145 * valid NFC node, forward the request to the sama5 logic.
2146 */
2147 if (of_find_compatible_node(pdev->dev.of_node, NULL,
2148 "atmel,sama5d3-nfc"))
2149 caps = &atmel_sama5_nand_caps;
2150
2151 /*
2152 * Even if the compatible says we are dealing with an
2153 * at91rm9200 controller, the atmel,nand-has-dma specify that
2154 * this controller supports DMA, which means we are in fact
2155 * dealing with an at91sam9g45+ controller.
2156 */
2157 if (!caps->has_dma &&
2158 of_property_read_bool(pdev->dev.of_node,
2159 "atmel,nand-has-dma"))
2160 caps = &atmel_sam9g45_nand_caps;
2161
2162 /*
2163 * All SoCs except the at91sam9261 are assigning ALE to A21 and
2164 * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2165 * actually dealing with an at91sam9261 controller.
2166 */
2167 of_property_read_u32(pdev->dev.of_node,
2168 "atmel,nand-addr-offset", &ale_offs);
2169 if (ale_offs != 21)
2170 caps = &atmel_sam9261_nand_caps;
2171 }
2172
2173 return caps->ops->probe(pdev, caps);
2174}
2175
2176static int atmel_nand_controller_remove(struct platform_device *pdev)
2177{
2178 struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2179
2180 return nc->caps->ops->remove(nc);
2181}
2182
2183static struct platform_driver atmel_nand_controller_driver = {
2184 .driver = {
2185 .name = "atmel-nand-controller",
2186 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2187 },
2188 .probe = atmel_nand_controller_probe,
2189 .remove = atmel_nand_controller_remove,
2190};
2191module_platform_driver(atmel_nand_controller_driver);
2192
2193MODULE_LICENSE("GPL");
2194MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2195MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2196MODULE_ALIAS("platform:atmel-nand-controller");
diff --git a/drivers/mtd/nand/atmel/pmecc.c b/drivers/mtd/nand/atmel/pmecc.c
new file mode 100644
index 000000000000..55a8ee5306ea
--- /dev/null
+++ b/drivers/mtd/nand/atmel/pmecc.c
@@ -0,0 +1,1020 @@
1/*
2 * Copyright 2017 ATMEL
3 * Copyright 2017 Free Electrons
4 *
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
6 *
7 * Derived from the atmel_nand.c driver which contained the following
8 * copyrights:
9 *
10 * Copyright 2003 Rick Bronson
11 *
12 * Derived from drivers/mtd/nand/autcpu12.c
13 * Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
14 *
15 * Derived from drivers/mtd/spia.c
16 * Copyright 2000 Steven J. Hill (sjhill@cotw.com)
17 *
18 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
19 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
20 *
21 * Derived from Das U-Boot source code
22 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
23 * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
24 *
25 * Add Programmable Multibit ECC support for various AT91 SoC
26 * Copyright 2012 ATMEL, Hong Xu
27 *
28 * Add Nand Flash Controller support for SAMA5 SoC
29 * Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
30 *
31 * This program is free software; you can redistribute it and/or modify
32 * it under the terms of the GNU General Public License version 2 as
33 * published by the Free Software Foundation.
34 *
35 * The PMECC is an hardware assisted BCH engine, which means part of the
36 * ECC algorithm is left to the software. The hardware/software repartition
37 * is explained in the "PMECC Controller Functional Description" chapter in
38 * Atmel datasheets, and some of the functions in this file are directly
39 * implementing the algorithms described in the "Software Implementation"
40 * sub-section.
41 *
42 * TODO: it seems that the software BCH implementation in lib/bch.c is already
43 * providing some of the logic we are implementing here. It would be smart
44 * to expose the needed lib/bch.c helpers/functions and re-use them here.
45 */
46
47#include <linux/genalloc.h>
48#include <linux/iopoll.h>
49#include <linux/module.h>
50#include <linux/mtd/nand.h>
51#include <linux/of_irq.h>
52#include <linux/of_platform.h>
53#include <linux/platform_device.h>
54#include <linux/slab.h>
55
56#include "pmecc.h"
57
58/* Galois field dimension */
59#define PMECC_GF_DIMENSION_13 13
60#define PMECC_GF_DIMENSION_14 14
61
62/* Primitive Polynomial used by PMECC */
63#define PMECC_GF_13_PRIMITIVE_POLY 0x201b
64#define PMECC_GF_14_PRIMITIVE_POLY 0x4443
65
66#define PMECC_LOOKUP_TABLE_SIZE_512 0x2000
67#define PMECC_LOOKUP_TABLE_SIZE_1024 0x4000
68
69/* Time out value for reading PMECC status register */
70#define PMECC_MAX_TIMEOUT_MS 100
71
72/* PMECC Register Definitions */
73#define ATMEL_PMECC_CFG 0x0
74#define PMECC_CFG_BCH_STRENGTH(x) (x)
75#define PMECC_CFG_BCH_STRENGTH_MASK GENMASK(2, 0)
76#define PMECC_CFG_SECTOR512 (0 << 4)
77#define PMECC_CFG_SECTOR1024 (1 << 4)
78#define PMECC_CFG_NSECTORS(x) ((fls(x) - 1) << 8)
79#define PMECC_CFG_READ_OP (0 << 12)
80#define PMECC_CFG_WRITE_OP (1 << 12)
81#define PMECC_CFG_SPARE_ENABLE BIT(16)
82#define PMECC_CFG_AUTO_ENABLE BIT(20)
83
84#define ATMEL_PMECC_SAREA 0x4
85#define ATMEL_PMECC_SADDR 0x8
86#define ATMEL_PMECC_EADDR 0xc
87
88#define ATMEL_PMECC_CLK 0x10
89#define PMECC_CLK_133MHZ (2 << 0)
90
91#define ATMEL_PMECC_CTRL 0x14
92#define PMECC_CTRL_RST BIT(0)
93#define PMECC_CTRL_DATA BIT(1)
94#define PMECC_CTRL_USER BIT(2)
95#define PMECC_CTRL_ENABLE BIT(4)
96#define PMECC_CTRL_DISABLE BIT(5)
97
98#define ATMEL_PMECC_SR 0x18
99#define PMECC_SR_BUSY BIT(0)
100#define PMECC_SR_ENABLE BIT(4)
101
102#define ATMEL_PMECC_IER 0x1c
103#define ATMEL_PMECC_IDR 0x20
104#define ATMEL_PMECC_IMR 0x24
105#define ATMEL_PMECC_ISR 0x28
106#define PMECC_ERROR_INT BIT(0)
107
108#define ATMEL_PMECC_ECC(sector, n) \
109 ((((sector) + 1) * 0x40) + (n))
110
111#define ATMEL_PMECC_REM(sector, n) \
112 ((((sector) + 1) * 0x40) + ((n) * 4) + 0x200)
113
114/* PMERRLOC Register Definitions */
115#define ATMEL_PMERRLOC_ELCFG 0x0
116#define PMERRLOC_ELCFG_SECTOR_512 (0 << 0)
117#define PMERRLOC_ELCFG_SECTOR_1024 (1 << 0)
118#define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16)
119
120#define ATMEL_PMERRLOC_ELPRIM 0x4
121#define ATMEL_PMERRLOC_ELEN 0x8
122#define ATMEL_PMERRLOC_ELDIS 0xc
123#define PMERRLOC_DISABLE BIT(0)
124
125#define ATMEL_PMERRLOC_ELSR 0x10
126#define PMERRLOC_ELSR_BUSY BIT(0)
127
128#define ATMEL_PMERRLOC_ELIER 0x14
129#define ATMEL_PMERRLOC_ELIDR 0x18
130#define ATMEL_PMERRLOC_ELIMR 0x1c
131#define ATMEL_PMERRLOC_ELISR 0x20
132#define PMERRLOC_ERR_NUM_MASK GENMASK(12, 8)
133#define PMERRLOC_CALC_DONE BIT(0)
134
135#define ATMEL_PMERRLOC_SIGMA(x) (((x) * 0x4) + 0x28)
136
137#define ATMEL_PMERRLOC_EL(offs, x) (((x) * 0x4) + (offs))
138
139struct atmel_pmecc_gf_tables {
140 u16 *alpha_to;
141 u16 *index_of;
142};
143
144struct atmel_pmecc_caps {
145 const int *strengths;
146 int nstrengths;
147 int el_offset;
148 bool correct_erased_chunks;
149};
150
151struct atmel_pmecc {
152 struct device *dev;
153 const struct atmel_pmecc_caps *caps;
154
155 struct {
156 void __iomem *base;
157 void __iomem *errloc;
158 } regs;
159
160 struct mutex lock;
161};
162
163struct atmel_pmecc_user_conf_cache {
164 u32 cfg;
165 u32 sarea;
166 u32 saddr;
167 u32 eaddr;
168};
169
170struct atmel_pmecc_user {
171 struct atmel_pmecc_user_conf_cache cache;
172 struct atmel_pmecc *pmecc;
173 const struct atmel_pmecc_gf_tables *gf_tables;
174 int eccbytes;
175 s16 *partial_syn;
176 s16 *si;
177 s16 *lmu;
178 s16 *smu;
179 s32 *mu;
180 s32 *dmu;
181 s32 *delta;
182 u32 isr;
183};
184
185static DEFINE_MUTEX(pmecc_gf_tables_lock);
186static const struct atmel_pmecc_gf_tables *pmecc_gf_tables_512;
187static const struct atmel_pmecc_gf_tables *pmecc_gf_tables_1024;
188
189static inline int deg(unsigned int poly)
190{
191 /* polynomial degree is the most-significant bit index */
192 return fls(poly) - 1;
193}
194
195static int atmel_pmecc_build_gf_tables(int mm, unsigned int poly,
196 struct atmel_pmecc_gf_tables *gf_tables)
197{
198 unsigned int i, x = 1;
199 const unsigned int k = BIT(deg(poly));
200 unsigned int nn = BIT(mm) - 1;
201
202 /* primitive polynomial must be of degree m */
203 if (k != (1u << mm))
204 return -EINVAL;
205
206 for (i = 0; i < nn; i++) {
207 gf_tables->alpha_to[i] = x;
208 gf_tables->index_of[x] = i;
209 if (i && (x == 1))
210 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
211 return -EINVAL;
212 x <<= 1;
213 if (x & k)
214 x ^= poly;
215 }
216 gf_tables->alpha_to[nn] = 1;
217 gf_tables->index_of[0] = 0;
218
219 return 0;
220}
221
222static const struct atmel_pmecc_gf_tables *
223atmel_pmecc_create_gf_tables(const struct atmel_pmecc_user_req *req)
224{
225 struct atmel_pmecc_gf_tables *gf_tables;
226 unsigned int poly, degree, table_size;
227 int ret;
228
229 if (req->ecc.sectorsize == 512) {
230 degree = PMECC_GF_DIMENSION_13;
231 poly = PMECC_GF_13_PRIMITIVE_POLY;
232 table_size = PMECC_LOOKUP_TABLE_SIZE_512;
233 } else {
234 degree = PMECC_GF_DIMENSION_14;
235 poly = PMECC_GF_14_PRIMITIVE_POLY;
236 table_size = PMECC_LOOKUP_TABLE_SIZE_1024;
237 }
238
239 gf_tables = kzalloc(sizeof(*gf_tables) +
240 (2 * table_size * sizeof(u16)),
241 GFP_KERNEL);
242 if (!gf_tables)
243 return ERR_PTR(-ENOMEM);
244
245 gf_tables->alpha_to = (void *)(gf_tables + 1);
246 gf_tables->index_of = gf_tables->alpha_to + table_size;
247
248 ret = atmel_pmecc_build_gf_tables(degree, poly, gf_tables);
249 if (ret) {
250 kfree(gf_tables);
251 return ERR_PTR(ret);
252 }
253
254 return gf_tables;
255}
256
257static const struct atmel_pmecc_gf_tables *
258atmel_pmecc_get_gf_tables(const struct atmel_pmecc_user_req *req)
259{
260 const struct atmel_pmecc_gf_tables **gf_tables, *ret;
261
262 mutex_lock(&pmecc_gf_tables_lock);
263 if (req->ecc.sectorsize == 512)
264 gf_tables = &pmecc_gf_tables_512;
265 else
266 gf_tables = &pmecc_gf_tables_1024;
267
268 ret = *gf_tables;
269
270 if (!ret) {
271 ret = atmel_pmecc_create_gf_tables(req);
272 if (!IS_ERR(ret))
273 *gf_tables = ret;
274 }
275 mutex_unlock(&pmecc_gf_tables_lock);
276
277 return ret;
278}
279
280static int atmel_pmecc_prepare_user_req(struct atmel_pmecc *pmecc,
281 struct atmel_pmecc_user_req *req)
282{
283 int i, max_eccbytes, eccbytes = 0, eccstrength = 0;
284
285 if (req->pagesize <= 0 || req->oobsize <= 0 || req->ecc.bytes <= 0)
286 return -EINVAL;
287
288 if (req->ecc.ooboffset >= 0 &&
289 req->ecc.ooboffset + req->ecc.bytes > req->oobsize)
290 return -EINVAL;
291
292 if (req->ecc.sectorsize == ATMEL_PMECC_SECTOR_SIZE_AUTO) {
293 if (req->ecc.strength != ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH)
294 return -EINVAL;
295
296 if (req->pagesize > 512)
297 req->ecc.sectorsize = 1024;
298 else
299 req->ecc.sectorsize = 512;
300 }
301
302 if (req->ecc.sectorsize != 512 && req->ecc.sectorsize != 1024)
303 return -EINVAL;
304
305 if (req->pagesize % req->ecc.sectorsize)
306 return -EINVAL;
307
308 req->ecc.nsectors = req->pagesize / req->ecc.sectorsize;
309
310 max_eccbytes = req->ecc.bytes;
311
312 for (i = 0; i < pmecc->caps->nstrengths; i++) {
313 int nbytes, strength = pmecc->caps->strengths[i];
314
315 if (req->ecc.strength != ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH &&
316 strength < req->ecc.strength)
317 continue;
318
319 nbytes = DIV_ROUND_UP(strength * fls(8 * req->ecc.sectorsize),
320 8);
321 nbytes *= req->ecc.nsectors;
322
323 if (nbytes > max_eccbytes)
324 break;
325
326 eccstrength = strength;
327 eccbytes = nbytes;
328
329 if (req->ecc.strength != ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH)
330 break;
331 }
332
333 if (!eccstrength)
334 return -EINVAL;
335
336 req->ecc.bytes = eccbytes;
337 req->ecc.strength = eccstrength;
338
339 if (req->ecc.ooboffset < 0)
340 req->ecc.ooboffset = req->oobsize - eccbytes;
341
342 return 0;
343}
344
345struct atmel_pmecc_user *
346atmel_pmecc_create_user(struct atmel_pmecc *pmecc,
347 struct atmel_pmecc_user_req *req)
348{
349 struct atmel_pmecc_user *user;
350 const struct atmel_pmecc_gf_tables *gf_tables;
351 int strength, size, ret;
352
353 ret = atmel_pmecc_prepare_user_req(pmecc, req);
354 if (ret)
355 return ERR_PTR(ret);
356
357 size = sizeof(*user);
358 size = ALIGN(size, sizeof(u16));
359 /* Reserve space for partial_syn, si and smu */
360 size += ((2 * req->ecc.strength) + 1) * sizeof(u16) *
361 (2 + req->ecc.strength + 2);
362 /* Reserve space for lmu. */
363 size += (req->ecc.strength + 1) * sizeof(u16);
364 /* Reserve space for mu, dmu and delta. */
365 size = ALIGN(size, sizeof(s32));
366 size += (req->ecc.strength + 1) * sizeof(s32);
367
368 user = kzalloc(size, GFP_KERNEL);
369 if (!user)
370 return ERR_PTR(-ENOMEM);
371
372 user->pmecc = pmecc;
373
374 user->partial_syn = (s16 *)PTR_ALIGN(user + 1, sizeof(u16));
375 user->si = user->partial_syn + ((2 * req->ecc.strength) + 1);
376 user->lmu = user->si + ((2 * req->ecc.strength) + 1);
377 user->smu = user->lmu + (req->ecc.strength + 1);
378 user->mu = (s32 *)PTR_ALIGN(user->smu +
379 (((2 * req->ecc.strength) + 1) *
380 (req->ecc.strength + 2)),
381 sizeof(s32));
382 user->dmu = user->mu + req->ecc.strength + 1;
383 user->delta = user->dmu + req->ecc.strength + 1;
384
385 gf_tables = atmel_pmecc_get_gf_tables(req);
386 if (IS_ERR(gf_tables)) {
387 kfree(user);
388 return ERR_CAST(gf_tables);
389 }
390
391 user->gf_tables = gf_tables;
392
393 user->eccbytes = req->ecc.bytes / req->ecc.nsectors;
394
395 for (strength = 0; strength < pmecc->caps->nstrengths; strength++) {
396 if (pmecc->caps->strengths[strength] == req->ecc.strength)
397 break;
398 }
399
400 user->cache.cfg = PMECC_CFG_BCH_STRENGTH(strength) |
401 PMECC_CFG_NSECTORS(req->ecc.nsectors);
402
403 if (req->ecc.sectorsize == 1024)
404 user->cache.cfg |= PMECC_CFG_SECTOR1024;
405
406 user->cache.sarea = req->oobsize - 1;
407 user->cache.saddr = req->ecc.ooboffset;
408 user->cache.eaddr = req->ecc.ooboffset + req->ecc.bytes - 1;
409
410 return user;
411}
412EXPORT_SYMBOL_GPL(atmel_pmecc_create_user);
413
414void atmel_pmecc_destroy_user(struct atmel_pmecc_user *user)
415{
416 kfree(user);
417}
418EXPORT_SYMBOL_GPL(atmel_pmecc_destroy_user);
419
420static int get_strength(struct atmel_pmecc_user *user)
421{
422 const int *strengths = user->pmecc->caps->strengths;
423
424 return strengths[user->cache.cfg & PMECC_CFG_BCH_STRENGTH_MASK];
425}
426
427static int get_sectorsize(struct atmel_pmecc_user *user)
428{
429 return user->cache.cfg & PMECC_LOOKUP_TABLE_SIZE_1024 ? 1024 : 512;
430}
431
432static void atmel_pmecc_gen_syndrome(struct atmel_pmecc_user *user, int sector)
433{
434 int strength = get_strength(user);
435 u32 value;
436 int i;
437
438 /* Fill odd syndromes */
439 for (i = 0; i < strength; i++) {
440 value = readl_relaxed(user->pmecc->regs.base +
441 ATMEL_PMECC_REM(sector, i / 2));
442 if (i & 1)
443 value >>= 16;
444
445 user->partial_syn[(2 * i) + 1] = value;
446 }
447}
448
449static void atmel_pmecc_substitute(struct atmel_pmecc_user *user)
450{
451 int degree = get_sectorsize(user) == 512 ? 13 : 14;
452 int cw_len = BIT(degree) - 1;
453 int strength = get_strength(user);
454 s16 *alpha_to = user->gf_tables->alpha_to;
455 s16 *index_of = user->gf_tables->index_of;
456 s16 *partial_syn = user->partial_syn;
457 s16 *si;
458 int i, j;
459
460 /*
461 * si[] is a table that holds the current syndrome value,
462 * an element of that table belongs to the field
463 */
464 si = user->si;
465
466 memset(&si[1], 0, sizeof(s16) * ((2 * strength) - 1));
467
468 /* Computation 2t syndromes based on S(x) */
469 /* Odd syndromes */
470 for (i = 1; i < 2 * strength; i += 2) {
471 for (j = 0; j < degree; j++) {
472 if (partial_syn[i] & BIT(j))
473 si[i] = alpha_to[i * j] ^ si[i];
474 }
475 }
476 /* Even syndrome = (Odd syndrome) ** 2 */
477 for (i = 2, j = 1; j <= strength; i = ++j << 1) {
478 if (si[j] == 0) {
479 si[i] = 0;
480 } else {
481 s16 tmp;
482
483 tmp = index_of[si[j]];
484 tmp = (tmp * 2) % cw_len;
485 si[i] = alpha_to[tmp];
486 }
487 }
488}
489
490static void atmel_pmecc_get_sigma(struct atmel_pmecc_user *user)
491{
492 s16 *lmu = user->lmu;
493 s16 *si = user->si;
494 s32 *mu = user->mu;
495 s32 *dmu = user->dmu;
496 s32 *delta = user->delta;
497 int degree = get_sectorsize(user) == 512 ? 13 : 14;
498 int cw_len = BIT(degree) - 1;
499 int strength = get_strength(user);
500 int num = 2 * strength + 1;
501 s16 *index_of = user->gf_tables->index_of;
502 s16 *alpha_to = user->gf_tables->alpha_to;
503 int i, j, k;
504 u32 dmu_0_count, tmp;
505 s16 *smu = user->smu;
506
507 /* index of largest delta */
508 int ro;
509 int largest;
510 int diff;
511
512 dmu_0_count = 0;
513
514 /* First Row */
515
516 /* Mu */
517 mu[0] = -1;
518
519 memset(smu, 0, sizeof(s16) * num);
520 smu[0] = 1;
521
522 /* discrepancy set to 1 */
523 dmu[0] = 1;
524 /* polynom order set to 0 */
525 lmu[0] = 0;
526 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
527
528 /* Second Row */
529
530 /* Mu */
531 mu[1] = 0;
532 /* Sigma(x) set to 1 */
533 memset(&smu[num], 0, sizeof(s16) * num);
534 smu[num] = 1;
535
536 /* discrepancy set to S1 */
537 dmu[1] = si[1];
538
539 /* polynom order set to 0 */
540 lmu[1] = 0;
541
542 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
543
544 /* Init the Sigma(x) last row */
545 memset(&smu[(strength + 1) * num], 0, sizeof(s16) * num);
546
547 for (i = 1; i <= strength; i++) {
548 mu[i + 1] = i << 1;
549 /* Begin Computing Sigma (Mu+1) and L(mu) */
550 /* check if discrepancy is set to 0 */
551 if (dmu[i] == 0) {
552 dmu_0_count++;
553
554 tmp = ((strength - (lmu[i] >> 1) - 1) / 2);
555 if ((strength - (lmu[i] >> 1) - 1) & 0x1)
556 tmp += 2;
557 else
558 tmp += 1;
559
560 if (dmu_0_count == tmp) {
561 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
562 smu[(strength + 1) * num + j] =
563 smu[i * num + j];
564
565 lmu[strength + 1] = lmu[i];
566 return;
567 }
568
569 /* copy polynom */
570 for (j = 0; j <= lmu[i] >> 1; j++)
571 smu[(i + 1) * num + j] = smu[i * num + j];
572
573 /* copy previous polynom order to the next */
574 lmu[i + 1] = lmu[i];
575 } else {
576 ro = 0;
577 largest = -1;
578 /* find largest delta with dmu != 0 */
579 for (j = 0; j < i; j++) {
580 if ((dmu[j]) && (delta[j] > largest)) {
581 largest = delta[j];
582 ro = j;
583 }
584 }
585
586 /* compute difference */
587 diff = (mu[i] - mu[ro]);
588
589 /* Compute degree of the new smu polynomial */
590 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
591 lmu[i + 1] = lmu[i];
592 else
593 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
594
595 /* Init smu[i+1] with 0 */
596 for (k = 0; k < num; k++)
597 smu[(i + 1) * num + k] = 0;
598
599 /* Compute smu[i+1] */
600 for (k = 0; k <= lmu[ro] >> 1; k++) {
601 s16 a, b, c;
602
603 if (!(smu[ro * num + k] && dmu[i]))
604 continue;
605
606 a = index_of[dmu[i]];
607 b = index_of[dmu[ro]];
608 c = index_of[smu[ro * num + k]];
609 tmp = a + (cw_len - b) + c;
610 a = alpha_to[tmp % cw_len];
611 smu[(i + 1) * num + (k + diff)] = a;
612 }
613
614 for (k = 0; k <= lmu[i] >> 1; k++)
615 smu[(i + 1) * num + k] ^= smu[i * num + k];
616 }
617
618 /* End Computing Sigma (Mu+1) and L(mu) */
619 /* In either case compute delta */
620 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
621
622 /* Do not compute discrepancy for the last iteration */
623 if (i >= strength)
624 continue;
625
626 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
627 tmp = 2 * (i - 1);
628 if (k == 0) {
629 dmu[i + 1] = si[tmp + 3];
630 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
631 s16 a, b, c;
632
633 a = index_of[smu[(i + 1) * num + k]];
634 b = si[2 * (i - 1) + 3 - k];
635 c = index_of[b];
636 tmp = a + c;
637 tmp %= cw_len;
638 dmu[i + 1] = alpha_to[tmp] ^ dmu[i + 1];
639 }
640 }
641 }
642}
643
644static int atmel_pmecc_err_location(struct atmel_pmecc_user *user)
645{
646 int sector_size = get_sectorsize(user);
647 int degree = sector_size == 512 ? 13 : 14;
648 struct atmel_pmecc *pmecc = user->pmecc;
649 int strength = get_strength(user);
650 int ret, roots_nbr, i, err_nbr = 0;
651 int num = (2 * strength) + 1;
652 s16 *smu = user->smu;
653 u32 val;
654
655 writel(PMERRLOC_DISABLE, pmecc->regs.errloc + ATMEL_PMERRLOC_ELDIS);
656
657 for (i = 0; i <= user->lmu[strength + 1] >> 1; i++) {
658 writel_relaxed(smu[(strength + 1) * num + i],
659 pmecc->regs.errloc + ATMEL_PMERRLOC_SIGMA(i));
660 err_nbr++;
661 }
662
663 val = (err_nbr - 1) << 16;
664 if (sector_size == 1024)
665 val |= 1;
666
667 writel(val, pmecc->regs.errloc + ATMEL_PMERRLOC_ELCFG);
668 writel((sector_size * 8) + (degree * strength),
669 pmecc->regs.errloc + ATMEL_PMERRLOC_ELEN);
670
671 ret = readl_relaxed_poll_timeout(pmecc->regs.errloc +
672 ATMEL_PMERRLOC_ELISR,
673 val, val & PMERRLOC_CALC_DONE, 0,
674 PMECC_MAX_TIMEOUT_MS * 1000);
675 if (ret) {
676 dev_err(pmecc->dev,
677 "PMECC: Timeout to calculate error location.\n");
678 return ret;
679 }
680
681 roots_nbr = (val & PMERRLOC_ERR_NUM_MASK) >> 8;
682 /* Number of roots == degree of smu hence <= cap */
683 if (roots_nbr == user->lmu[strength + 1] >> 1)
684 return err_nbr - 1;
685
686 /*
687 * Number of roots does not match the degree of smu
688 * unable to correct error.
689 */
690 return -EBADMSG;
691}
692
693int atmel_pmecc_correct_sector(struct atmel_pmecc_user *user, int sector,
694 void *data, void *ecc)
695{
696 struct atmel_pmecc *pmecc = user->pmecc;
697 int sectorsize = get_sectorsize(user);
698 int eccbytes = user->eccbytes;
699 int i, nerrors;
700
701 if (!(user->isr & BIT(sector)))
702 return 0;
703
704 atmel_pmecc_gen_syndrome(user, sector);
705 atmel_pmecc_substitute(user);
706 atmel_pmecc_get_sigma(user);
707
708 nerrors = atmel_pmecc_err_location(user);
709 if (nerrors < 0)
710 return nerrors;
711
712 for (i = 0; i < nerrors; i++) {
713 const char *area;
714 int byte, bit;
715 u32 errpos;
716 u8 *ptr;
717
718 errpos = readl_relaxed(pmecc->regs.errloc +
719 ATMEL_PMERRLOC_EL(pmecc->caps->el_offset, i));
720 errpos--;
721
722 byte = errpos / 8;
723 bit = errpos % 8;
724
725 if (byte < sectorsize) {
726 ptr = data + byte;
727 area = "data";
728 } else if (byte < sectorsize + eccbytes) {
729 ptr = ecc + byte - sectorsize;
730 area = "ECC";
731 } else {
732 dev_dbg(pmecc->dev,
733 "Invalid errpos value (%d, max is %d)\n",
734 errpos, (sectorsize + eccbytes) * 8);
735 return -EINVAL;
736 }
737
738 dev_dbg(pmecc->dev,
739 "Bit flip in %s area, byte %d: 0x%02x -> 0x%02x\n",
740 area, byte, *ptr, (unsigned int)(*ptr ^ BIT(bit)));
741
742 *ptr ^= BIT(bit);
743 }
744
745 return nerrors;
746}
747EXPORT_SYMBOL_GPL(atmel_pmecc_correct_sector);
748
749bool atmel_pmecc_correct_erased_chunks(struct atmel_pmecc_user *user)
750{
751 return user->pmecc->caps->correct_erased_chunks;
752}
753EXPORT_SYMBOL_GPL(atmel_pmecc_correct_erased_chunks);
754
755void atmel_pmecc_get_generated_eccbytes(struct atmel_pmecc_user *user,
756 int sector, void *ecc)
757{
758 struct atmel_pmecc *pmecc = user->pmecc;
759 u8 *ptr = ecc;
760 int i;
761
762 for (i = 0; i < user->eccbytes; i++)
763 ptr[i] = readb_relaxed(pmecc->regs.base +
764 ATMEL_PMECC_ECC(sector, i));
765}
766EXPORT_SYMBOL_GPL(atmel_pmecc_get_generated_eccbytes);
767
768int atmel_pmecc_enable(struct atmel_pmecc_user *user, int op)
769{
770 struct atmel_pmecc *pmecc = user->pmecc;
771 u32 cfg;
772
773 if (op != NAND_ECC_READ && op != NAND_ECC_WRITE) {
774 dev_err(pmecc->dev, "Bad ECC operation!");
775 return -EINVAL;
776 }
777
778 mutex_lock(&user->pmecc->lock);
779
780 cfg = user->cache.cfg;
781 if (op == NAND_ECC_WRITE)
782 cfg |= PMECC_CFG_WRITE_OP;
783 else
784 cfg |= PMECC_CFG_AUTO_ENABLE;
785
786 writel(cfg, pmecc->regs.base + ATMEL_PMECC_CFG);
787 writel(user->cache.sarea, pmecc->regs.base + ATMEL_PMECC_SAREA);
788 writel(user->cache.saddr, pmecc->regs.base + ATMEL_PMECC_SADDR);
789 writel(user->cache.eaddr, pmecc->regs.base + ATMEL_PMECC_EADDR);
790
791 writel(PMECC_CTRL_ENABLE, pmecc->regs.base + ATMEL_PMECC_CTRL);
792 writel(PMECC_CTRL_DATA, pmecc->regs.base + ATMEL_PMECC_CTRL);
793
794 return 0;
795}
796EXPORT_SYMBOL_GPL(atmel_pmecc_enable);
797
798void atmel_pmecc_disable(struct atmel_pmecc_user *user)
799{
800 struct atmel_pmecc *pmecc = user->pmecc;
801
802 writel(PMECC_CTRL_RST, pmecc->regs.base + ATMEL_PMECC_CTRL);
803 writel(PMECC_CTRL_DISABLE, pmecc->regs.base + ATMEL_PMECC_CTRL);
804 mutex_unlock(&user->pmecc->lock);
805}
806EXPORT_SYMBOL_GPL(atmel_pmecc_disable);
807
808int atmel_pmecc_wait_rdy(struct atmel_pmecc_user *user)
809{
810 struct atmel_pmecc *pmecc = user->pmecc;
811 u32 status;
812 int ret;
813
814 ret = readl_relaxed_poll_timeout(pmecc->regs.base +
815 ATMEL_PMECC_SR,
816 status, !(status & PMECC_SR_BUSY), 0,
817 PMECC_MAX_TIMEOUT_MS * 1000);
818 if (ret) {
819 dev_err(pmecc->dev,
820 "Timeout while waiting for PMECC ready.\n");
821 return ret;
822 }
823
824 user->isr = readl_relaxed(pmecc->regs.base + ATMEL_PMECC_ISR);
825
826 return 0;
827}
828EXPORT_SYMBOL_GPL(atmel_pmecc_wait_rdy);
829
830static struct atmel_pmecc *atmel_pmecc_create(struct platform_device *pdev,
831 const struct atmel_pmecc_caps *caps,
832 int pmecc_res_idx, int errloc_res_idx)
833{
834 struct device *dev = &pdev->dev;
835 struct atmel_pmecc *pmecc;
836 struct resource *res;
837
838 pmecc = devm_kzalloc(dev, sizeof(*pmecc), GFP_KERNEL);
839 if (!pmecc)
840 return ERR_PTR(-ENOMEM);
841
842 pmecc->caps = caps;
843 pmecc->dev = dev;
844 mutex_init(&pmecc->lock);
845
846 res = platform_get_resource(pdev, IORESOURCE_MEM, pmecc_res_idx);
847 pmecc->regs.base = devm_ioremap_resource(dev, res);
848 if (IS_ERR(pmecc->regs.base))
849 return ERR_CAST(pmecc->regs.base);
850
851 res = platform_get_resource(pdev, IORESOURCE_MEM, errloc_res_idx);
852 pmecc->regs.errloc = devm_ioremap_resource(dev, res);
853 if (IS_ERR(pmecc->regs.errloc))
854 return ERR_CAST(pmecc->regs.errloc);
855
856 /* Disable all interrupts before registering the PMECC handler. */
857 writel(0xffffffff, pmecc->regs.base + ATMEL_PMECC_IDR);
858
859 /* Reset the ECC engine */
860 writel(PMECC_CTRL_RST, pmecc->regs.base + ATMEL_PMECC_CTRL);
861 writel(PMECC_CTRL_DISABLE, pmecc->regs.base + ATMEL_PMECC_CTRL);
862
863 return pmecc;
864}
865
866static void devm_atmel_pmecc_put(struct device *dev, void *res)
867{
868 struct atmel_pmecc **pmecc = res;
869
870 put_device((*pmecc)->dev);
871}
872
873static struct atmel_pmecc *atmel_pmecc_get_by_node(struct device *userdev,
874 struct device_node *np)
875{
876 struct platform_device *pdev;
877 struct atmel_pmecc *pmecc, **ptr;
878
879 pdev = of_find_device_by_node(np);
880 if (!pdev || !platform_get_drvdata(pdev))
881 return ERR_PTR(-EPROBE_DEFER);
882
883 ptr = devres_alloc(devm_atmel_pmecc_put, sizeof(*ptr), GFP_KERNEL);
884 if (!ptr)
885 return ERR_PTR(-ENOMEM);
886
887 get_device(&pdev->dev);
888 pmecc = platform_get_drvdata(pdev);
889
890 *ptr = pmecc;
891
892 devres_add(userdev, ptr);
893
894 return pmecc;
895}
896
897static const int atmel_pmecc_strengths[] = { 2, 4, 8, 12, 24, 32 };
898
899static struct atmel_pmecc_caps at91sam9g45_caps = {
900 .strengths = atmel_pmecc_strengths,
901 .nstrengths = 5,
902 .el_offset = 0x8c,
903};
904
905static struct atmel_pmecc_caps sama5d4_caps = {
906 .strengths = atmel_pmecc_strengths,
907 .nstrengths = 5,
908 .el_offset = 0x8c,
909 .correct_erased_chunks = true,
910};
911
912static struct atmel_pmecc_caps sama5d2_caps = {
913 .strengths = atmel_pmecc_strengths,
914 .nstrengths = 6,
915 .el_offset = 0xac,
916 .correct_erased_chunks = true,
917};
918
919static const struct of_device_id atmel_pmecc_legacy_match[] = {
920 { .compatible = "atmel,sama5d4-nand", &sama5d4_caps },
921 { .compatible = "atmel,sama5d2-nand", &sama5d2_caps },
922 { /* sentinel */ }
923};
924
925struct atmel_pmecc *devm_atmel_pmecc_get(struct device *userdev)
926{
927 struct atmel_pmecc *pmecc;
928 struct device_node *np;
929
930 if (!userdev)
931 return ERR_PTR(-EINVAL);
932
933 if (!userdev->of_node)
934 return NULL;
935
936 np = of_parse_phandle(userdev->of_node, "ecc-engine", 0);
937 if (np) {
938 pmecc = atmel_pmecc_get_by_node(userdev, np);
939 of_node_put(np);
940 } else {
941 /*
942 * Support old DT bindings: in this case the PMECC iomem
943 * resources are directly defined in the user pdev at position
944 * 1 and 2. Extract all relevant information from there.
945 */
946 struct platform_device *pdev = to_platform_device(userdev);
947 const struct atmel_pmecc_caps *caps;
948
949 /* No PMECC engine available. */
950 if (!of_property_read_bool(userdev->of_node,
951 "atmel,has-pmecc"))
952 return NULL;
953
954 caps = &at91sam9g45_caps;
955
956 /*
957 * Try to find the NFC subnode and extract the associated caps
958 * from there.
959 */
960 np = of_find_compatible_node(userdev->of_node, NULL,
961 "atmel,sama5d3-nfc");
962 if (np) {
963 const struct of_device_id *match;
964
965 match = of_match_node(atmel_pmecc_legacy_match, np);
966 if (match && match->data)
967 caps = match->data;
968
969 of_node_put(np);
970 }
971
972 pmecc = atmel_pmecc_create(pdev, caps, 1, 2);
973 }
974
975 return pmecc;
976}
977EXPORT_SYMBOL(devm_atmel_pmecc_get);
978
979static const struct of_device_id atmel_pmecc_match[] = {
980 { .compatible = "atmel,at91sam9g45-pmecc", &at91sam9g45_caps },
981 { .compatible = "atmel,sama5d4-pmecc", &sama5d4_caps },
982 { .compatible = "atmel,sama5d2-pmecc", &sama5d2_caps },
983 { /* sentinel */ }
984};
985MODULE_DEVICE_TABLE(of, atmel_pmecc_match);
986
987static int atmel_pmecc_probe(struct platform_device *pdev)
988{
989 struct device *dev = &pdev->dev;
990 const struct atmel_pmecc_caps *caps;
991 struct atmel_pmecc *pmecc;
992
993 caps = of_device_get_match_data(&pdev->dev);
994 if (!caps) {
995 dev_err(dev, "Invalid caps\n");
996 return -EINVAL;
997 }
998
999 pmecc = atmel_pmecc_create(pdev, caps, 0, 1);
1000 if (IS_ERR(pmecc))
1001 return PTR_ERR(pmecc);
1002
1003 platform_set_drvdata(pdev, pmecc);
1004
1005 return 0;
1006}
1007
1008static struct platform_driver atmel_pmecc_driver = {
1009 .driver = {
1010 .name = "atmel-pmecc",
1011 .of_match_table = of_match_ptr(atmel_pmecc_match),
1012 },
1013 .probe = atmel_pmecc_probe,
1014};
1015module_platform_driver(atmel_pmecc_driver);
1016
1017MODULE_LICENSE("GPL");
1018MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
1019MODULE_DESCRIPTION("PMECC engine driver");
1020MODULE_ALIAS("platform:atmel_pmecc");
diff --git a/drivers/mtd/nand/atmel/pmecc.h b/drivers/mtd/nand/atmel/pmecc.h
new file mode 100644
index 000000000000..a8ddbfca2ea5
--- /dev/null
+++ b/drivers/mtd/nand/atmel/pmecc.h
@@ -0,0 +1,73 @@
1/*
2 * © Copyright 2016 ATMEL
3 * © Copyright 2016 Free Electrons
4 *
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
6 *
7 * Derived from the atmel_nand.c driver which contained the following
8 * copyrights:
9 *
10 * Copyright © 2003 Rick Bronson
11 *
12 * Derived from drivers/mtd/nand/autcpu12.c
13 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
14 *
15 * Derived from drivers/mtd/spia.c
16 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
17 *
18 *
19 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
20 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
21 *
22 * Derived from Das U-Boot source code
23 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
24 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
25 *
26 * Add Programmable Multibit ECC support for various AT91 SoC
27 * © Copyright 2012 ATMEL, Hong Xu
28 *
29 * Add Nand Flash Controller support for SAMA5 SoC
30 * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
31 *
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License version 2 as
34 * published by the Free Software Foundation.
35 *
36 */
37
38#ifndef ATMEL_PMECC_H
39#define ATMEL_PMECC_H
40
41#define ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH 0
42#define ATMEL_PMECC_SECTOR_SIZE_AUTO 0
43#define ATMEL_PMECC_OOBOFFSET_AUTO -1
44
45struct atmel_pmecc_user_req {
46 int pagesize;
47 int oobsize;
48 struct {
49 int strength;
50 int bytes;
51 int sectorsize;
52 int nsectors;
53 int ooboffset;
54 } ecc;
55};
56
57struct atmel_pmecc *devm_atmel_pmecc_get(struct device *dev);
58
59struct atmel_pmecc_user *
60atmel_pmecc_create_user(struct atmel_pmecc *pmecc,
61 struct atmel_pmecc_user_req *req);
62void atmel_pmecc_destroy_user(struct atmel_pmecc_user *user);
63
64int atmel_pmecc_enable(struct atmel_pmecc_user *user, int op);
65void atmel_pmecc_disable(struct atmel_pmecc_user *user);
66int atmel_pmecc_wait_rdy(struct atmel_pmecc_user *user);
67int atmel_pmecc_correct_sector(struct atmel_pmecc_user *user, int sector,
68 void *data, void *ecc);
69bool atmel_pmecc_correct_erased_chunks(struct atmel_pmecc_user *user);
70void atmel_pmecc_get_generated_eccbytes(struct atmel_pmecc_user *user,
71 int sector, void *ecc);
72
73#endif /* ATMEL_PMECC_H */
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
deleted file mode 100644
index 9ebd5ecefea6..000000000000
--- a/drivers/mtd/nand/atmel_nand.c
+++ /dev/null
@@ -1,2479 +0,0 @@
1/*
2 * Copyright © 2003 Rick Bronson
3 *
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
6 *
7 * Derived from drivers/mtd/spia.c
8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
9 *
10 *
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
13 *
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
17 *
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
20 *
21 * Add Nand Flash Controller support for SAMA5 SoC
22 * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
30#include <linux/clk.h>
31#include <linux/dma-mapping.h>
32#include <linux/slab.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/platform_device.h>
36#include <linux/of.h>
37#include <linux/of_device.h>
38#include <linux/of_gpio.h>
39#include <linux/mtd/mtd.h>
40#include <linux/mtd/nand.h>
41#include <linux/mtd/partitions.h>
42
43#include <linux/delay.h>
44#include <linux/dmaengine.h>
45#include <linux/gpio.h>
46#include <linux/interrupt.h>
47#include <linux/io.h>
48#include <linux/platform_data/atmel.h>
49
50static int use_dma = 1;
51module_param(use_dma, int, 0);
52
53static int on_flash_bbt = 0;
54module_param(on_flash_bbt, int, 0);
55
56/* Register access macros */
57#define ecc_readl(add, reg) \
58 __raw_readl(add + ATMEL_ECC_##reg)
59#define ecc_writel(add, reg, value) \
60 __raw_writel((value), add + ATMEL_ECC_##reg)
61
62#include "atmel_nand_ecc.h" /* Hardware ECC registers */
63#include "atmel_nand_nfc.h" /* Nand Flash Controller definition */
64
65struct atmel_nand_caps {
66 bool pmecc_correct_erase_page;
67 uint8_t pmecc_max_correction;
68};
69
70/*
71 * oob layout for large page size
72 * bad block info is on bytes 0 and 1
73 * the bytes have to be consecutives to avoid
74 * several NAND_CMD_RNDOUT during read
75 *
76 * oob layout for small page size
77 * bad block info is on bytes 4 and 5
78 * the bytes have to be consecutives to avoid
79 * several NAND_CMD_RNDOUT during read
80 */
81static int atmel_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
82 struct mtd_oob_region *oobregion)
83{
84 if (section)
85 return -ERANGE;
86
87 oobregion->length = 4;
88 oobregion->offset = 0;
89
90 return 0;
91}
92
93static int atmel_ooblayout_free_sp(struct mtd_info *mtd, int section,
94 struct mtd_oob_region *oobregion)
95{
96 if (section)
97 return -ERANGE;
98
99 oobregion->offset = 6;
100 oobregion->length = mtd->oobsize - oobregion->offset;
101
102 return 0;
103}
104
105static const struct mtd_ooblayout_ops atmel_ooblayout_sp_ops = {
106 .ecc = atmel_ooblayout_ecc_sp,
107 .free = atmel_ooblayout_free_sp,
108};
109
110struct atmel_nfc {
111 void __iomem *base_cmd_regs;
112 void __iomem *hsmc_regs;
113 void *sram_bank0;
114 dma_addr_t sram_bank0_phys;
115 bool use_nfc_sram;
116 bool write_by_sram;
117
118 struct clk *clk;
119
120 bool is_initialized;
121 struct completion comp_ready;
122 struct completion comp_cmd_done;
123 struct completion comp_xfer_done;
124
125 /* Point to the sram bank which include readed data via NFC */
126 void *data_in_sram;
127 bool will_write_sram;
128};
129static struct atmel_nfc nand_nfc;
130
131struct atmel_nand_host {
132 struct nand_chip nand_chip;
133 void __iomem *io_base;
134 dma_addr_t io_phys;
135 struct atmel_nand_data board;
136 struct device *dev;
137 void __iomem *ecc;
138
139 struct completion comp;
140 struct dma_chan *dma_chan;
141
142 struct atmel_nfc *nfc;
143
144 const struct atmel_nand_caps *caps;
145 bool has_pmecc;
146 u8 pmecc_corr_cap;
147 u16 pmecc_sector_size;
148 bool has_no_lookup_table;
149 u32 pmecc_lookup_table_offset;
150 u32 pmecc_lookup_table_offset_512;
151 u32 pmecc_lookup_table_offset_1024;
152
153 int pmecc_degree; /* Degree of remainders */
154 int pmecc_cw_len; /* Length of codeword */
155
156 void __iomem *pmerrloc_base;
157 void __iomem *pmerrloc_el_base;
158 void __iomem *pmecc_rom_base;
159
160 /* lookup table for alpha_to and index_of */
161 void __iomem *pmecc_alpha_to;
162 void __iomem *pmecc_index_of;
163
164 /* data for pmecc computation */
165 int16_t *pmecc_partial_syn;
166 int16_t *pmecc_si;
167 int16_t *pmecc_smu; /* Sigma table */
168 int16_t *pmecc_lmu; /* polynomal order */
169 int *pmecc_mu;
170 int *pmecc_dmu;
171 int *pmecc_delta;
172};
173
174/*
175 * Enable NAND.
176 */
177static void atmel_nand_enable(struct atmel_nand_host *host)
178{
179 if (gpio_is_valid(host->board.enable_pin))
180 gpio_set_value(host->board.enable_pin, 0);
181}
182
183/*
184 * Disable NAND.
185 */
186static void atmel_nand_disable(struct atmel_nand_host *host)
187{
188 if (gpio_is_valid(host->board.enable_pin))
189 gpio_set_value(host->board.enable_pin, 1);
190}
191
192/*
193 * Hardware specific access to control-lines
194 */
195static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
196{
197 struct nand_chip *nand_chip = mtd_to_nand(mtd);
198 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
199
200 if (ctrl & NAND_CTRL_CHANGE) {
201 if (ctrl & NAND_NCE)
202 atmel_nand_enable(host);
203 else
204 atmel_nand_disable(host);
205 }
206 if (cmd == NAND_CMD_NONE)
207 return;
208
209 if (ctrl & NAND_CLE)
210 writeb(cmd, host->io_base + (1 << host->board.cle));
211 else
212 writeb(cmd, host->io_base + (1 << host->board.ale));
213}
214
215/*
216 * Read the Device Ready pin.
217 */
218static int atmel_nand_device_ready(struct mtd_info *mtd)
219{
220 struct nand_chip *nand_chip = mtd_to_nand(mtd);
221 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
222
223 return gpio_get_value(host->board.rdy_pin) ^
224 !!host->board.rdy_pin_active_low;
225}
226
227/* Set up for hardware ready pin and enable pin. */
228static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
229{
230 struct nand_chip *chip = mtd_to_nand(mtd);
231 struct atmel_nand_host *host = nand_get_controller_data(chip);
232 int res = 0;
233
234 if (gpio_is_valid(host->board.rdy_pin)) {
235 res = devm_gpio_request(host->dev,
236 host->board.rdy_pin, "nand_rdy");
237 if (res < 0) {
238 dev_err(host->dev,
239 "can't request rdy gpio %d\n",
240 host->board.rdy_pin);
241 return res;
242 }
243
244 res = gpio_direction_input(host->board.rdy_pin);
245 if (res < 0) {
246 dev_err(host->dev,
247 "can't request input direction rdy gpio %d\n",
248 host->board.rdy_pin);
249 return res;
250 }
251
252 chip->dev_ready = atmel_nand_device_ready;
253 }
254
255 if (gpio_is_valid(host->board.enable_pin)) {
256 res = devm_gpio_request(host->dev,
257 host->board.enable_pin, "nand_enable");
258 if (res < 0) {
259 dev_err(host->dev,
260 "can't request enable gpio %d\n",
261 host->board.enable_pin);
262 return res;
263 }
264
265 res = gpio_direction_output(host->board.enable_pin, 1);
266 if (res < 0) {
267 dev_err(host->dev,
268 "can't request output direction enable gpio %d\n",
269 host->board.enable_pin);
270 return res;
271 }
272 }
273
274 return res;
275}
276
277/*
278 * Minimal-overhead PIO for data access.
279 */
280static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
281{
282 struct nand_chip *nand_chip = mtd_to_nand(mtd);
283 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
284
285 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
286 memcpy(buf, host->nfc->data_in_sram, len);
287 host->nfc->data_in_sram += len;
288 } else {
289 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
290 }
291}
292
293static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
294{
295 struct nand_chip *nand_chip = mtd_to_nand(mtd);
296 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
297
298 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
299 memcpy(buf, host->nfc->data_in_sram, len);
300 host->nfc->data_in_sram += len;
301 } else {
302 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
303 }
304}
305
306static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
307{
308 struct nand_chip *nand_chip = mtd_to_nand(mtd);
309
310 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
311}
312
313static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
314{
315 struct nand_chip *nand_chip = mtd_to_nand(mtd);
316
317 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
318}
319
320static void dma_complete_func(void *completion)
321{
322 complete(completion);
323}
324
325static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
326{
327 /* NFC only has two banks. Must be 0 or 1 */
328 if (bank > 1)
329 return -EINVAL;
330
331 if (bank) {
332 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
333
334 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
335 if (mtd->writesize > 2048)
336 return -EINVAL;
337 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
338 } else {
339 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
340 }
341
342 return 0;
343}
344
345static uint nfc_get_sram_off(struct atmel_nand_host *host)
346{
347 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
348 return NFC_SRAM_BANK1_OFFSET;
349 else
350 return 0;
351}
352
353static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
354{
355 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
356 return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
357 else
358 return host->nfc->sram_bank0_phys;
359}
360
361static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
362 int is_read)
363{
364 struct dma_device *dma_dev;
365 enum dma_ctrl_flags flags;
366 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
367 struct dma_async_tx_descriptor *tx = NULL;
368 dma_cookie_t cookie;
369 struct nand_chip *chip = mtd_to_nand(mtd);
370 struct atmel_nand_host *host = nand_get_controller_data(chip);
371 void *p = buf;
372 int err = -EIO;
373 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
374 struct atmel_nfc *nfc = host->nfc;
375
376 if (buf >= high_memory)
377 goto err_buf;
378
379 dma_dev = host->dma_chan->device;
380
381 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
382
383 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
384 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
385 dev_err(host->dev, "Failed to dma_map_single\n");
386 goto err_buf;
387 }
388
389 if (is_read) {
390 if (nfc && nfc->data_in_sram)
391 dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
392 - (nfc->sram_bank0 + nfc_get_sram_off(host)));
393 else
394 dma_src_addr = host->io_phys;
395
396 dma_dst_addr = phys_addr;
397 } else {
398 dma_src_addr = phys_addr;
399
400 if (nfc && nfc->write_by_sram)
401 dma_dst_addr = nfc_sram_phys(host);
402 else
403 dma_dst_addr = host->io_phys;
404 }
405
406 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
407 dma_src_addr, len, flags);
408 if (!tx) {
409 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
410 goto err_dma;
411 }
412
413 init_completion(&host->comp);
414 tx->callback = dma_complete_func;
415 tx->callback_param = &host->comp;
416
417 cookie = tx->tx_submit(tx);
418 if (dma_submit_error(cookie)) {
419 dev_err(host->dev, "Failed to do DMA tx_submit\n");
420 goto err_dma;
421 }
422
423 dma_async_issue_pending(host->dma_chan);
424 wait_for_completion(&host->comp);
425
426 if (is_read && nfc && nfc->data_in_sram)
427 /* After read data from SRAM, need to increase the position */
428 nfc->data_in_sram += len;
429
430 err = 0;
431
432err_dma:
433 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
434err_buf:
435 if (err != 0)
436 dev_dbg(host->dev, "Fall back to CPU I/O\n");
437 return err;
438}
439
440static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
441{
442 struct nand_chip *chip = mtd_to_nand(mtd);
443
444 if (use_dma && len > mtd->oobsize)
445 /* only use DMA for bigger than oob size: better performances */
446 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
447 return;
448
449 if (chip->options & NAND_BUSWIDTH_16)
450 atmel_read_buf16(mtd, buf, len);
451 else
452 atmel_read_buf8(mtd, buf, len);
453}
454
455static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
456{
457 struct nand_chip *chip = mtd_to_nand(mtd);
458
459 if (use_dma && len > mtd->oobsize)
460 /* only use DMA for bigger than oob size: better performances */
461 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
462 return;
463
464 if (chip->options & NAND_BUSWIDTH_16)
465 atmel_write_buf16(mtd, buf, len);
466 else
467 atmel_write_buf8(mtd, buf, len);
468}
469
470/*
471 * Return number of ecc bytes per sector according to sector size and
472 * correction capability
473 *
474 * Following table shows what at91 PMECC supported:
475 * Correction Capability Sector_512_bytes Sector_1024_bytes
476 * ===================== ================ =================
477 * 2-bits 4-bytes 4-bytes
478 * 4-bits 7-bytes 7-bytes
479 * 8-bits 13-bytes 14-bytes
480 * 12-bits 20-bytes 21-bytes
481 * 24-bits 39-bytes 42-bytes
482 * 32-bits 52-bytes 56-bytes
483 */
484static int pmecc_get_ecc_bytes(int cap, int sector_size)
485{
486 int m = 12 + sector_size / 512;
487 return (m * cap + 7) / 8;
488}
489
490static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
491{
492 int table_size;
493
494 table_size = host->pmecc_sector_size == 512 ?
495 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
496
497 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
498 table_size * sizeof(int16_t);
499}
500
501static int pmecc_data_alloc(struct atmel_nand_host *host)
502{
503 const int cap = host->pmecc_corr_cap;
504 int size;
505
506 size = (2 * cap + 1) * sizeof(int16_t);
507 host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
508 host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
509 host->pmecc_lmu = devm_kzalloc(host->dev,
510 (cap + 1) * sizeof(int16_t), GFP_KERNEL);
511 host->pmecc_smu = devm_kzalloc(host->dev,
512 (cap + 2) * size, GFP_KERNEL);
513
514 size = (cap + 1) * sizeof(int);
515 host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
516 host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
517 host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);
518
519 if (!host->pmecc_partial_syn ||
520 !host->pmecc_si ||
521 !host->pmecc_lmu ||
522 !host->pmecc_smu ||
523 !host->pmecc_mu ||
524 !host->pmecc_dmu ||
525 !host->pmecc_delta)
526 return -ENOMEM;
527
528 return 0;
529}
530
531static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
532{
533 struct nand_chip *nand_chip = mtd_to_nand(mtd);
534 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
535 int i;
536 uint32_t value;
537
538 /* Fill odd syndromes */
539 for (i = 0; i < host->pmecc_corr_cap; i++) {
540 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
541 if (i & 1)
542 value >>= 16;
543 value &= 0xffff;
544 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
545 }
546}
547
548static void pmecc_substitute(struct mtd_info *mtd)
549{
550 struct nand_chip *nand_chip = mtd_to_nand(mtd);
551 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
552 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
553 int16_t __iomem *index_of = host->pmecc_index_of;
554 int16_t *partial_syn = host->pmecc_partial_syn;
555 const int cap = host->pmecc_corr_cap;
556 int16_t *si;
557 int i, j;
558
559 /* si[] is a table that holds the current syndrome value,
560 * an element of that table belongs to the field
561 */
562 si = host->pmecc_si;
563
564 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
565
566 /* Computation 2t syndromes based on S(x) */
567 /* Odd syndromes */
568 for (i = 1; i < 2 * cap; i += 2) {
569 for (j = 0; j < host->pmecc_degree; j++) {
570 if (partial_syn[i] & ((unsigned short)0x1 << j))
571 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
572 }
573 }
574 /* Even syndrome = (Odd syndrome) ** 2 */
575 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
576 if (si[j] == 0) {
577 si[i] = 0;
578 } else {
579 int16_t tmp;
580
581 tmp = readw_relaxed(index_of + si[j]);
582 tmp = (tmp * 2) % host->pmecc_cw_len;
583 si[i] = readw_relaxed(alpha_to + tmp);
584 }
585 }
586
587 return;
588}
589
590static void pmecc_get_sigma(struct mtd_info *mtd)
591{
592 struct nand_chip *nand_chip = mtd_to_nand(mtd);
593 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
594
595 int16_t *lmu = host->pmecc_lmu;
596 int16_t *si = host->pmecc_si;
597 int *mu = host->pmecc_mu;
598 int *dmu = host->pmecc_dmu; /* Discrepancy */
599 int *delta = host->pmecc_delta; /* Delta order */
600 int cw_len = host->pmecc_cw_len;
601 const int16_t cap = host->pmecc_corr_cap;
602 const int num = 2 * cap + 1;
603 int16_t __iomem *index_of = host->pmecc_index_of;
604 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
605 int i, j, k;
606 uint32_t dmu_0_count, tmp;
607 int16_t *smu = host->pmecc_smu;
608
609 /* index of largest delta */
610 int ro;
611 int largest;
612 int diff;
613
614 dmu_0_count = 0;
615
616 /* First Row */
617
618 /* Mu */
619 mu[0] = -1;
620
621 memset(smu, 0, sizeof(int16_t) * num);
622 smu[0] = 1;
623
624 /* discrepancy set to 1 */
625 dmu[0] = 1;
626 /* polynom order set to 0 */
627 lmu[0] = 0;
628 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
629
630 /* Second Row */
631
632 /* Mu */
633 mu[1] = 0;
634 /* Sigma(x) set to 1 */
635 memset(&smu[num], 0, sizeof(int16_t) * num);
636 smu[num] = 1;
637
638 /* discrepancy set to S1 */
639 dmu[1] = si[1];
640
641 /* polynom order set to 0 */
642 lmu[1] = 0;
643
644 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
645
646 /* Init the Sigma(x) last row */
647 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
648
649 for (i = 1; i <= cap; i++) {
650 mu[i + 1] = i << 1;
651 /* Begin Computing Sigma (Mu+1) and L(mu) */
652 /* check if discrepancy is set to 0 */
653 if (dmu[i] == 0) {
654 dmu_0_count++;
655
656 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
657 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
658 tmp += 2;
659 else
660 tmp += 1;
661
662 if (dmu_0_count == tmp) {
663 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
664 smu[(cap + 1) * num + j] =
665 smu[i * num + j];
666
667 lmu[cap + 1] = lmu[i];
668 return;
669 }
670
671 /* copy polynom */
672 for (j = 0; j <= lmu[i] >> 1; j++)
673 smu[(i + 1) * num + j] = smu[i * num + j];
674
675 /* copy previous polynom order to the next */
676 lmu[i + 1] = lmu[i];
677 } else {
678 ro = 0;
679 largest = -1;
680 /* find largest delta with dmu != 0 */
681 for (j = 0; j < i; j++) {
682 if ((dmu[j]) && (delta[j] > largest)) {
683 largest = delta[j];
684 ro = j;
685 }
686 }
687
688 /* compute difference */
689 diff = (mu[i] - mu[ro]);
690
691 /* Compute degree of the new smu polynomial */
692 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
693 lmu[i + 1] = lmu[i];
694 else
695 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
696
697 /* Init smu[i+1] with 0 */
698 for (k = 0; k < num; k++)
699 smu[(i + 1) * num + k] = 0;
700
701 /* Compute smu[i+1] */
702 for (k = 0; k <= lmu[ro] >> 1; k++) {
703 int16_t a, b, c;
704
705 if (!(smu[ro * num + k] && dmu[i]))
706 continue;
707 a = readw_relaxed(index_of + dmu[i]);
708 b = readw_relaxed(index_of + dmu[ro]);
709 c = readw_relaxed(index_of + smu[ro * num + k]);
710 tmp = a + (cw_len - b) + c;
711 a = readw_relaxed(alpha_to + tmp % cw_len);
712 smu[(i + 1) * num + (k + diff)] = a;
713 }
714
715 for (k = 0; k <= lmu[i] >> 1; k++)
716 smu[(i + 1) * num + k] ^= smu[i * num + k];
717 }
718
719 /* End Computing Sigma (Mu+1) and L(mu) */
720 /* In either case compute delta */
721 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
722
723 /* Do not compute discrepancy for the last iteration */
724 if (i >= cap)
725 continue;
726
727 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
728 tmp = 2 * (i - 1);
729 if (k == 0) {
730 dmu[i + 1] = si[tmp + 3];
731 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
732 int16_t a, b, c;
733 a = readw_relaxed(index_of +
734 smu[(i + 1) * num + k]);
735 b = si[2 * (i - 1) + 3 - k];
736 c = readw_relaxed(index_of + b);
737 tmp = a + c;
738 tmp %= cw_len;
739 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
740 dmu[i + 1];
741 }
742 }
743 }
744
745 return;
746}
747
748static int pmecc_err_location(struct mtd_info *mtd)
749{
750 struct nand_chip *nand_chip = mtd_to_nand(mtd);
751 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
752 unsigned long end_time;
753 const int cap = host->pmecc_corr_cap;
754 const int num = 2 * cap + 1;
755 int sector_size = host->pmecc_sector_size;
756 int err_nbr = 0; /* number of error */
757 int roots_nbr; /* number of roots */
758 int i;
759 uint32_t val;
760 int16_t *smu = host->pmecc_smu;
761
762 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
763
764 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
765 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
766 smu[(cap + 1) * num + i]);
767 err_nbr++;
768 }
769
770 val = (err_nbr - 1) << 16;
771 if (sector_size == 1024)
772 val |= 1;
773
774 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
775 pmerrloc_writel(host->pmerrloc_base, ELEN,
776 sector_size * 8 + host->pmecc_degree * cap);
777
778 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
779 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
780 & PMERRLOC_CALC_DONE)) {
781 if (unlikely(time_after(jiffies, end_time))) {
782 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
783 return -1;
784 }
785 cpu_relax();
786 }
787
788 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
789 & PMERRLOC_ERR_NUM_MASK) >> 8;
790 /* Number of roots == degree of smu hence <= cap */
791 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
792 return err_nbr - 1;
793
794 /* Number of roots does not match the degree of smu
795 * unable to correct error */
796 return -1;
797}
798
799static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
800 int sector_num, int extra_bytes, int err_nbr)
801{
802 struct nand_chip *nand_chip = mtd_to_nand(mtd);
803 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
804 int i = 0;
805 int byte_pos, bit_pos, sector_size, pos;
806 uint32_t tmp;
807 uint8_t err_byte;
808
809 sector_size = host->pmecc_sector_size;
810
811 while (err_nbr) {
812 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_el_base, i) - 1;
813 byte_pos = tmp / 8;
814 bit_pos = tmp % 8;
815
816 if (byte_pos >= (sector_size + extra_bytes))
817 BUG(); /* should never happen */
818
819 if (byte_pos < sector_size) {
820 err_byte = *(buf + byte_pos);
821 *(buf + byte_pos) ^= (1 << bit_pos);
822
823 pos = sector_num * host->pmecc_sector_size + byte_pos;
824 dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
825 pos, bit_pos, err_byte, *(buf + byte_pos));
826 } else {
827 struct mtd_oob_region oobregion;
828
829 /* Bit flip in OOB area */
830 tmp = sector_num * nand_chip->ecc.bytes
831 + (byte_pos - sector_size);
832 err_byte = ecc[tmp];
833 ecc[tmp] ^= (1 << bit_pos);
834
835 mtd_ooblayout_ecc(mtd, 0, &oobregion);
836 pos = tmp + oobregion.offset;
837 dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
838 pos, bit_pos, err_byte, ecc[tmp]);
839 }
840
841 i++;
842 err_nbr--;
843 }
844
845 return;
846}
847
848static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
849 u8 *ecc)
850{
851 struct nand_chip *nand_chip = mtd_to_nand(mtd);
852 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
853 int i, err_nbr;
854 uint8_t *buf_pos;
855 int max_bitflips = 0;
856
857 for (i = 0; i < nand_chip->ecc.steps; i++) {
858 err_nbr = 0;
859 if (pmecc_stat & 0x1) {
860 buf_pos = buf + i * host->pmecc_sector_size;
861
862 pmecc_gen_syndrome(mtd, i);
863 pmecc_substitute(mtd);
864 pmecc_get_sigma(mtd);
865
866 err_nbr = pmecc_err_location(mtd);
867 if (err_nbr >= 0) {
868 pmecc_correct_data(mtd, buf_pos, ecc, i,
869 nand_chip->ecc.bytes,
870 err_nbr);
871 } else if (!host->caps->pmecc_correct_erase_page) {
872 u8 *ecc_pos = ecc + (i * nand_chip->ecc.bytes);
873
874 /* Try to detect erased pages */
875 err_nbr = nand_check_erased_ecc_chunk(buf_pos,
876 host->pmecc_sector_size,
877 ecc_pos,
878 nand_chip->ecc.bytes,
879 NULL, 0,
880 nand_chip->ecc.strength);
881 }
882
883 if (err_nbr < 0) {
884 dev_err(host->dev, "PMECC: Too many errors\n");
885 mtd->ecc_stats.failed++;
886 return -EIO;
887 }
888
889 mtd->ecc_stats.corrected += err_nbr;
890 max_bitflips = max_t(int, max_bitflips, err_nbr);
891 }
892 pmecc_stat >>= 1;
893 }
894
895 return max_bitflips;
896}
897
898static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
899{
900 u32 val;
901
902 if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
903 dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
904 return;
905 }
906
907 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
908 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
909 val = pmecc_readl_relaxed(host->ecc, CFG);
910
911 if (ecc_op == NAND_ECC_READ)
912 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
913 | PMECC_CFG_AUTO_ENABLE);
914 else
915 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
916 & ~PMECC_CFG_AUTO_ENABLE);
917
918 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
919 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
920}
921
922static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
923 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
924{
925 struct atmel_nand_host *host = nand_get_controller_data(chip);
926 int eccsize = chip->ecc.size * chip->ecc.steps;
927 uint8_t *oob = chip->oob_poi;
928 uint32_t stat;
929 unsigned long end_time;
930 int bitflips = 0;
931
932 if (!host->nfc || !host->nfc->use_nfc_sram)
933 pmecc_enable(host, NAND_ECC_READ);
934
935 chip->read_buf(mtd, buf, eccsize);
936 chip->read_buf(mtd, oob, mtd->oobsize);
937
938 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
939 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
940 if (unlikely(time_after(jiffies, end_time))) {
941 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
942 return -EIO;
943 }
944 cpu_relax();
945 }
946
947 stat = pmecc_readl_relaxed(host->ecc, ISR);
948 if (stat != 0) {
949 struct mtd_oob_region oobregion;
950
951 mtd_ooblayout_ecc(mtd, 0, &oobregion);
952 bitflips = pmecc_correction(mtd, stat, buf,
953 &oob[oobregion.offset]);
954 if (bitflips < 0)
955 /* uncorrectable errors */
956 return 0;
957 }
958
959 return bitflips;
960}
961
962static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
963 struct nand_chip *chip, const uint8_t *buf, int oob_required,
964 int page)
965{
966 struct atmel_nand_host *host = nand_get_controller_data(chip);
967 struct mtd_oob_region oobregion = { };
968 int i, j, section = 0;
969 unsigned long end_time;
970
971 if (!host->nfc || !host->nfc->write_by_sram) {
972 pmecc_enable(host, NAND_ECC_WRITE);
973 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
974 }
975
976 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
977 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
978 if (unlikely(time_after(jiffies, end_time))) {
979 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
980 return -EIO;
981 }
982 cpu_relax();
983 }
984
985 for (i = 0; i < chip->ecc.steps; i++) {
986 for (j = 0; j < chip->ecc.bytes; j++) {
987 if (!oobregion.length)
988 mtd_ooblayout_ecc(mtd, section, &oobregion);
989
990 chip->oob_poi[oobregion.offset] =
991 pmecc_readb_ecc_relaxed(host->ecc, i, j);
992 oobregion.length--;
993 oobregion.offset++;
994 section++;
995 }
996 }
997 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
998
999 return 0;
1000}
1001
1002static void atmel_pmecc_core_init(struct mtd_info *mtd)
1003{
1004 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1005 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1006 int eccbytes = mtd_ooblayout_count_eccbytes(mtd);
1007 uint32_t val = 0;
1008 struct mtd_oob_region oobregion;
1009
1010 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
1011 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1012
1013 switch (host->pmecc_corr_cap) {
1014 case 2:
1015 val = PMECC_CFG_BCH_ERR2;
1016 break;
1017 case 4:
1018 val = PMECC_CFG_BCH_ERR4;
1019 break;
1020 case 8:
1021 val = PMECC_CFG_BCH_ERR8;
1022 break;
1023 case 12:
1024 val = PMECC_CFG_BCH_ERR12;
1025 break;
1026 case 24:
1027 val = PMECC_CFG_BCH_ERR24;
1028 break;
1029 case 32:
1030 val = PMECC_CFG_BCH_ERR32;
1031 break;
1032 }
1033
1034 if (host->pmecc_sector_size == 512)
1035 val |= PMECC_CFG_SECTOR512;
1036 else if (host->pmecc_sector_size == 1024)
1037 val |= PMECC_CFG_SECTOR1024;
1038
1039 switch (nand_chip->ecc.steps) {
1040 case 1:
1041 val |= PMECC_CFG_PAGE_1SECTOR;
1042 break;
1043 case 2:
1044 val |= PMECC_CFG_PAGE_2SECTORS;
1045 break;
1046 case 4:
1047 val |= PMECC_CFG_PAGE_4SECTORS;
1048 break;
1049 case 8:
1050 val |= PMECC_CFG_PAGE_8SECTORS;
1051 break;
1052 }
1053
1054 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
1055 | PMECC_CFG_AUTO_DISABLE);
1056 pmecc_writel(host->ecc, CFG, val);
1057
1058 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
1059 mtd_ooblayout_ecc(mtd, 0, &oobregion);
1060 pmecc_writel(host->ecc, SADDR, oobregion.offset);
1061 pmecc_writel(host->ecc, EADDR,
1062 oobregion.offset + eccbytes - 1);
1063 /* See datasheet about PMECC Clock Control Register */
1064 pmecc_writel(host->ecc, CLK, 2);
1065 pmecc_writel(host->ecc, IDR, 0xff);
1066 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
1067}
1068
1069/*
1070 * Get minimum ecc requirements from NAND.
1071 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1072 * will set them according to minimum ecc requirement. Otherwise, use the
1073 * value in DTS file.
1074 * return 0 if success. otherwise return error code.
1075 */
1076static int pmecc_choose_ecc(struct atmel_nand_host *host,
1077 int *cap, int *sector_size)
1078{
1079 /* Get minimum ECC requirements */
1080 if (host->nand_chip.ecc_strength_ds) {
1081 *cap = host->nand_chip.ecc_strength_ds;
1082 *sector_size = host->nand_chip.ecc_step_ds;
1083 dev_info(host->dev, "minimum ECC: %d bits in %d bytes\n",
1084 *cap, *sector_size);
1085 } else {
1086 *cap = 2;
1087 *sector_size = 512;
1088 dev_info(host->dev, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
1089 }
1090
1091 /* If device tree doesn't specify, use NAND's minimum ECC parameters */
1092 if (host->pmecc_corr_cap == 0) {
1093 if (*cap > host->caps->pmecc_max_correction)
1094 return -EINVAL;
1095
1096 /* use the most fitable ecc bits (the near bigger one ) */
1097 if (*cap <= 2)
1098 host->pmecc_corr_cap = 2;
1099 else if (*cap <= 4)
1100 host->pmecc_corr_cap = 4;
1101 else if (*cap <= 8)
1102 host->pmecc_corr_cap = 8;
1103 else if (*cap <= 12)
1104 host->pmecc_corr_cap = 12;
1105 else if (*cap <= 24)
1106 host->pmecc_corr_cap = 24;
1107 else if (*cap <= 32)
1108 host->pmecc_corr_cap = 32;
1109 else
1110 return -EINVAL;
1111 }
1112 if (host->pmecc_sector_size == 0) {
1113 /* use the most fitable sector size (the near smaller one ) */
1114 if (*sector_size >= 1024)
1115 host->pmecc_sector_size = 1024;
1116 else if (*sector_size >= 512)
1117 host->pmecc_sector_size = 512;
1118 else
1119 return -EINVAL;
1120 }
1121 return 0;
1122}
1123
1124static inline int deg(unsigned int poly)
1125{
1126 /* polynomial degree is the most-significant bit index */
1127 return fls(poly) - 1;
1128}
1129
1130static int build_gf_tables(int mm, unsigned int poly,
1131 int16_t *index_of, int16_t *alpha_to)
1132{
1133 unsigned int i, x = 1;
1134 const unsigned int k = 1 << deg(poly);
1135 unsigned int nn = (1 << mm) - 1;
1136
1137 /* primitive polynomial must be of degree m */
1138 if (k != (1u << mm))
1139 return -EINVAL;
1140
1141 for (i = 0; i < nn; i++) {
1142 alpha_to[i] = x;
1143 index_of[x] = i;
1144 if (i && (x == 1))
1145 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
1146 return -EINVAL;
1147 x <<= 1;
1148 if (x & k)
1149 x ^= poly;
1150 }
1151 alpha_to[nn] = 1;
1152 index_of[0] = 0;
1153
1154 return 0;
1155}
1156
1157static uint16_t *create_lookup_table(struct device *dev, int sector_size)
1158{
1159 int degree = (sector_size == 512) ?
1160 PMECC_GF_DIMENSION_13 :
1161 PMECC_GF_DIMENSION_14;
1162 unsigned int poly = (sector_size == 512) ?
1163 PMECC_GF_13_PRIMITIVE_POLY :
1164 PMECC_GF_14_PRIMITIVE_POLY;
1165 int table_size = (sector_size == 512) ?
1166 PMECC_LOOKUP_TABLE_SIZE_512 :
1167 PMECC_LOOKUP_TABLE_SIZE_1024;
1168
1169 int16_t *addr = devm_kzalloc(dev, 2 * table_size * sizeof(uint16_t),
1170 GFP_KERNEL);
1171 if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
1172 return NULL;
1173
1174 return addr;
1175}
1176
1177static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
1178 struct atmel_nand_host *host)
1179{
1180 struct nand_chip *nand_chip = &host->nand_chip;
1181 struct mtd_info *mtd = nand_to_mtd(nand_chip);
1182 struct resource *regs, *regs_pmerr, *regs_rom;
1183 uint16_t *galois_table;
1184 int cap, sector_size, err_no;
1185
1186 err_no = pmecc_choose_ecc(host, &cap, &sector_size);
1187 if (err_no) {
1188 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1189 return err_no;
1190 }
1191
1192 if (cap > host->pmecc_corr_cap ||
1193 sector_size != host->pmecc_sector_size)
1194 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1195
1196 cap = host->pmecc_corr_cap;
1197 sector_size = host->pmecc_sector_size;
1198 host->pmecc_lookup_table_offset = (sector_size == 512) ?
1199 host->pmecc_lookup_table_offset_512 :
1200 host->pmecc_lookup_table_offset_1024;
1201
1202 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1203 cap, sector_size);
1204
1205 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1206 if (!regs) {
1207 dev_warn(host->dev,
1208 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1209 nand_chip->ecc.mode = NAND_ECC_SOFT;
1210 nand_chip->ecc.algo = NAND_ECC_HAMMING;
1211 return 0;
1212 }
1213
1214 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1215 if (IS_ERR(host->ecc)) {
1216 err_no = PTR_ERR(host->ecc);
1217 goto err;
1218 }
1219
1220 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1221 host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
1222 if (IS_ERR(host->pmerrloc_base)) {
1223 err_no = PTR_ERR(host->pmerrloc_base);
1224 goto err;
1225 }
1226 host->pmerrloc_el_base = host->pmerrloc_base + ATMEL_PMERRLOC_SIGMAx +
1227 (host->caps->pmecc_max_correction + 1) * 4;
1228
1229 if (!host->has_no_lookup_table) {
1230 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1231 host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev,
1232 regs_rom);
1233 if (IS_ERR(host->pmecc_rom_base)) {
1234 dev_err(host->dev, "Can not get I/O resource for ROM, will build a lookup table in runtime!\n");
1235 host->has_no_lookup_table = true;
1236 }
1237 }
1238
1239 if (host->has_no_lookup_table) {
1240 /* Build the look-up table in runtime */
1241 galois_table = create_lookup_table(host->dev, sector_size);
1242 if (!galois_table) {
1243 dev_err(host->dev, "Failed to build a lookup table in runtime!\n");
1244 err_no = -EINVAL;
1245 goto err;
1246 }
1247
1248 host->pmecc_rom_base = (void __iomem *)galois_table;
1249 host->pmecc_lookup_table_offset = 0;
1250 }
1251
1252 nand_chip->ecc.size = sector_size;
1253
1254 /* set ECC page size and oob layout */
1255 switch (mtd->writesize) {
1256 case 512:
1257 case 1024:
1258 case 2048:
1259 case 4096:
1260 case 8192:
1261 if (sector_size > mtd->writesize) {
1262 dev_err(host->dev, "pmecc sector size is bigger than the page size!\n");
1263 err_no = -EINVAL;
1264 goto err;
1265 }
1266
1267 host->pmecc_degree = (sector_size == 512) ?
1268 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
1269 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1270 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1271 host->pmecc_index_of = host->pmecc_rom_base +
1272 host->pmecc_lookup_table_offset;
1273
1274 nand_chip->ecc.strength = cap;
1275 nand_chip->ecc.bytes = pmecc_get_ecc_bytes(cap, sector_size);
1276 nand_chip->ecc.steps = mtd->writesize / sector_size;
1277 nand_chip->ecc.total = nand_chip->ecc.bytes *
1278 nand_chip->ecc.steps;
1279 if (nand_chip->ecc.total >
1280 mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
1281 dev_err(host->dev, "No room for ECC bytes\n");
1282 err_no = -EINVAL;
1283 goto err;
1284 }
1285
1286 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1287 break;
1288 default:
1289 dev_warn(host->dev,
1290 "Unsupported page size for PMECC, use Software ECC\n");
1291 /* page size not handled by HW ECC */
1292 /* switching back to soft ECC */
1293 nand_chip->ecc.mode = NAND_ECC_SOFT;
1294 nand_chip->ecc.algo = NAND_ECC_HAMMING;
1295 return 0;
1296 }
1297
1298 /* Allocate data for PMECC computation */
1299 err_no = pmecc_data_alloc(host);
1300 if (err_no) {
1301 dev_err(host->dev,
1302 "Cannot allocate memory for PMECC computation!\n");
1303 goto err;
1304 }
1305
1306 nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
1307 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1308 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1309
1310 atmel_pmecc_core_init(mtd);
1311
1312 return 0;
1313
1314err:
1315 return err_no;
1316}
1317
1318/*
1319 * Calculate HW ECC
1320 *
1321 * function called after a write
1322 *
1323 * mtd: MTD block structure
1324 * dat: raw data (unused)
1325 * ecc_code: buffer for ECC
1326 */
1327static int atmel_nand_calculate(struct mtd_info *mtd,
1328 const u_char *dat, unsigned char *ecc_code)
1329{
1330 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1331 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1332 unsigned int ecc_value;
1333
1334 /* get the first 2 ECC bytes */
1335 ecc_value = ecc_readl(host->ecc, PR);
1336
1337 ecc_code[0] = ecc_value & 0xFF;
1338 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1339
1340 /* get the last 2 ECC bytes */
1341 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1342
1343 ecc_code[2] = ecc_value & 0xFF;
1344 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1345
1346 return 0;
1347}
1348
1349/*
1350 * HW ECC read page function
1351 *
1352 * mtd: mtd info structure
1353 * chip: nand chip info structure
1354 * buf: buffer to store read data
1355 * oob_required: caller expects OOB data read to chip->oob_poi
1356 */
1357static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1358 uint8_t *buf, int oob_required, int page)
1359{
1360 int eccsize = chip->ecc.size;
1361 int eccbytes = chip->ecc.bytes;
1362 uint8_t *p = buf;
1363 uint8_t *oob = chip->oob_poi;
1364 uint8_t *ecc_pos;
1365 int stat;
1366 unsigned int max_bitflips = 0;
1367 struct mtd_oob_region oobregion = {};
1368
1369 /*
1370 * Errata: ALE is incorrectly wired up to the ECC controller
1371 * on the AP7000, so it will include the address cycles in the
1372 * ECC calculation.
1373 *
1374 * Workaround: Reset the parity registers before reading the
1375 * actual data.
1376 */
1377 struct atmel_nand_host *host = nand_get_controller_data(chip);
1378 if (host->board.need_reset_workaround)
1379 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1380
1381 /* read the page */
1382 chip->read_buf(mtd, p, eccsize);
1383
1384 /* move to ECC position if needed */
1385 mtd_ooblayout_ecc(mtd, 0, &oobregion);
1386 if (oobregion.offset != 0) {
1387 /*
1388 * This only works on large pages because the ECC controller
1389 * waits for NAND_CMD_RNDOUTSTART after the NAND_CMD_RNDOUT.
1390 * Anyway, for small pages, the first ECC byte is at offset
1391 * 0 in the OOB area.
1392 */
1393 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1394 mtd->writesize + oobregion.offset, -1);
1395 }
1396
1397 /* the ECC controller needs to read the ECC just after the data */
1398 ecc_pos = oob + oobregion.offset;
1399 chip->read_buf(mtd, ecc_pos, eccbytes);
1400
1401 /* check if there's an error */
1402 stat = chip->ecc.correct(mtd, p, oob, NULL);
1403
1404 if (stat < 0) {
1405 mtd->ecc_stats.failed++;
1406 } else {
1407 mtd->ecc_stats.corrected += stat;
1408 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1409 }
1410
1411 /* get back to oob start (end of page) */
1412 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1413
1414 /* read the oob */
1415 chip->read_buf(mtd, oob, mtd->oobsize);
1416
1417 return max_bitflips;
1418}
1419
1420/*
1421 * HW ECC Correction
1422 *
1423 * function called after a read
1424 *
1425 * mtd: MTD block structure
1426 * dat: raw data read from the chip
1427 * read_ecc: ECC from the chip (unused)
1428 * isnull: unused
1429 *
1430 * Detect and correct a 1 bit error for a page
1431 */
1432static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1433 u_char *read_ecc, u_char *isnull)
1434{
1435 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1436 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1437 unsigned int ecc_status;
1438 unsigned int ecc_word, ecc_bit;
1439
1440 /* get the status from the Status Register */
1441 ecc_status = ecc_readl(host->ecc, SR);
1442
1443 /* if there's no error */
1444 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1445 return 0;
1446
1447 /* get error bit offset (4 bits) */
1448 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1449 /* get word address (12 bits) */
1450 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1451 ecc_word >>= 4;
1452
1453 /* if there are multiple errors */
1454 if (ecc_status & ATMEL_ECC_MULERR) {
1455 /* check if it is a freshly erased block
1456 * (filled with 0xff) */
1457 if ((ecc_bit == ATMEL_ECC_BITADDR)
1458 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1459 /* the block has just been erased, return OK */
1460 return 0;
1461 }
1462 /* it doesn't seems to be a freshly
1463 * erased block.
1464 * We can't correct so many errors */
1465 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1466 " Unable to correct.\n");
1467 return -EBADMSG;
1468 }
1469
1470 /* if there's a single bit error : we can correct it */
1471 if (ecc_status & ATMEL_ECC_ECCERR) {
1472 /* there's nothing much to do here.
1473 * the bit error is on the ECC itself.
1474 */
1475 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1476 " Nothing to correct\n");
1477 return 0;
1478 }
1479
1480 dev_dbg(host->dev, "atmel_nand : one bit error on data."
1481 " (word offset in the page :"
1482 " 0x%x bit offset : 0x%x)\n",
1483 ecc_word, ecc_bit);
1484 /* correct the error */
1485 if (nand_chip->options & NAND_BUSWIDTH_16) {
1486 /* 16 bits words */
1487 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1488 } else {
1489 /* 8 bits words */
1490 dat[ecc_word] ^= (1 << ecc_bit);
1491 }
1492 dev_dbg(host->dev, "atmel_nand : error corrected\n");
1493 return 1;
1494}
1495
1496/*
1497 * Enable HW ECC : unused on most chips
1498 */
1499static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1500{
1501 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1502 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1503
1504 if (host->board.need_reset_workaround)
1505 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1506}
1507
1508static int atmel_of_init_ecc(struct atmel_nand_host *host,
1509 struct device_node *np)
1510{
1511 u32 offset[2];
1512 u32 val;
1513
1514 host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1515
1516 /* Not using PMECC */
1517 if (!(host->nand_chip.ecc.mode == NAND_ECC_HW) || !host->has_pmecc)
1518 return 0;
1519
1520 /* use PMECC, get correction capability, sector size and lookup
1521 * table offset.
1522 * If correction bits and sector size are not specified, then find
1523 * them from NAND ONFI parameters.
1524 */
1525 if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1526 if (val > host->caps->pmecc_max_correction) {
1527 dev_err(host->dev,
1528 "Required ECC strength too high: %u max %u\n",
1529 val, host->caps->pmecc_max_correction);
1530 return -EINVAL;
1531 }
1532 if ((val != 2) && (val != 4) && (val != 8) &&
1533 (val != 12) && (val != 24) && (val != 32)) {
1534 dev_err(host->dev,
1535 "Required ECC strength not supported: %u\n",
1536 val);
1537 return -EINVAL;
1538 }
1539 host->pmecc_corr_cap = (u8)val;
1540 }
1541
1542 if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1543 if ((val != 512) && (val != 1024)) {
1544 dev_err(host->dev,
1545 "Required ECC sector size not supported: %u\n",
1546 val);
1547 return -EINVAL;
1548 }
1549 host->pmecc_sector_size = (u16)val;
1550 }
1551
1552 if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1553 offset, 2) != 0) {
1554 dev_err(host->dev, "Cannot get PMECC lookup table offset, will build a lookup table in runtime.\n");
1555 host->has_no_lookup_table = true;
1556 /* Will build a lookup table and initialize the offset later */
1557 return 0;
1558 }
1559
1560 if (!offset[0] && !offset[1]) {
1561 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1562 return -EINVAL;
1563 }
1564
1565 host->pmecc_lookup_table_offset_512 = offset[0];
1566 host->pmecc_lookup_table_offset_1024 = offset[1];
1567
1568 return 0;
1569}
1570
1571static int atmel_of_init_port(struct atmel_nand_host *host,
1572 struct device_node *np)
1573{
1574 u32 val;
1575 struct atmel_nand_data *board = &host->board;
1576 enum of_gpio_flags flags = 0;
1577
1578 host->caps = (struct atmel_nand_caps *)
1579 of_device_get_match_data(host->dev);
1580
1581 if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1582 if (val >= 32) {
1583 dev_err(host->dev, "invalid addr-offset %u\n", val);
1584 return -EINVAL;
1585 }
1586 board->ale = val;
1587 }
1588
1589 if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1590 if (val >= 32) {
1591 dev_err(host->dev, "invalid cmd-offset %u\n", val);
1592 return -EINVAL;
1593 }
1594 board->cle = val;
1595 }
1596
1597 board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1598
1599 board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1600 board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1601
1602 board->enable_pin = of_get_gpio(np, 1);
1603 board->det_pin = of_get_gpio(np, 2);
1604
1605 /* load the nfc driver if there is */
1606 of_platform_populate(np, NULL, NULL, host->dev);
1607
1608 /*
1609 * Initialize ECC mode to NAND_ECC_SOFT so that we have a correct value
1610 * even if the nand-ecc-mode property is not defined.
1611 */
1612 host->nand_chip.ecc.mode = NAND_ECC_SOFT;
1613 host->nand_chip.ecc.algo = NAND_ECC_HAMMING;
1614
1615 return 0;
1616}
1617
1618static int atmel_hw_nand_init_params(struct platform_device *pdev,
1619 struct atmel_nand_host *host)
1620{
1621 struct nand_chip *nand_chip = &host->nand_chip;
1622 struct mtd_info *mtd = nand_to_mtd(nand_chip);
1623 struct resource *regs;
1624
1625 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1626 if (!regs) {
1627 dev_err(host->dev,
1628 "Can't get I/O resource regs, use software ECC\n");
1629 nand_chip->ecc.mode = NAND_ECC_SOFT;
1630 nand_chip->ecc.algo = NAND_ECC_HAMMING;
1631 return 0;
1632 }
1633
1634 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1635 if (IS_ERR(host->ecc))
1636 return PTR_ERR(host->ecc);
1637
1638 /* ECC is calculated for the whole page (1 step) */
1639 nand_chip->ecc.size = mtd->writesize;
1640
1641 /* set ECC page size and oob layout */
1642 switch (mtd->writesize) {
1643 case 512:
1644 mtd_set_ooblayout(mtd, &atmel_ooblayout_sp_ops);
1645 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1646 break;
1647 case 1024:
1648 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1649 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1650 break;
1651 case 2048:
1652 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1653 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1654 break;
1655 case 4096:
1656 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1657 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1658 break;
1659 default:
1660 /* page size not handled by HW ECC */
1661 /* switching back to soft ECC */
1662 nand_chip->ecc.mode = NAND_ECC_SOFT;
1663 nand_chip->ecc.algo = NAND_ECC_HAMMING;
1664 return 0;
1665 }
1666
1667 /* set up for HW ECC */
1668 nand_chip->ecc.calculate = atmel_nand_calculate;
1669 nand_chip->ecc.correct = atmel_nand_correct;
1670 nand_chip->ecc.hwctl = atmel_nand_hwctl;
1671 nand_chip->ecc.read_page = atmel_nand_read_page;
1672 nand_chip->ecc.bytes = 4;
1673 nand_chip->ecc.strength = 1;
1674
1675 return 0;
1676}
1677
1678static inline u32 nfc_read_status(struct atmel_nand_host *host)
1679{
1680 u32 err_flags = NFC_SR_DTOE | NFC_SR_UNDEF | NFC_SR_AWB | NFC_SR_ASE;
1681 u32 nfc_status = nfc_readl(host->nfc->hsmc_regs, SR);
1682
1683 if (unlikely(nfc_status & err_flags)) {
1684 if (nfc_status & NFC_SR_DTOE)
1685 dev_err(host->dev, "NFC: Waiting Nand R/B Timeout Error\n");
1686 else if (nfc_status & NFC_SR_UNDEF)
1687 dev_err(host->dev, "NFC: Access Undefined Area Error\n");
1688 else if (nfc_status & NFC_SR_AWB)
1689 dev_err(host->dev, "NFC: Access memory While NFC is busy\n");
1690 else if (nfc_status & NFC_SR_ASE)
1691 dev_err(host->dev, "NFC: Access memory Size Error\n");
1692 }
1693
1694 return nfc_status;
1695}
1696
1697/* SMC interrupt service routine */
1698static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
1699{
1700 struct atmel_nand_host *host = dev_id;
1701 u32 status, mask, pending;
1702 irqreturn_t ret = IRQ_NONE;
1703
1704 status = nfc_read_status(host);
1705 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1706 pending = status & mask;
1707
1708 if (pending & NFC_SR_XFR_DONE) {
1709 complete(&host->nfc->comp_xfer_done);
1710 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
1711 ret = IRQ_HANDLED;
1712 }
1713 if (pending & NFC_SR_RB_EDGE) {
1714 complete(&host->nfc->comp_ready);
1715 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
1716 ret = IRQ_HANDLED;
1717 }
1718 if (pending & NFC_SR_CMD_DONE) {
1719 complete(&host->nfc->comp_cmd_done);
1720 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
1721 ret = IRQ_HANDLED;
1722 }
1723
1724 return ret;
1725}
1726
1727/* NFC(Nand Flash Controller) related functions */
1728static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
1729{
1730 if (flag & NFC_SR_XFR_DONE)
1731 init_completion(&host->nfc->comp_xfer_done);
1732
1733 if (flag & NFC_SR_RB_EDGE)
1734 init_completion(&host->nfc->comp_ready);
1735
1736 if (flag & NFC_SR_CMD_DONE)
1737 init_completion(&host->nfc->comp_cmd_done);
1738
1739 /* Enable interrupt that need to wait for */
1740 nfc_writel(host->nfc->hsmc_regs, IER, flag);
1741}
1742
1743static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
1744{
1745 int i, index = 0;
1746 struct completion *comp[3]; /* Support 3 interrupt completion */
1747
1748 if (flag & NFC_SR_XFR_DONE)
1749 comp[index++] = &host->nfc->comp_xfer_done;
1750
1751 if (flag & NFC_SR_RB_EDGE)
1752 comp[index++] = &host->nfc->comp_ready;
1753
1754 if (flag & NFC_SR_CMD_DONE)
1755 comp[index++] = &host->nfc->comp_cmd_done;
1756
1757 if (index == 0) {
1758 dev_err(host->dev, "Unknown interrupt flag: 0x%08x\n", flag);
1759 return -EINVAL;
1760 }
1761
1762 for (i = 0; i < index; i++) {
1763 if (wait_for_completion_timeout(comp[i],
1764 msecs_to_jiffies(NFC_TIME_OUT_MS)))
1765 continue; /* wait for next completion */
1766 else
1767 goto err_timeout;
1768 }
1769
1770 return 0;
1771
1772err_timeout:
1773 dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
1774 /* Disable the interrupt as it is not handled by interrupt handler */
1775 nfc_writel(host->nfc->hsmc_regs, IDR, flag);
1776 return -ETIMEDOUT;
1777}
1778
1779static int nfc_send_command(struct atmel_nand_host *host,
1780 unsigned int cmd, unsigned int addr, unsigned char cycle0)
1781{
1782 unsigned long timeout;
1783 u32 flag = NFC_SR_CMD_DONE;
1784 flag |= cmd & NFCADDR_CMD_DATAEN ? NFC_SR_XFR_DONE : 0;
1785
1786 dev_dbg(host->dev,
1787 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1788 cmd, addr, cycle0);
1789
1790 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1791 while (nfc_readl(host->nfc->hsmc_regs, SR) & NFC_SR_BUSY) {
1792 if (time_after(jiffies, timeout)) {
1793 dev_err(host->dev,
1794 "Time out to wait for NFC ready!\n");
1795 return -ETIMEDOUT;
1796 }
1797 }
1798
1799 nfc_prepare_interrupt(host, flag);
1800 nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
1801 nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
1802 return nfc_wait_interrupt(host, flag);
1803}
1804
1805static int nfc_device_ready(struct mtd_info *mtd)
1806{
1807 u32 status, mask;
1808 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1809 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1810
1811 status = nfc_read_status(host);
1812 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1813
1814 /* The mask should be 0. If not we may lost interrupts */
1815 if (unlikely(mask & status))
1816 dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
1817 mask & status);
1818
1819 return status & NFC_SR_RB_EDGE;
1820}
1821
1822static void nfc_select_chip(struct mtd_info *mtd, int chip)
1823{
1824 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1825 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1826
1827 if (chip == -1)
1828 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
1829 else
1830 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
1831}
1832
1833static int nfc_make_addr(struct mtd_info *mtd, int command, int column,
1834 int page_addr, unsigned int *addr1234, unsigned int *cycle0)
1835{
1836 struct nand_chip *chip = mtd_to_nand(mtd);
1837
1838 int acycle = 0;
1839 unsigned char addr_bytes[8];
1840 int index = 0, bit_shift;
1841
1842 BUG_ON(addr1234 == NULL || cycle0 == NULL);
1843
1844 *cycle0 = 0;
1845 *addr1234 = 0;
1846
1847 if (column != -1) {
1848 if (chip->options & NAND_BUSWIDTH_16 &&
1849 !nand_opcode_8bits(command))
1850 column >>= 1;
1851 addr_bytes[acycle++] = column & 0xff;
1852 if (mtd->writesize > 512)
1853 addr_bytes[acycle++] = (column >> 8) & 0xff;
1854 }
1855
1856 if (page_addr != -1) {
1857 addr_bytes[acycle++] = page_addr & 0xff;
1858 addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
1859 if (chip->chipsize > (128 << 20))
1860 addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
1861 }
1862
1863 if (acycle > 4)
1864 *cycle0 = addr_bytes[index++];
1865
1866 for (bit_shift = 0; index < acycle; bit_shift += 8)
1867 *addr1234 += addr_bytes[index++] << bit_shift;
1868
1869 /* return acycle in cmd register */
1870 return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
1871}
1872
1873static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
1874 int column, int page_addr)
1875{
1876 struct nand_chip *chip = mtd_to_nand(mtd);
1877 struct atmel_nand_host *host = nand_get_controller_data(chip);
1878 unsigned long timeout;
1879 unsigned int nfc_addr_cmd = 0;
1880
1881 unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1882
1883 /* Set default settings: no cmd2, no addr cycle. read from nand */
1884 unsigned int cmd2 = 0;
1885 unsigned int vcmd2 = 0;
1886 int acycle = NFCADDR_CMD_ACYCLE_NONE;
1887 int csid = NFCADDR_CMD_CSID_3;
1888 int dataen = NFCADDR_CMD_DATADIS;
1889 int nfcwr = NFCADDR_CMD_NFCRD;
1890 unsigned int addr1234 = 0;
1891 unsigned int cycle0 = 0;
1892 bool do_addr = true;
1893 host->nfc->data_in_sram = NULL;
1894
1895 dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1896 __func__, command, column, page_addr);
1897
1898 switch (command) {
1899 case NAND_CMD_RESET:
1900 nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
1901 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1902 udelay(chip->chip_delay);
1903
1904 nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
1905 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1906 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
1907 if (time_after(jiffies, timeout)) {
1908 dev_err(host->dev,
1909 "Time out to wait status ready!\n");
1910 break;
1911 }
1912 }
1913 return;
1914 case NAND_CMD_STATUS:
1915 do_addr = false;
1916 break;
1917 case NAND_CMD_PARAM:
1918 case NAND_CMD_READID:
1919 do_addr = false;
1920 acycle = NFCADDR_CMD_ACYCLE_1;
1921 if (column != -1)
1922 addr1234 = column;
1923 break;
1924 case NAND_CMD_RNDOUT:
1925 cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
1926 vcmd2 = NFCADDR_CMD_VCMD2;
1927 break;
1928 case NAND_CMD_READ0:
1929 case NAND_CMD_READOOB:
1930 if (command == NAND_CMD_READOOB) {
1931 column += mtd->writesize;
1932 command = NAND_CMD_READ0; /* only READ0 is valid */
1933 cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1934 }
1935 if (host->nfc->use_nfc_sram) {
1936 /* Enable Data transfer to sram */
1937 dataen = NFCADDR_CMD_DATAEN;
1938
1939 /* Need enable PMECC now, since NFC will transfer
1940 * data in bus after sending nfc read command.
1941 */
1942 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1943 pmecc_enable(host, NAND_ECC_READ);
1944 }
1945
1946 cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
1947 vcmd2 = NFCADDR_CMD_VCMD2;
1948 break;
1949 /* For prgramming command, the cmd need set to write enable */
1950 case NAND_CMD_PAGEPROG:
1951 case NAND_CMD_SEQIN:
1952 case NAND_CMD_RNDIN:
1953 nfcwr = NFCADDR_CMD_NFCWR;
1954 if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
1955 dataen = NFCADDR_CMD_DATAEN;
1956 break;
1957 default:
1958 break;
1959 }
1960
1961 if (do_addr)
1962 acycle = nfc_make_addr(mtd, command, column, page_addr,
1963 &addr1234, &cycle0);
1964
1965 nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
1966 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1967
1968 /*
1969 * Program and erase have their own busy handlers status, sequential
1970 * in, and deplete1 need no delay.
1971 */
1972 switch (command) {
1973 case NAND_CMD_CACHEDPROG:
1974 case NAND_CMD_PAGEPROG:
1975 case NAND_CMD_ERASE1:
1976 case NAND_CMD_ERASE2:
1977 case NAND_CMD_RNDIN:
1978 case NAND_CMD_STATUS:
1979 case NAND_CMD_RNDOUT:
1980 case NAND_CMD_SEQIN:
1981 case NAND_CMD_READID:
1982 return;
1983
1984 case NAND_CMD_READ0:
1985 if (dataen == NFCADDR_CMD_DATAEN) {
1986 host->nfc->data_in_sram = host->nfc->sram_bank0 +
1987 nfc_get_sram_off(host);
1988 return;
1989 }
1990 /* fall through */
1991 default:
1992 nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
1993 nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
1994 }
1995}
1996
1997static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1998 uint32_t offset, int data_len, const uint8_t *buf,
1999 int oob_required, int page, int cached, int raw)
2000{
2001 int cfg, len;
2002 int status = 0;
2003 struct atmel_nand_host *host = nand_get_controller_data(chip);
2004 void *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
2005
2006 /* Subpage write is not supported */
2007 if (offset || (data_len < mtd->writesize))
2008 return -EINVAL;
2009
2010 len = mtd->writesize;
2011 /* Copy page data to sram that will write to nand via NFC */
2012 if (use_dma) {
2013 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
2014 /* Fall back to use cpu copy */
2015 memcpy(sram, buf, len);
2016 } else {
2017 memcpy(sram, buf, len);
2018 }
2019
2020 cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
2021 if (unlikely(raw) && oob_required) {
2022 memcpy(sram + len, chip->oob_poi, mtd->oobsize);
2023 len += mtd->oobsize;
2024 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
2025 } else {
2026 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
2027 }
2028
2029 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
2030 /*
2031 * When use NFC sram, need set up PMECC before send
2032 * NAND_CMD_SEQIN command. Since when the nand command
2033 * is sent, nfc will do transfer from sram and nand.
2034 */
2035 pmecc_enable(host, NAND_ECC_WRITE);
2036
2037 host->nfc->will_write_sram = true;
2038 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2039 host->nfc->will_write_sram = false;
2040
2041 if (likely(!raw))
2042 /* Need to write ecc into oob */
2043 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2044 page);
2045
2046 if (status < 0)
2047 return status;
2048
2049 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2050 status = chip->waitfunc(mtd, chip);
2051
2052 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2053 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
2054
2055 if (status & NAND_STATUS_FAIL)
2056 return -EIO;
2057
2058 return 0;
2059}
2060
2061static int nfc_sram_init(struct mtd_info *mtd)
2062{
2063 struct nand_chip *chip = mtd_to_nand(mtd);
2064 struct atmel_nand_host *host = nand_get_controller_data(chip);
2065 int res = 0;
2066
2067 /* Initialize the NFC CFG register */
2068 unsigned int cfg_nfc = 0;
2069
2070 /* set page size and oob layout */
2071 switch (mtd->writesize) {
2072 case 512:
2073 cfg_nfc = NFC_CFG_PAGESIZE_512;
2074 break;
2075 case 1024:
2076 cfg_nfc = NFC_CFG_PAGESIZE_1024;
2077 break;
2078 case 2048:
2079 cfg_nfc = NFC_CFG_PAGESIZE_2048;
2080 break;
2081 case 4096:
2082 cfg_nfc = NFC_CFG_PAGESIZE_4096;
2083 break;
2084 case 8192:
2085 cfg_nfc = NFC_CFG_PAGESIZE_8192;
2086 break;
2087 default:
2088 dev_err(host->dev, "Unsupported page size for NFC.\n");
2089 res = -ENXIO;
2090 return res;
2091 }
2092
2093 /* oob bytes size = (NFCSPARESIZE + 1) * 4
2094 * Max support spare size is 512 bytes. */
2095 cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
2096 & NFC_CFG_NFC_SPARESIZE);
2097 /* default set a max timeout */
2098 cfg_nfc |= NFC_CFG_RSPARE |
2099 NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;
2100
2101 nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);
2102
2103 host->nfc->will_write_sram = false;
2104 nfc_set_sram_bank(host, 0);
2105
2106 /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
2107 if (host->nfc->write_by_sram) {
2108 if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
2109 chip->ecc.mode == NAND_ECC_NONE)
2110 chip->write_page = nfc_sram_write_page;
2111 else
2112 host->nfc->write_by_sram = false;
2113 }
2114
2115 dev_info(host->dev, "Using NFC Sram read %s\n",
2116 host->nfc->write_by_sram ? "and write" : "");
2117 return 0;
2118}
2119
2120static struct platform_driver atmel_nand_nfc_driver;
2121/*
2122 * Probe for the NAND device.
2123 */
2124static int atmel_nand_probe(struct platform_device *pdev)
2125{
2126 struct atmel_nand_host *host;
2127 struct mtd_info *mtd;
2128 struct nand_chip *nand_chip;
2129 struct resource *mem;
2130 int res, irq;
2131
2132 /* Allocate memory for the device structure (and zero it) */
2133 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2134 if (!host)
2135 return -ENOMEM;
2136
2137 res = platform_driver_register(&atmel_nand_nfc_driver);
2138 if (res)
2139 dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");
2140
2141 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2142 host->io_base = devm_ioremap_resource(&pdev->dev, mem);
2143 if (IS_ERR(host->io_base)) {
2144 res = PTR_ERR(host->io_base);
2145 goto err_nand_ioremap;
2146 }
2147 host->io_phys = (dma_addr_t)mem->start;
2148
2149 nand_chip = &host->nand_chip;
2150 mtd = nand_to_mtd(nand_chip);
2151 host->dev = &pdev->dev;
2152 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
2153 nand_set_flash_node(nand_chip, pdev->dev.of_node);
2154 /* Only when CONFIG_OF is enabled of_node can be parsed */
2155 res = atmel_of_init_port(host, pdev->dev.of_node);
2156 if (res)
2157 goto err_nand_ioremap;
2158 } else {
2159 memcpy(&host->board, dev_get_platdata(&pdev->dev),
2160 sizeof(struct atmel_nand_data));
2161 nand_chip->ecc.mode = host->board.ecc_mode;
2162
2163 /*
2164 * When using software ECC every supported avr32 board means
2165 * Hamming algorithm. If that ever changes we'll need to add
2166 * ecc_algo field to the struct atmel_nand_data.
2167 */
2168 if (nand_chip->ecc.mode == NAND_ECC_SOFT)
2169 nand_chip->ecc.algo = NAND_ECC_HAMMING;
2170
2171 /* 16-bit bus width */
2172 if (host->board.bus_width_16)
2173 nand_chip->options |= NAND_BUSWIDTH_16;
2174 }
2175
2176 /* link the private data structures */
2177 nand_set_controller_data(nand_chip, host);
2178 mtd->dev.parent = &pdev->dev;
2179
2180 /* Set address of NAND IO lines */
2181 nand_chip->IO_ADDR_R = host->io_base;
2182 nand_chip->IO_ADDR_W = host->io_base;
2183
2184 if (nand_nfc.is_initialized) {
2185 /* NFC driver is probed and initialized */
2186 host->nfc = &nand_nfc;
2187
2188 nand_chip->select_chip = nfc_select_chip;
2189 nand_chip->dev_ready = nfc_device_ready;
2190 nand_chip->cmdfunc = nfc_nand_command;
2191
2192 /* Initialize the interrupt for NFC */
2193 irq = platform_get_irq(pdev, 0);
2194 if (irq < 0) {
2195 dev_err(host->dev, "Cannot get HSMC irq!\n");
2196 res = irq;
2197 goto err_nand_ioremap;
2198 }
2199
2200 res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
2201 0, "hsmc", host);
2202 if (res) {
2203 dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
2204 irq);
2205 goto err_nand_ioremap;
2206 }
2207 } else {
2208 res = atmel_nand_set_enable_ready_pins(mtd);
2209 if (res)
2210 goto err_nand_ioremap;
2211
2212 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
2213 }
2214
2215 nand_chip->chip_delay = 40; /* 40us command delay time */
2216
2217
2218 nand_chip->read_buf = atmel_read_buf;
2219 nand_chip->write_buf = atmel_write_buf;
2220
2221 platform_set_drvdata(pdev, host);
2222 atmel_nand_enable(host);
2223
2224 if (gpio_is_valid(host->board.det_pin)) {
2225 res = devm_gpio_request(&pdev->dev,
2226 host->board.det_pin, "nand_det");
2227 if (res < 0) {
2228 dev_err(&pdev->dev,
2229 "can't request det gpio %d\n",
2230 host->board.det_pin);
2231 goto err_no_card;
2232 }
2233
2234 res = gpio_direction_input(host->board.det_pin);
2235 if (res < 0) {
2236 dev_err(&pdev->dev,
2237 "can't request input direction det gpio %d\n",
2238 host->board.det_pin);
2239 goto err_no_card;
2240 }
2241
2242 if (gpio_get_value(host->board.det_pin)) {
2243 dev_info(&pdev->dev, "No SmartMedia card inserted.\n");
2244 res = -ENXIO;
2245 goto err_no_card;
2246 }
2247 }
2248
2249 if (!host->board.has_dma)
2250 use_dma = 0;
2251
2252 if (use_dma) {
2253 dma_cap_mask_t mask;
2254
2255 dma_cap_zero(mask);
2256 dma_cap_set(DMA_MEMCPY, mask);
2257 host->dma_chan = dma_request_channel(mask, NULL, NULL);
2258 if (!host->dma_chan) {
2259 dev_err(host->dev, "Failed to request DMA channel\n");
2260 use_dma = 0;
2261 }
2262 }
2263 if (use_dma)
2264 dev_info(host->dev, "Using %s for DMA transfers.\n",
2265 dma_chan_name(host->dma_chan));
2266 else
2267 dev_info(host->dev, "No DMA support for NAND access.\n");
2268
2269 /* first scan to find the device and get the page size */
2270 res = nand_scan_ident(mtd, 1, NULL);
2271 if (res)
2272 goto err_scan_ident;
2273
2274 if (host->board.on_flash_bbt || on_flash_bbt)
2275 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2276
2277 if (nand_chip->bbt_options & NAND_BBT_USE_FLASH)
2278 dev_info(&pdev->dev, "Use On Flash BBT\n");
2279
2280 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
2281 res = atmel_of_init_ecc(host, pdev->dev.of_node);
2282 if (res)
2283 goto err_hw_ecc;
2284 }
2285
2286 if (nand_chip->ecc.mode == NAND_ECC_HW) {
2287 if (host->has_pmecc)
2288 res = atmel_pmecc_nand_init_params(pdev, host);
2289 else
2290 res = atmel_hw_nand_init_params(pdev, host);
2291
2292 if (res != 0)
2293 goto err_hw_ecc;
2294 }
2295
2296 /* initialize the nfc configuration register */
2297 if (host->nfc && host->nfc->use_nfc_sram) {
2298 res = nfc_sram_init(mtd);
2299 if (res) {
2300 host->nfc->use_nfc_sram = false;
2301 dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
2302 }
2303 }
2304
2305 /* second phase scan */
2306 res = nand_scan_tail(mtd);
2307 if (res)
2308 goto err_scan_tail;
2309
2310 mtd->name = "atmel_nand";
2311 res = mtd_device_register(mtd, host->board.parts,
2312 host->board.num_parts);
2313 if (!res)
2314 return res;
2315
2316err_scan_tail:
2317 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
2318 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2319err_hw_ecc:
2320err_scan_ident:
2321err_no_card:
2322 atmel_nand_disable(host);
2323 if (host->dma_chan)
2324 dma_release_channel(host->dma_chan);
2325err_nand_ioremap:
2326 return res;
2327}
2328
2329/*
2330 * Remove a NAND device.
2331 */
2332static int atmel_nand_remove(struct platform_device *pdev)
2333{
2334 struct atmel_nand_host *host = platform_get_drvdata(pdev);
2335 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
2336
2337 nand_release(mtd);
2338
2339 atmel_nand_disable(host);
2340
2341 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
2342 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2343 pmerrloc_writel(host->pmerrloc_base, ELDIS,
2344 PMERRLOC_DISABLE);
2345 }
2346
2347 if (host->dma_chan)
2348 dma_release_channel(host->dma_chan);
2349
2350 platform_driver_unregister(&atmel_nand_nfc_driver);
2351
2352 return 0;
2353}
2354
2355/*
2356 * AT91RM9200 does not have PMECC or PMECC Errloc peripherals for
2357 * BCH ECC. Combined with the "atmel,has-pmecc", it is used to describe
2358 * devices from the SAM9 family that have those.
2359 */
2360static const struct atmel_nand_caps at91rm9200_caps = {
2361 .pmecc_correct_erase_page = false,
2362 .pmecc_max_correction = 24,
2363};
2364
2365static const struct atmel_nand_caps sama5d4_caps = {
2366 .pmecc_correct_erase_page = true,
2367 .pmecc_max_correction = 24,
2368};
2369
2370/*
2371 * The PMECC Errloc controller starting in SAMA5D2 is not compatible,
2372 * as the increased correction strength requires more registers.
2373 */
2374static const struct atmel_nand_caps sama5d2_caps = {
2375 .pmecc_correct_erase_page = true,
2376 .pmecc_max_correction = 32,
2377};
2378
2379static const struct of_device_id atmel_nand_dt_ids[] = {
2380 { .compatible = "atmel,at91rm9200-nand", .data = &at91rm9200_caps },
2381 { .compatible = "atmel,sama5d4-nand", .data = &sama5d4_caps },
2382 { .compatible = "atmel,sama5d2-nand", .data = &sama5d2_caps },
2383 { /* sentinel */ }
2384};
2385
2386MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
2387
2388static int atmel_nand_nfc_probe(struct platform_device *pdev)
2389{
2390 struct atmel_nfc *nfc = &nand_nfc;
2391 struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2392 int ret;
2393
2394 nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2395 nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
2396 if (IS_ERR(nfc->base_cmd_regs))
2397 return PTR_ERR(nfc->base_cmd_regs);
2398
2399 nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2400 nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
2401 if (IS_ERR(nfc->hsmc_regs))
2402 return PTR_ERR(nfc->hsmc_regs);
2403
2404 nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2405 if (nfc_sram) {
2406 nfc->sram_bank0 = (void * __force)
2407 devm_ioremap_resource(&pdev->dev, nfc_sram);
2408 if (IS_ERR(nfc->sram_bank0)) {
2409 dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2410 PTR_ERR(nfc->sram_bank0));
2411 } else {
2412 nfc->use_nfc_sram = true;
2413 nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
2414
2415 if (pdev->dev.of_node)
2416 nfc->write_by_sram = of_property_read_bool(
2417 pdev->dev.of_node,
2418 "atmel,write-by-sram");
2419 }
2420 }
2421
2422 nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
2423 nfc_readl(nfc->hsmc_regs, SR); /* clear the NFC_SR */
2424
2425 nfc->clk = devm_clk_get(&pdev->dev, NULL);
2426 if (!IS_ERR(nfc->clk)) {
2427 ret = clk_prepare_enable(nfc->clk);
2428 if (ret)
2429 return ret;
2430 } else {
2431 dev_warn(&pdev->dev, "NFC clock missing, update your Device Tree");
2432 }
2433
2434 nfc->is_initialized = true;
2435 dev_info(&pdev->dev, "NFC is probed.\n");
2436
2437 return 0;
2438}
2439
2440static int atmel_nand_nfc_remove(struct platform_device *pdev)
2441{
2442 struct atmel_nfc *nfc = &nand_nfc;
2443
2444 if (!IS_ERR(nfc->clk))
2445 clk_disable_unprepare(nfc->clk);
2446
2447 return 0;
2448}
2449
2450static const struct of_device_id atmel_nand_nfc_match[] = {
2451 { .compatible = "atmel,sama5d3-nfc" },
2452 { /* sentinel */ }
2453};
2454MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
2455
2456static struct platform_driver atmel_nand_nfc_driver = {
2457 .driver = {
2458 .name = "atmel_nand_nfc",
2459 .of_match_table = of_match_ptr(atmel_nand_nfc_match),
2460 },
2461 .probe = atmel_nand_nfc_probe,
2462 .remove = atmel_nand_nfc_remove,
2463};
2464
2465static struct platform_driver atmel_nand_driver = {
2466 .probe = atmel_nand_probe,
2467 .remove = atmel_nand_remove,
2468 .driver = {
2469 .name = "atmel_nand",
2470 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
2471 },
2472};
2473
2474module_platform_driver(atmel_nand_driver);
2475
2476MODULE_LICENSE("GPL");
2477MODULE_AUTHOR("Rick Bronson");
2478MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
2479MODULE_ALIAS("platform:atmel_nand");
diff --git a/drivers/mtd/nand/atmel_nand_ecc.h b/drivers/mtd/nand/atmel_nand_ecc.h
deleted file mode 100644
index 834d694487bd..000000000000
--- a/drivers/mtd/nand/atmel_nand_ecc.h
+++ /dev/null
@@ -1,163 +0,0 @@
1/*
2 * Error Corrected Code Controller (ECC) - System peripherals regsters.
3 * Based on AT91SAM9260 datasheet revision B.
4 *
5 * Copyright (C) 2007 Andrew Victor
6 * Copyright (C) 2007 - 2012 Atmel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifndef ATMEL_NAND_ECC_H
15#define ATMEL_NAND_ECC_H
16
17#define ATMEL_ECC_CR 0x00 /* Control register */
18#define ATMEL_ECC_RST (1 << 0) /* Reset parity */
19
20#define ATMEL_ECC_MR 0x04 /* Mode register */
21#define ATMEL_ECC_PAGESIZE (3 << 0) /* Page Size */
22#define ATMEL_ECC_PAGESIZE_528 (0)
23#define ATMEL_ECC_PAGESIZE_1056 (1)
24#define ATMEL_ECC_PAGESIZE_2112 (2)
25#define ATMEL_ECC_PAGESIZE_4224 (3)
26
27#define ATMEL_ECC_SR 0x08 /* Status register */
28#define ATMEL_ECC_RECERR (1 << 0) /* Recoverable Error */
29#define ATMEL_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
30#define ATMEL_ECC_MULERR (1 << 2) /* Multiple Errors */
31
32#define ATMEL_ECC_PR 0x0c /* Parity register */
33#define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */
34#define ATMEL_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
35
36#define ATMEL_ECC_NPR 0x10 /* NParity register */
37#define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */
38
39/* PMECC Register Definitions */
40#define ATMEL_PMECC_CFG 0x000 /* Configuration Register */
41#define PMECC_CFG_BCH_ERR2 (0 << 0)
42#define PMECC_CFG_BCH_ERR4 (1 << 0)
43#define PMECC_CFG_BCH_ERR8 (2 << 0)
44#define PMECC_CFG_BCH_ERR12 (3 << 0)
45#define PMECC_CFG_BCH_ERR24 (4 << 0)
46#define PMECC_CFG_BCH_ERR32 (5 << 0)
47
48#define PMECC_CFG_SECTOR512 (0 << 4)
49#define PMECC_CFG_SECTOR1024 (1 << 4)
50
51#define PMECC_CFG_PAGE_1SECTOR (0 << 8)
52#define PMECC_CFG_PAGE_2SECTORS (1 << 8)
53#define PMECC_CFG_PAGE_4SECTORS (2 << 8)
54#define PMECC_CFG_PAGE_8SECTORS (3 << 8)
55
56#define PMECC_CFG_READ_OP (0 << 12)
57#define PMECC_CFG_WRITE_OP (1 << 12)
58
59#define PMECC_CFG_SPARE_ENABLE (1 << 16)
60#define PMECC_CFG_SPARE_DISABLE (0 << 16)
61
62#define PMECC_CFG_AUTO_ENABLE (1 << 20)
63#define PMECC_CFG_AUTO_DISABLE (0 << 20)
64
65#define ATMEL_PMECC_SAREA 0x004 /* Spare area size */
66#define ATMEL_PMECC_SADDR 0x008 /* PMECC starting address */
67#define ATMEL_PMECC_EADDR 0x00c /* PMECC ending address */
68#define ATMEL_PMECC_CLK 0x010 /* PMECC clock control */
69#define PMECC_CLK_133MHZ (2 << 0)
70
71#define ATMEL_PMECC_CTRL 0x014 /* PMECC control register */
72#define PMECC_CTRL_RST (1 << 0)
73#define PMECC_CTRL_DATA (1 << 1)
74#define PMECC_CTRL_USER (1 << 2)
75#define PMECC_CTRL_ENABLE (1 << 4)
76#define PMECC_CTRL_DISABLE (1 << 5)
77
78#define ATMEL_PMECC_SR 0x018 /* PMECC status register */
79#define PMECC_SR_BUSY (1 << 0)
80#define PMECC_SR_ENABLE (1 << 4)
81
82#define ATMEL_PMECC_IER 0x01c /* PMECC interrupt enable */
83#define PMECC_IER_ENABLE (1 << 0)
84#define ATMEL_PMECC_IDR 0x020 /* PMECC interrupt disable */
85#define PMECC_IER_DISABLE (1 << 0)
86#define ATMEL_PMECC_IMR 0x024 /* PMECC interrupt mask */
87#define PMECC_IER_MASK (1 << 0)
88#define ATMEL_PMECC_ISR 0x028 /* PMECC interrupt status */
89#define ATMEL_PMECC_ECCx 0x040 /* PMECC ECC x */
90#define ATMEL_PMECC_REMx 0x240 /* PMECC REM x */
91
92/* PMERRLOC Register Definitions */
93#define ATMEL_PMERRLOC_ELCFG 0x000 /* Error location config */
94#define PMERRLOC_ELCFG_SECTOR_512 (0 << 0)
95#define PMERRLOC_ELCFG_SECTOR_1024 (1 << 0)
96#define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16)
97
98#define ATMEL_PMERRLOC_ELPRIM 0x004 /* Error location primitive */
99#define ATMEL_PMERRLOC_ELEN 0x008 /* Error location enable */
100#define ATMEL_PMERRLOC_ELDIS 0x00c /* Error location disable */
101#define PMERRLOC_DISABLE (1 << 0)
102
103#define ATMEL_PMERRLOC_ELSR 0x010 /* Error location status */
104#define PMERRLOC_ELSR_BUSY (1 << 0)
105#define ATMEL_PMERRLOC_ELIER 0x014 /* Error location int enable */
106#define ATMEL_PMERRLOC_ELIDR 0x018 /* Error location int disable */
107#define ATMEL_PMERRLOC_ELIMR 0x01c /* Error location int mask */
108#define ATMEL_PMERRLOC_ELISR 0x020 /* Error location int status */
109#define PMERRLOC_ERR_NUM_MASK (0x1f << 8)
110#define PMERRLOC_CALC_DONE (1 << 0)
111#define ATMEL_PMERRLOC_SIGMAx 0x028 /* Error location SIGMA x */
112
113/*
114 * The ATMEL_PMERRLOC_ELx register location depends from the number of
115 * bits corrected by the PMECC controller. Do not use it.
116 */
117
118/* Register access macros for PMECC */
119#define pmecc_readl_relaxed(addr, reg) \
120 readl_relaxed((addr) + ATMEL_PMECC_##reg)
121
122#define pmecc_writel(addr, reg, value) \
123 writel((value), (addr) + ATMEL_PMECC_##reg)
124
125#define pmecc_readb_ecc_relaxed(addr, sector, n) \
126 readb_relaxed((addr) + ATMEL_PMECC_ECCx + ((sector) * 0x40) + (n))
127
128#define pmecc_readl_rem_relaxed(addr, sector, n) \
129 readl_relaxed((addr) + ATMEL_PMECC_REMx + ((sector) * 0x40) + ((n) * 4))
130
131#define pmerrloc_readl_relaxed(addr, reg) \
132 readl_relaxed((addr) + ATMEL_PMERRLOC_##reg)
133
134#define pmerrloc_writel(addr, reg, value) \
135 writel((value), (addr) + ATMEL_PMERRLOC_##reg)
136
137#define pmerrloc_writel_sigma_relaxed(addr, n, value) \
138 writel_relaxed((value), (addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
139
140#define pmerrloc_readl_sigma_relaxed(addr, n) \
141 readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
142
143#define pmerrloc_readl_el_relaxed(addr, n) \
144 readl_relaxed((addr) + ((n) * 4))
145
146/* Galois field dimension */
147#define PMECC_GF_DIMENSION_13 13
148#define PMECC_GF_DIMENSION_14 14
149
150/* Primitive Polynomial used by PMECC */
151#define PMECC_GF_13_PRIMITIVE_POLY 0x201b
152#define PMECC_GF_14_PRIMITIVE_POLY 0x4443
153
154#define PMECC_LOOKUP_TABLE_SIZE_512 0x2000
155#define PMECC_LOOKUP_TABLE_SIZE_1024 0x4000
156
157/* Time out value for reading PMECC status register */
158#define PMECC_MAX_TIMEOUT_MS 100
159
160/* Reserved bytes in oob area */
161#define PMECC_OOB_RESERVED_BYTES 2
162
163#endif
diff --git a/drivers/mtd/nand/atmel_nand_nfc.h b/drivers/mtd/nand/atmel_nand_nfc.h
deleted file mode 100644
index 4d5d26221a7e..000000000000
--- a/drivers/mtd/nand/atmel_nand_nfc.h
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 * Atmel Nand Flash Controller (NFC) - System peripherals regsters.
3 * Based on SAMA5D3 datasheet.
4 *
5 * © Copyright 2013 Atmel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef ATMEL_NAND_NFC_H
14#define ATMEL_NAND_NFC_H
15
16/*
17 * HSMC NFC registers
18 */
19#define ATMEL_HSMC_NFC_CFG 0x00 /* NFC Configuration Register */
20#define NFC_CFG_PAGESIZE (7 << 0)
21#define NFC_CFG_PAGESIZE_512 (0 << 0)
22#define NFC_CFG_PAGESIZE_1024 (1 << 0)
23#define NFC_CFG_PAGESIZE_2048 (2 << 0)
24#define NFC_CFG_PAGESIZE_4096 (3 << 0)
25#define NFC_CFG_PAGESIZE_8192 (4 << 0)
26#define NFC_CFG_WSPARE (1 << 8)
27#define NFC_CFG_RSPARE (1 << 9)
28#define NFC_CFG_NFC_DTOCYC (0xf << 16)
29#define NFC_CFG_NFC_DTOMUL (0x7 << 20)
30#define NFC_CFG_NFC_SPARESIZE (0x7f << 24)
31#define NFC_CFG_NFC_SPARESIZE_BIT_POS 24
32
33#define ATMEL_HSMC_NFC_CTRL 0x04 /* NFC Control Register */
34#define NFC_CTRL_ENABLE (1 << 0)
35#define NFC_CTRL_DISABLE (1 << 1)
36
37#define ATMEL_HSMC_NFC_SR 0x08 /* NFC Status Register */
38#define NFC_SR_BUSY (1 << 8)
39#define NFC_SR_XFR_DONE (1 << 16)
40#define NFC_SR_CMD_DONE (1 << 17)
41#define NFC_SR_DTOE (1 << 20)
42#define NFC_SR_UNDEF (1 << 21)
43#define NFC_SR_AWB (1 << 22)
44#define NFC_SR_ASE (1 << 23)
45#define NFC_SR_RB_EDGE (1 << 24)
46
47#define ATMEL_HSMC_NFC_IER 0x0c
48#define ATMEL_HSMC_NFC_IDR 0x10
49#define ATMEL_HSMC_NFC_IMR 0x14
50#define ATMEL_HSMC_NFC_CYCLE0 0x18 /* NFC Address Cycle Zero */
51#define ATMEL_HSMC_NFC_ADDR_CYCLE0 (0xff)
52
53#define ATMEL_HSMC_NFC_BANK 0x1c /* NFC Bank Register */
54#define ATMEL_HSMC_NFC_BANK0 (0 << 0)
55#define ATMEL_HSMC_NFC_BANK1 (1 << 0)
56
57#define nfc_writel(addr, reg, value) \
58 writel((value), (addr) + ATMEL_HSMC_NFC_##reg)
59
60#define nfc_readl(addr, reg) \
61 readl_relaxed((addr) + ATMEL_HSMC_NFC_##reg)
62
63/*
64 * NFC Address Command definitions
65 */
66#define NFCADDR_CMD_CMD1 (0xff << 2) /* Command for Cycle 1 */
67#define NFCADDR_CMD_CMD1_BIT_POS 2
68#define NFCADDR_CMD_CMD2 (0xff << 10) /* Command for Cycle 2 */
69#define NFCADDR_CMD_CMD2_BIT_POS 10
70#define NFCADDR_CMD_VCMD2 (0x1 << 18) /* Valid Cycle 2 Command */
71#define NFCADDR_CMD_ACYCLE (0x7 << 19) /* Number of Address required */
72#define NFCADDR_CMD_ACYCLE_NONE (0x0 << 19)
73#define NFCADDR_CMD_ACYCLE_1 (0x1 << 19)
74#define NFCADDR_CMD_ACYCLE_2 (0x2 << 19)
75#define NFCADDR_CMD_ACYCLE_3 (0x3 << 19)
76#define NFCADDR_CMD_ACYCLE_4 (0x4 << 19)
77#define NFCADDR_CMD_ACYCLE_5 (0x5 << 19)
78#define NFCADDR_CMD_ACYCLE_BIT_POS 19
79#define NFCADDR_CMD_CSID (0x7 << 22) /* Chip Select Identifier */
80#define NFCADDR_CMD_CSID_0 (0x0 << 22)
81#define NFCADDR_CMD_CSID_1 (0x1 << 22)
82#define NFCADDR_CMD_CSID_2 (0x2 << 22)
83#define NFCADDR_CMD_CSID_3 (0x3 << 22)
84#define NFCADDR_CMD_CSID_4 (0x4 << 22)
85#define NFCADDR_CMD_CSID_5 (0x5 << 22)
86#define NFCADDR_CMD_CSID_6 (0x6 << 22)
87#define NFCADDR_CMD_CSID_7 (0x7 << 22)
88#define NFCADDR_CMD_DATAEN (0x1 << 25) /* Data Transfer Enable */
89#define NFCADDR_CMD_DATADIS (0x0 << 25) /* Data Transfer Disable */
90#define NFCADDR_CMD_NFCRD (0x0 << 26) /* NFC Read Enable */
91#define NFCADDR_CMD_NFCWR (0x1 << 26) /* NFC Write Enable */
92#define NFCADDR_CMD_NFCBUSY (0x1 << 27) /* NFC Busy */
93
94#define nfc_cmd_addr1234_writel(cmd, addr1234, nfc_base) \
95 writel((addr1234), (cmd) + nfc_base)
96
97#define nfc_cmd_readl(bitstatus, nfc_base) \
98 readl_relaxed((bitstatus) + nfc_base)
99
100#define NFC_TIME_OUT_MS 100
101#define NFC_SRAM_BANK1_OFFSET 0x1200
102
103#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-17 05:43:45 -0400