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authorMarek Vasut <marek.vasut@gmail.com>2018-06-11 07:58:41 -0400
committerLee Jones <lee.jones@linaro.org>2018-07-04 02:15:51 -0400
commit8b55734dc8bdc2327d78fcace3811e64a7c7cfec (patch)
tree0058964b35c8833592395550cea21779b94e1740 /drivers/mfd
parent2905086def931d70e61ffd912b1c0ab7c15c6f85 (diff)
mfd: da9063: Use REGMAP_IRQ_REG
Convert the regmap_irq table to use REGMAP_IRQ_REG(). Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Acked-by: Steve Twiss <stwiss.opensource@diasemi.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'drivers/mfd')
-rw-r--r--drivers/mfd/da9063-irq.c175
1 files changed, 58 insertions, 117 deletions
diff --git a/drivers/mfd/da9063-irq.c b/drivers/mfd/da9063-irq.c
index da6ceb41f0d1..044bd867f540 100644
--- a/drivers/mfd/da9063-irq.c
+++ b/drivers/mfd/da9063-irq.c
@@ -28,132 +28,73 @@
28 28
29static const struct regmap_irq da9063_irqs[] = { 29static const struct regmap_irq da9063_irqs[] = {
30 /* DA9063 event A register */ 30 /* DA9063 event A register */
31 [DA9063_IRQ_ONKEY] = { 31 REGMAP_IRQ_REG(DA9063_IRQ_ONKEY,
32 .reg_offset = DA9063_REG_EVENT_A_OFFSET, 32 DA9063_REG_EVENT_A_OFFSET, DA9063_M_ONKEY),
33 .mask = DA9063_M_ONKEY, 33 REGMAP_IRQ_REG(DA9063_IRQ_ALARM,
34 }, 34 DA9063_REG_EVENT_A_OFFSET, DA9063_M_ALARM),
35 [DA9063_IRQ_ALARM] = { 35 REGMAP_IRQ_REG(DA9063_IRQ_TICK,
36 .reg_offset = DA9063_REG_EVENT_A_OFFSET, 36 DA9063_REG_EVENT_A_OFFSET, DA9063_M_TICK),
37 .mask = DA9063_M_ALARM, 37 REGMAP_IRQ_REG(DA9063_IRQ_ADC_RDY,
38 }, 38 DA9063_REG_EVENT_A_OFFSET, DA9063_M_ADC_RDY),
39 [DA9063_IRQ_TICK] = { 39 REGMAP_IRQ_REG(DA9063_IRQ_SEQ_RDY,
40 .reg_offset = DA9063_REG_EVENT_A_OFFSET, 40 DA9063_REG_EVENT_A_OFFSET, DA9063_M_SEQ_RDY),
41 .mask = DA9063_M_TICK,
42 },
43 [DA9063_IRQ_ADC_RDY] = {
44 .reg_offset = DA9063_REG_EVENT_A_OFFSET,
45 .mask = DA9063_M_ADC_RDY,
46 },
47 [DA9063_IRQ_SEQ_RDY] = {
48 .reg_offset = DA9063_REG_EVENT_A_OFFSET,
49 .mask = DA9063_M_SEQ_RDY,
50 },
51 /* DA9063 event B register */ 41 /* DA9063 event B register */
52 [DA9063_IRQ_WAKE] = { 42 REGMAP_IRQ_REG(DA9063_IRQ_WAKE,
53 .reg_offset = DA9063_REG_EVENT_B_OFFSET, 43 DA9063_REG_EVENT_B_OFFSET, DA9063_M_WAKE),
54 .mask = DA9063_M_WAKE, 44 REGMAP_IRQ_REG(DA9063_IRQ_TEMP,
55 }, 45 DA9063_REG_EVENT_B_OFFSET, DA9063_M_TEMP),
56 [DA9063_IRQ_TEMP] = { 46 REGMAP_IRQ_REG(DA9063_IRQ_COMP_1V2,
57 .reg_offset = DA9063_REG_EVENT_B_OFFSET, 47 DA9063_REG_EVENT_B_OFFSET, DA9063_M_COMP_1V2),
58 .mask = DA9063_M_TEMP, 48 REGMAP_IRQ_REG(DA9063_IRQ_LDO_LIM,
59 }, 49 DA9063_REG_EVENT_B_OFFSET, DA9063_M_LDO_LIM),
60 [DA9063_IRQ_COMP_1V2] = { 50 REGMAP_IRQ_REG(DA9063_IRQ_REG_UVOV,
61 .reg_offset = DA9063_REG_EVENT_B_OFFSET, 51 DA9063_REG_EVENT_B_OFFSET, DA9063_M_UVOV),
62 .mask = DA9063_M_COMP_1V2, 52 REGMAP_IRQ_REG(DA9063_IRQ_DVC_RDY,
63 }, 53 DA9063_REG_EVENT_B_OFFSET, DA9063_M_DVC_RDY),
64 [DA9063_IRQ_LDO_LIM] = { 54 REGMAP_IRQ_REG(DA9063_IRQ_VDD_MON,
65 .reg_offset = DA9063_REG_EVENT_B_OFFSET, 55 DA9063_REG_EVENT_B_OFFSET, DA9063_M_VDD_MON),
66 .mask = DA9063_M_LDO_LIM, 56 REGMAP_IRQ_REG(DA9063_IRQ_WARN,
67 }, 57 DA9063_REG_EVENT_B_OFFSET, DA9063_M_VDD_WARN),
68 [DA9063_IRQ_REG_UVOV] = {
69 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
70 .mask = DA9063_M_UVOV,
71 },
72 [DA9063_IRQ_DVC_RDY] = {
73 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
74 .mask = DA9063_M_DVC_RDY,
75 },
76 [DA9063_IRQ_VDD_MON] = {
77 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
78 .mask = DA9063_M_VDD_MON,
79 },
80 [DA9063_IRQ_WARN] = {
81 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
82 .mask = DA9063_M_VDD_WARN,
83 },
84 /* DA9063 event C register */ 58 /* DA9063 event C register */
85 [DA9063_IRQ_GPI0] = { 59 REGMAP_IRQ_REG(DA9063_IRQ_GPI0,
86 .reg_offset = DA9063_REG_EVENT_C_OFFSET, 60 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI0),
87 .mask = DA9063_M_GPI0, 61 REGMAP_IRQ_REG(DA9063_IRQ_GPI1,
88 }, 62 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI1),
89 [DA9063_IRQ_GPI1] = { 63 REGMAP_IRQ_REG(DA9063_IRQ_GPI2,
90 .reg_offset = DA9063_REG_EVENT_C_OFFSET, 64 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI2),
91 .mask = DA9063_M_GPI1, 65 REGMAP_IRQ_REG(DA9063_IRQ_GPI3,
92 }, 66 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI3),
93 [DA9063_IRQ_GPI2] = { 67 REGMAP_IRQ_REG(DA9063_IRQ_GPI4,
94 .reg_offset = DA9063_REG_EVENT_C_OFFSET, 68 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI4),
95 .mask = DA9063_M_GPI2, 69 REGMAP_IRQ_REG(DA9063_IRQ_GPI5,
96 }, 70 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI5),
97 [DA9063_IRQ_GPI3] = { 71 REGMAP_IRQ_REG(DA9063_IRQ_GPI6,
98 .reg_offset = DA9063_REG_EVENT_C_OFFSET, 72 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI6),
99 .mask = DA9063_M_GPI3, 73 REGMAP_IRQ_REG(DA9063_IRQ_GPI7,
100 }, 74 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI7),
101 [DA9063_IRQ_GPI4] = {
102 .reg_offset = DA9063_REG_EVENT_C_OFFSET,
103 .mask = DA9063_M_GPI4,
104 },
105 [DA9063_IRQ_GPI5] = {
106 .reg_offset = DA9063_REG_EVENT_C_OFFSET,
107 .mask = DA9063_M_GPI5,
108 },
109 [DA9063_IRQ_GPI6] = {
110 .reg_offset = DA9063_REG_EVENT_C_OFFSET,
111 .mask = DA9063_M_GPI6,
112 },
113 [DA9063_IRQ_GPI7] = {
114 .reg_offset = DA9063_REG_EVENT_C_OFFSET,
115 .mask = DA9063_M_GPI7,
116 },
117 /* DA9063 event D register */ 75 /* DA9063 event D register */
118 [DA9063_IRQ_GPI8] = { 76 REGMAP_IRQ_REG(DA9063_IRQ_GPI8,
119 .reg_offset = DA9063_REG_EVENT_D_OFFSET, 77 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI8),
120 .mask = DA9063_M_GPI8, 78 REGMAP_IRQ_REG(DA9063_IRQ_GPI9,
121 }, 79 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI9),
122 [DA9063_IRQ_GPI9] = { 80 REGMAP_IRQ_REG(DA9063_IRQ_GPI10,
123 .reg_offset = DA9063_REG_EVENT_D_OFFSET, 81 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI10),
124 .mask = DA9063_M_GPI9, 82 REGMAP_IRQ_REG(DA9063_IRQ_GPI11,
125 }, 83 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI11),
126 [DA9063_IRQ_GPI10] = { 84 REGMAP_IRQ_REG(DA9063_IRQ_GPI12,
127 .reg_offset = DA9063_REG_EVENT_D_OFFSET, 85 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI12),
128 .mask = DA9063_M_GPI10, 86 REGMAP_IRQ_REG(DA9063_IRQ_GPI13,
129 }, 87 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI13),
130 [DA9063_IRQ_GPI11] = { 88 REGMAP_IRQ_REG(DA9063_IRQ_GPI14,
131 .reg_offset = DA9063_REG_EVENT_D_OFFSET, 89 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI14),
132 .mask = DA9063_M_GPI11, 90 REGMAP_IRQ_REG(DA9063_IRQ_GPI15,
133 }, 91 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI15),
134 [DA9063_IRQ_GPI12] = {
135 .reg_offset = DA9063_REG_EVENT_D_OFFSET,
136 .mask = DA9063_M_GPI12,
137 },
138 [DA9063_IRQ_GPI13] = {
139 .reg_offset = DA9063_REG_EVENT_D_OFFSET,
140 .mask = DA9063_M_GPI13,
141 },
142 [DA9063_IRQ_GPI14] = {
143 .reg_offset = DA9063_REG_EVENT_D_OFFSET,
144 .mask = DA9063_M_GPI14,
145 },
146 [DA9063_IRQ_GPI15] = {
147 .reg_offset = DA9063_REG_EVENT_D_OFFSET,
148 .mask = DA9063_M_GPI15,
149 },
150}; 92};
151 93
152static const struct regmap_irq_chip da9063_irq_chip = { 94static const struct regmap_irq_chip da9063_irq_chip = {
153 .name = "da9063-irq", 95 .name = "da9063-irq",
154 .irqs = da9063_irqs, 96 .irqs = da9063_irqs,
155 .num_irqs = DA9063_NUM_IRQ, 97 .num_irqs = DA9063_NUM_IRQ,
156
157 .num_regs = 4, 98 .num_regs = 4,
158 .status_base = DA9063_REG_EVENT_A, 99 .status_base = DA9063_REG_EVENT_A,
159 .mask_base = DA9063_REG_IRQ_MASK_A, 100 .mask_base = DA9063_REG_IRQ_MASK_A,
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-15 21:54:56 -0400