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authorThierry Reding <treding@nvidia.com>2017-10-12 10:29:19 -0400
committerThierry Reding <treding@nvidia.com>2017-12-15 04:12:32 -0500
commit2a8102dfe0da7dbb61794e6b85dc7ac9271e5fc8 (patch)
tree2f0e111f2fb5f4797a8bce773f122053278c5ca2 /drivers/memory
parent02b0cc52c0c3c89641276cb1e7abddd35e036923 (diff)
memory: tegra: Create SMMU display groups
Create SMMU display groups for Tegra30, Tegra114, Tegra124 and Tegra210. This allows the display controllers on these devices to share the same IOMMU domain using the standard IOMMU group mechanism. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/memory')
-rw-r--r--drivers/memory/tegra/tegra114.c15
-rw-r--r--drivers/memory/tegra/tegra124.c17
-rw-r--r--drivers/memory/tegra/tegra210.c15
-rw-r--r--drivers/memory/tegra/tegra30.c15
4 files changed, 62 insertions, 0 deletions
diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c
index ba8fff3d66a6..b20e6e3e208e 100644
--- a/drivers/memory/tegra/tegra114.c
+++ b/drivers/memory/tegra/tegra114.c
@@ -912,11 +912,26 @@ static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
912 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, 912 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
913}; 913};
914 914
915static const unsigned int tegra114_group_display[] = {
916 TEGRA_SWGROUP_DC,
917 TEGRA_SWGROUP_DCB,
918};
919
920static const struct tegra_smmu_group_soc tegra114_groups[] = {
921 {
922 .name = "display",
923 .swgroups = tegra114_group_display,
924 .num_swgroups = ARRAY_SIZE(tegra114_group_display),
925 },
926};
927
915static const struct tegra_smmu_soc tegra114_smmu_soc = { 928static const struct tegra_smmu_soc tegra114_smmu_soc = {
916 .clients = tegra114_mc_clients, 929 .clients = tegra114_mc_clients,
917 .num_clients = ARRAY_SIZE(tegra114_mc_clients), 930 .num_clients = ARRAY_SIZE(tegra114_mc_clients),
918 .swgroups = tegra114_swgroups, 931 .swgroups = tegra114_swgroups,
919 .num_swgroups = ARRAY_SIZE(tegra114_swgroups), 932 .num_swgroups = ARRAY_SIZE(tegra114_swgroups),
933 .groups = tegra114_groups,
934 .num_groups = ARRAY_SIZE(tegra114_groups),
920 .supports_round_robin_arbitration = false, 935 .supports_round_robin_arbitration = false,
921 .supports_request_limit = false, 936 .supports_request_limit = false,
922 .num_tlb_lines = 32, 937 .num_tlb_lines = 32,
diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c
index 5a58e440f4a7..8b6360eabb8a 100644
--- a/drivers/memory/tegra/tegra124.c
+++ b/drivers/memory/tegra/tegra124.c
@@ -999,12 +999,27 @@ static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
999 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, 999 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1000}; 1000};
1001 1001
1002static const unsigned int tegra124_group_display[] = {
1003 TEGRA_SWGROUP_DC,
1004 TEGRA_SWGROUP_DCB,
1005};
1006
1007static const struct tegra_smmu_group_soc tegra124_groups[] = {
1008 {
1009 .name = "display",
1010 .swgroups = tegra124_group_display,
1011 .num_swgroups = ARRAY_SIZE(tegra124_group_display),
1012 },
1013};
1014
1002#ifdef CONFIG_ARCH_TEGRA_124_SOC 1015#ifdef CONFIG_ARCH_TEGRA_124_SOC
1003static const struct tegra_smmu_soc tegra124_smmu_soc = { 1016static const struct tegra_smmu_soc tegra124_smmu_soc = {
1004 .clients = tegra124_mc_clients, 1017 .clients = tegra124_mc_clients,
1005 .num_clients = ARRAY_SIZE(tegra124_mc_clients), 1018 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1006 .swgroups = tegra124_swgroups, 1019 .swgroups = tegra124_swgroups,
1007 .num_swgroups = ARRAY_SIZE(tegra124_swgroups), 1020 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1021 .groups = tegra124_groups,
1022 .num_groups = ARRAY_SIZE(tegra124_groups),
1008 .supports_round_robin_arbitration = true, 1023 .supports_round_robin_arbitration = true,
1009 .supports_request_limit = true, 1024 .supports_request_limit = true,
1010 .num_tlb_lines = 32, 1025 .num_tlb_lines = 32,
@@ -1029,6 +1044,8 @@ static const struct tegra_smmu_soc tegra132_smmu_soc = {
1029 .num_clients = ARRAY_SIZE(tegra124_mc_clients), 1044 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1030 .swgroups = tegra124_swgroups, 1045 .swgroups = tegra124_swgroups,
1031 .num_swgroups = ARRAY_SIZE(tegra124_swgroups), 1046 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1047 .groups = tegra124_groups,
1048 .num_groups = ARRAY_SIZE(tegra124_groups),
1032 .supports_round_robin_arbitration = true, 1049 .supports_round_robin_arbitration = true,
1033 .supports_request_limit = true, 1050 .supports_request_limit = true,
1034 .num_tlb_lines = 32, 1051 .num_tlb_lines = 32,
diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index 5e144abe4c18..d398bcd3fc57 100644
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -1059,11 +1059,26 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
1059 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 }, 1059 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
1060}; 1060};
1061 1061
1062static const unsigned int tegra210_group_display[] = {
1063 TEGRA_SWGROUP_DC,
1064 TEGRA_SWGROUP_DCB,
1065};
1066
1067static const struct tegra_smmu_group_soc tegra210_groups[] = {
1068 {
1069 .name = "display",
1070 .swgroups = tegra210_group_display,
1071 .num_swgroups = ARRAY_SIZE(tegra210_group_display),
1072 },
1073};
1074
1062static const struct tegra_smmu_soc tegra210_smmu_soc = { 1075static const struct tegra_smmu_soc tegra210_smmu_soc = {
1063 .clients = tegra210_mc_clients, 1076 .clients = tegra210_mc_clients,
1064 .num_clients = ARRAY_SIZE(tegra210_mc_clients), 1077 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1065 .swgroups = tegra210_swgroups, 1078 .swgroups = tegra210_swgroups,
1066 .num_swgroups = ARRAY_SIZE(tegra210_swgroups), 1079 .num_swgroups = ARRAY_SIZE(tegra210_swgroups),
1080 .groups = tegra210_groups,
1081 .num_groups = ARRAY_SIZE(tegra210_groups),
1067 .supports_round_robin_arbitration = true, 1082 .supports_round_robin_arbitration = true,
1068 .supports_request_limit = true, 1083 .supports_request_limit = true,
1069 .num_tlb_lines = 32, 1084 .num_tlb_lines = 32,
diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c
index b44737840e70..d756c837f23e 100644
--- a/drivers/memory/tegra/tegra30.c
+++ b/drivers/memory/tegra/tegra30.c
@@ -934,11 +934,26 @@ static const struct tegra_smmu_swgroup tegra30_swgroups[] = {
934 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 }, 934 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
935}; 935};
936 936
937static const unsigned int tegra30_group_display[] = {
938 TEGRA_SWGROUP_DC,
939 TEGRA_SWGROUP_DCB,
940};
941
942static const struct tegra_smmu_group_soc tegra30_groups[] = {
943 {
944 .name = "display",
945 .swgroups = tegra30_group_display,
946 .num_swgroups = ARRAY_SIZE(tegra30_group_display),
947 },
948};
949
937static const struct tegra_smmu_soc tegra30_smmu_soc = { 950static const struct tegra_smmu_soc tegra30_smmu_soc = {
938 .clients = tegra30_mc_clients, 951 .clients = tegra30_mc_clients,
939 .num_clients = ARRAY_SIZE(tegra30_mc_clients), 952 .num_clients = ARRAY_SIZE(tegra30_mc_clients),
940 .swgroups = tegra30_swgroups, 953 .swgroups = tegra30_swgroups,
941 .num_swgroups = ARRAY_SIZE(tegra30_swgroups), 954 .num_swgroups = ARRAY_SIZE(tegra30_swgroups),
955 .groups = tegra30_groups,
956 .num_groups = ARRAY_SIZE(tegra30_groups),
942 .supports_round_robin_arbitration = false, 957 .supports_round_robin_arbitration = false,
943 .supports_request_limit = false, 958 .supports_request_limit = false,
944 .num_tlb_lines = 16, 959 .num_tlb_lines = 16,