diff options
| author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2019-03-28 01:31:32 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2019-04-25 11:06:35 -0400 |
| commit | 4735c16b8bdd3051227ca9c617b94009e4614e21 (patch) | |
| tree | f2e631a2002ec9fb97f5c5bc5814f8711c8b7a9e /drivers/media | |
| parent | 515c45650c9bfee14bfe0597eda933abc0e878d1 (diff) | |
media: vsp1: Add support for missing 16-bit RGB444 formats
Add support for the V4L2_PIX_FMT_RGBA444, V4L2_PIX_FMT_RGBX444,
V4L2_PIX_FMT_ABGR444, V4L2_PIX_FMT_XBGR444, V4L2_PIX_FMT_BGRA444 and
V4L2_PIX_FMT_BGRX444 formats to the VSP driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Jacopo Mondi <jacopo@jmondi.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'drivers/media')
| -rw-r--r-- | drivers/media/platform/vsp1/vsp1_pipe.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c b/drivers/media/platform/vsp1/vsp1_pipe.c index 9f08d85e89d7..4332c138ee22 100644 --- a/drivers/media/platform/vsp1/vsp1_pipe.c +++ b/drivers/media/platform/vsp1/vsp1_pipe.c | |||
| @@ -42,6 +42,30 @@ static const struct vsp1_format_info vsp1_video_formats[] = { | |||
| 42 | VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | 42 | VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 43 | VI6_RPF_DSWAP_P_WDS, | 43 | VI6_RPF_DSWAP_P_WDS, |
| 44 | 1, { 16, 0, 0 }, false, false, 1, 1, false }, | 44 | 1, { 16, 0, 0 }, false, false, 1, 1, false }, |
| 45 | { V4L2_PIX_FMT_RGBA444, MEDIA_BUS_FMT_ARGB8888_1X32, | ||
| 46 | VI6_FMT_RGBA_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | ||
| 47 | VI6_RPF_DSWAP_P_WDS, | ||
| 48 | 1, { 16, 0, 0 }, false, false, 1, 1, true }, | ||
| 49 | { V4L2_PIX_FMT_RGBX444, MEDIA_BUS_FMT_ARGB8888_1X32, | ||
| 50 | VI6_FMT_RGBX_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | ||
| 51 | VI6_RPF_DSWAP_P_WDS, | ||
| 52 | 1, { 16, 0, 0 }, false, false, 1, 1, false }, | ||
| 53 | { V4L2_PIX_FMT_ABGR444, MEDIA_BUS_FMT_ARGB8888_1X32, | ||
| 54 | VI6_FMT_ABGR_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | ||
| 55 | VI6_RPF_DSWAP_P_WDS, | ||
| 56 | 1, { 16, 0, 0 }, false, false, 1, 1, true }, | ||
| 57 | { V4L2_PIX_FMT_XBGR444, MEDIA_BUS_FMT_ARGB8888_1X32, | ||
| 58 | VI6_FMT_ABGR_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | ||
| 59 | VI6_RPF_DSWAP_P_WDS, | ||
| 60 | 1, { 16, 0, 0 }, false, false, 1, 1, false }, | ||
| 61 | { V4L2_PIX_FMT_BGRA444, MEDIA_BUS_FMT_ARGB8888_1X32, | ||
| 62 | VI6_FMT_BGRA_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | ||
| 63 | VI6_RPF_DSWAP_P_WDS, | ||
| 64 | 1, { 16, 0, 0 }, false, false, 1, 1, true }, | ||
| 65 | { V4L2_PIX_FMT_BGRX444, MEDIA_BUS_FMT_ARGB8888_1X32, | ||
| 66 | VI6_FMT_BGRA_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | ||
| 67 | VI6_RPF_DSWAP_P_WDS, | ||
| 68 | 1, { 16, 0, 0 }, false, false, 1, 1, false }, | ||
| 45 | { V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32, | 69 | { V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32, |
| 46 | VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | 70 | VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 47 | VI6_RPF_DSWAP_P_WDS, | 71 | VI6_RPF_DSWAP_P_WDS, |