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authorSteve Lin <steven.lin1@broadcom.com>2017-02-23 09:49:50 -0500
committerJassi Brar <jaswinder.singh@linaro.org>2017-03-28 13:57:56 -0400
commitfc2041c5415fbbe8a7f1f6ce73a5d4ad186c7827 (patch)
tree38d0becb9bc1edcbdf67967eb61e07e09be43a3e /drivers/mailbox/bcm-pdc-mailbox.c
parent8ce33c6ff375b59bfa0a347782c49da94e64bb85 (diff)
mailbox: bcm-pdc: Add Northstar Plus support to PDC driver
Adds support for Northstar Plus (NS+) products to the PDC mailbox driver. The PDC driver was originally written to support the PDC ring manager in the Northstar2 (64-bit) device. The NS+ (32 bit device) uses an almost identical ring manager, though with a different name. We just need to check for the type of hardware in use, in order to write the appropriate interrupt configuration register. Also updated DMA width to be correct for both NS+ and NS2. Tested on NS+ and NS2. Signed-off-by: Steve Lin <steven.lin1@broadcom.com> Acked-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Diffstat (limited to 'drivers/mailbox/bcm-pdc-mailbox.c')
-rw-r--r--drivers/mailbox/bcm-pdc-mailbox.c61
1 files changed, 46 insertions, 15 deletions
diff --git a/drivers/mailbox/bcm-pdc-mailbox.c b/drivers/mailbox/bcm-pdc-mailbox.c
index 2aeb034d5fb9..4fe7be0bdd11 100644
--- a/drivers/mailbox/bcm-pdc-mailbox.c
+++ b/drivers/mailbox/bcm-pdc-mailbox.c
@@ -18,7 +18,8 @@
18 * Broadcom PDC Mailbox Driver 18 * Broadcom PDC Mailbox Driver
19 * The PDC provides a ring based programming interface to one or more hardware 19 * The PDC provides a ring based programming interface to one or more hardware
20 * offload engines. For example, the PDC driver works with both SPU-M and SPU2 20 * offload engines. For example, the PDC driver works with both SPU-M and SPU2
21 * cryptographic offload hardware. In some chips the PDC is referred to as MDE. 21 * cryptographic offload hardware. In some chips the PDC is referred to as MDE,
22 * and in others the FA2/FA+ hardware is used with this PDC driver.
22 * 23 *
23 * The PDC driver registers with the Linux mailbox framework as a mailbox 24 * The PDC driver registers with the Linux mailbox framework as a mailbox
24 * controller, once for each PDC instance. Ring 0 for each PDC is registered as 25 * controller, once for each PDC instance. Ring 0 for each PDC is registered as
@@ -108,6 +109,7 @@
108#define PDC_INTMASK_OFFSET 0x24 109#define PDC_INTMASK_OFFSET 0x24
109#define PDC_INTSTATUS_OFFSET 0x20 110#define PDC_INTSTATUS_OFFSET 0x20
110#define PDC_RCVLAZY0_OFFSET (0x30 + 4 * PDC_RINGSET) 111#define PDC_RCVLAZY0_OFFSET (0x30 + 4 * PDC_RINGSET)
112#define FA_RCVLAZY0_OFFSET 0x100
111 113
112/* 114/*
113 * For SPU2, configure MDE_CKSUM_CONTROL to write 17 bytes of metadata 115 * For SPU2, configure MDE_CKSUM_CONTROL to write 17 bytes of metadata
@@ -162,6 +164,11 @@
162/* Maximum size buffer the DMA engine can handle */ 164/* Maximum size buffer the DMA engine can handle */
163#define PDC_DMA_BUF_MAX 16384 165#define PDC_DMA_BUF_MAX 16384
164 166
167enum pdc_hw {
168 FA_HW, /* FA2/FA+ hardware (i.e. Northstar Plus) */
169 PDC_HW /* PDC/MDE hardware (i.e. Northstar 2, Pegasus) */
170};
171
165struct pdc_dma_map { 172struct pdc_dma_map {
166 void *ctx; /* opaque context associated with frame */ 173 void *ctx; /* opaque context associated with frame */
167}; 174};
@@ -211,13 +218,13 @@ struct pdc_regs {
211 u32 gptimer; /* 0x028 */ 218 u32 gptimer; /* 0x028 */
212 219
213 u32 PAD; 220 u32 PAD;
214 u32 intrcvlazy_0; /* 0x030 */ 221 u32 intrcvlazy_0; /* 0x030 (Only in PDC, not FA2) */
215 u32 intrcvlazy_1; /* 0x034 */ 222 u32 intrcvlazy_1; /* 0x034 (Only in PDC, not FA2) */
216 u32 intrcvlazy_2; /* 0x038 */ 223 u32 intrcvlazy_2; /* 0x038 (Only in PDC, not FA2) */
217 u32 intrcvlazy_3; /* 0x03c */ 224 u32 intrcvlazy_3; /* 0x03c (Only in PDC, not FA2) */
218 225
219 u32 PAD[48]; 226 u32 PAD[48];
220 u32 removed_intrecvlazy; /* 0x100 */ 227 u32 fa_intrecvlazy; /* 0x100 (Only in FA2, not PDC) */
221 u32 flowctlthresh; /* 0x104 */ 228 u32 flowctlthresh; /* 0x104 */
222 u32 wrrthresh; /* 0x108 */ 229 u32 wrrthresh; /* 0x108 */
223 u32 gmac_idle_cnt_thresh; /* 0x10c */ 230 u32 gmac_idle_cnt_thresh; /* 0x10c */
@@ -243,7 +250,7 @@ struct pdc_regs {
243 u32 serdes_status1; /* 0x1b0 */ 250 u32 serdes_status1; /* 0x1b0 */
244 u32 PAD[11]; /* 0x1b4-1dc */ 251 u32 PAD[11]; /* 0x1b4-1dc */
245 u32 clk_ctl_st; /* 0x1e0 */ 252 u32 clk_ctl_st; /* 0x1e0 */
246 u32 hw_war; /* 0x1e4 */ 253 u32 hw_war; /* 0x1e4 (Only in PDC, not FA2) */
247 u32 pwrctl; /* 0x1e8 */ 254 u32 pwrctl; /* 0x1e8 */
248 u32 PAD[5]; 255 u32 PAD[5];
249 256
@@ -410,6 +417,9 @@ struct pdc_state {
410 u32 txnobuf; /* unable to create tx descriptor */ 417 u32 txnobuf; /* unable to create tx descriptor */
411 u32 rxnobuf; /* unable to create rx descriptor */ 418 u32 rxnobuf; /* unable to create rx descriptor */
412 u32 rx_oflow; /* count of rx overflows */ 419 u32 rx_oflow; /* count of rx overflows */
420
421 /* hardware type - FA2 or PDC/MDE */
422 enum pdc_hw hw_type;
413}; 423};
414 424
415/* Global variables */ 425/* Global variables */
@@ -1396,7 +1406,13 @@ static int pdc_interrupts_init(struct pdc_state *pdcs)
1396 1406
1397 /* interrupt configuration */ 1407 /* interrupt configuration */
1398 iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET); 1408 iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET);
1399 iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase + PDC_RCVLAZY0_OFFSET); 1409
1410 if (pdcs->hw_type == FA_HW)
1411 iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase +
1412 FA_RCVLAZY0_OFFSET);
1413 else
1414 iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase +
1415 PDC_RCVLAZY0_OFFSET);
1400 1416
1401 /* read irq from device tree */ 1417 /* read irq from device tree */
1402 pdcs->pdc_irq = irq_of_parse_and_map(dn, 0); 1418 pdcs->pdc_irq = irq_of_parse_and_map(dn, 0);
@@ -1465,6 +1481,17 @@ static int pdc_mb_init(struct pdc_state *pdcs)
1465 return 0; 1481 return 0;
1466} 1482}
1467 1483
1484/* Device tree API */
1485static const int pdc_hw = PDC_HW;
1486static const int fa_hw = FA_HW;
1487
1488static const struct of_device_id pdc_mbox_of_match[] = {
1489 {.compatible = "brcm,iproc-pdc-mbox", .data = &pdc_hw},
1490 {.compatible = "brcm,iproc-fa2-mbox", .data = &fa_hw},
1491 { /* sentinel */ }
1492};
1493MODULE_DEVICE_TABLE(of, pdc_mbox_of_match);
1494
1468/** 1495/**
1469 * pdc_dt_read() - Read application-specific data from device tree. 1496 * pdc_dt_read() - Read application-specific data from device tree.
1470 * @pdev: Platform device 1497 * @pdev: Platform device
@@ -1481,6 +1508,8 @@ static int pdc_dt_read(struct platform_device *pdev, struct pdc_state *pdcs)
1481{ 1508{
1482 struct device *dev = &pdev->dev; 1509 struct device *dev = &pdev->dev;
1483 struct device_node *dn = pdev->dev.of_node; 1510 struct device_node *dn = pdev->dev.of_node;
1511 const struct of_device_id *match;
1512 const int *hw_type;
1484 int err; 1513 int err;
1485 1514
1486 err = of_property_read_u32(dn, "brcm,rx-status-len", 1515 err = of_property_read_u32(dn, "brcm,rx-status-len",
@@ -1492,6 +1521,14 @@ static int pdc_dt_read(struct platform_device *pdev, struct pdc_state *pdcs)
1492 1521
1493 pdcs->use_bcm_hdr = of_property_read_bool(dn, "brcm,use-bcm-hdr"); 1522 pdcs->use_bcm_hdr = of_property_read_bool(dn, "brcm,use-bcm-hdr");
1494 1523
1524 pdcs->hw_type = PDC_HW;
1525
1526 match = of_match_device(of_match_ptr(pdc_mbox_of_match), dev);
1527 if (match != NULL) {
1528 hw_type = match->data;
1529 pdcs->hw_type = *hw_type;
1530 }
1531
1495 return 0; 1532 return 0;
1496} 1533}
1497 1534
@@ -1525,7 +1562,7 @@ static int pdc_probe(struct platform_device *pdev)
1525 pdcs->pdc_idx = pdcg.num_spu; 1562 pdcs->pdc_idx = pdcg.num_spu;
1526 pdcg.num_spu++; 1563 pdcg.num_spu++;
1527 1564
1528 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 1565 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(39));
1529 if (err) { 1566 if (err) {
1530 dev_warn(dev, "PDC device cannot perform DMA. Error %d.", err); 1567 dev_warn(dev, "PDC device cannot perform DMA. Error %d.", err);
1531 goto cleanup; 1568 goto cleanup;
@@ -1611,12 +1648,6 @@ static int pdc_remove(struct platform_device *pdev)
1611 return 0; 1648 return 0;
1612} 1649}
1613 1650
1614static const struct of_device_id pdc_mbox_of_match[] = {
1615 {.compatible = "brcm,iproc-pdc-mbox"},
1616 { /* sentinel */ }
1617};
1618MODULE_DEVICE_TABLE(of, pdc_mbox_of_match);
1619
1620static struct platform_driver pdc_mbox_driver = { 1651static struct platform_driver pdc_mbox_driver = {
1621 .probe = pdc_probe, 1652 .probe = pdc_probe,
1622 .remove = pdc_remove, 1653 .remove = pdc_remove,