diff options
author | Julien Grall <julien.grall@arm.com> | 2019-05-01 09:58:23 -0400 |
---|---|---|
committer | Marc Zyngier <marc.zyngier@arm.com> | 2019-05-03 10:30:03 -0400 |
commit | 73103975425786ebdb6c4d2868ecf26f391fb77e (patch) | |
tree | 38988ca2b22ef18a68ce28d56e2ee288b978d43e /drivers/irqchip | |
parent | 2cb3b16545495ee31dc9438f88232c2cfe44a41f (diff) |
irqchip/gic-v3-mbi: Don't map the MSI page in mbi_compose_m{b, s}i_msg()
The functions mbi_compose_m{b, s}i_msg may be called from non-preemptible
context. However, on RT, iommu_dma_map_msi_msg() requires to be called
from a preemptible context.
A recent patch split iommu_dma_map_msi_msg in two new functions:
one that should be called in preemptible context, the other does
not have any requirement.
The GICv3 MSI driver is reworked to avoid executing preemptible code in
non-preemptible context. This can be achieved by preparing the MSI
mapping when allocating the MSI interrupt.
Signed-off-by: Julien Grall <julien.grall@arm.com>
[maz: only call iommu_dma_prepare_msi once, fix commit log accordingly]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/irqchip')
-rw-r--r-- | drivers/irqchip/irq-gic-v3-mbi.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/irqchip/irq-gic-v3-mbi.c b/drivers/irqchip/irq-gic-v3-mbi.c index fbfa7ff6deb1..563a9b366294 100644 --- a/drivers/irqchip/irq-gic-v3-mbi.c +++ b/drivers/irqchip/irq-gic-v3-mbi.c | |||
@@ -84,6 +84,7 @@ static void mbi_free_msi(struct mbi_range *mbi, unsigned int hwirq, | |||
84 | static int mbi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | 84 | static int mbi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
85 | unsigned int nr_irqs, void *args) | 85 | unsigned int nr_irqs, void *args) |
86 | { | 86 | { |
87 | msi_alloc_info_t *info = args; | ||
87 | struct mbi_range *mbi = NULL; | 88 | struct mbi_range *mbi = NULL; |
88 | int hwirq, offset, i, err = 0; | 89 | int hwirq, offset, i, err = 0; |
89 | 90 | ||
@@ -104,6 +105,11 @@ static int mbi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |||
104 | 105 | ||
105 | hwirq = mbi->spi_start + offset; | 106 | hwirq = mbi->spi_start + offset; |
106 | 107 | ||
108 | err = iommu_dma_prepare_msi(info->desc, | ||
109 | mbi_phys_base + GICD_SETSPI_NSR); | ||
110 | if (err) | ||
111 | return err; | ||
112 | |||
107 | for (i = 0; i < nr_irqs; i++) { | 113 | for (i = 0; i < nr_irqs; i++) { |
108 | err = mbi_irq_gic_domain_alloc(domain, virq + i, hwirq + i); | 114 | err = mbi_irq_gic_domain_alloc(domain, virq + i, hwirq + i); |
109 | if (err) | 115 | if (err) |
@@ -142,7 +148,7 @@ static void mbi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) | |||
142 | msg[0].address_lo = lower_32_bits(mbi_phys_base + GICD_SETSPI_NSR); | 148 | msg[0].address_lo = lower_32_bits(mbi_phys_base + GICD_SETSPI_NSR); |
143 | msg[0].data = data->parent_data->hwirq; | 149 | msg[0].data = data->parent_data->hwirq; |
144 | 150 | ||
145 | iommu_dma_map_msi_msg(data->irq, msg); | 151 | iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg); |
146 | } | 152 | } |
147 | 153 | ||
148 | #ifdef CONFIG_PCI_MSI | 154 | #ifdef CONFIG_PCI_MSI |
@@ -202,7 +208,7 @@ static void mbi_compose_mbi_msg(struct irq_data *data, struct msi_msg *msg) | |||
202 | msg[1].address_lo = lower_32_bits(mbi_phys_base + GICD_CLRSPI_NSR); | 208 | msg[1].address_lo = lower_32_bits(mbi_phys_base + GICD_CLRSPI_NSR); |
203 | msg[1].data = data->parent_data->hwirq; | 209 | msg[1].data = data->parent_data->hwirq; |
204 | 210 | ||
205 | iommu_dma_map_msi_msg(data->irq, &msg[1]); | 211 | iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), &msg[1]); |
206 | } | 212 | } |
207 | 213 | ||
208 | /* Platform-MSI specific irqchip */ | 214 | /* Platform-MSI specific irqchip */ |