Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq updates from Thomas Gleixner:
 "The irq department provides:

   - Support for MSI to wire bridges and a first user of it

   - More ACPI support for ARM/GIC

   - A new TS-4800 interrupt controller driver

   - RCU based free of interrupt descriptors to support the upcoming
     Intel VMD technology without introducing a locking nightmare

   - The usual pile of fixes and updates to drivers and core code"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (41 commits)
  irqchip/omap-intc: Add support for spurious irq handling
  irqchip/zevio: Use irq_data_get_chip_type() helper
  irqchip/omap-intc: Remove duplicate setup for IRQ chip type handler
  irqchip/ts4800: Add TS-4800 interrupt controller
  irqchip/ts4800: Add documentation for TS-4800 interrupt controller
  irq/platform-MSI: Increase the maximum MSIs the MSI framework can support
  irqchip/gicv2m: Miscellaneous fixes for v2m resources and SPI ranges
  irqchip/bcm2836: Make code more readable
  irqchip/bcm2836: Tolerate IRQs while no flag is set in ISR
  irqchip/bcm2836: Add SMP support for the 2836
  irqchip/bcm2836: Fix initialization of the LOCAL_IRQ_CNT timers
  irqchip/gic-v2m: acpi: Introducing GICv2m ACPI support
  irqchip/gic-v2m: Refactor to prepare for ACPI support
  irqdomain: Introduce is_fwnode_irqchip helper
  acpi: pci: Setup MSI domain for ACPI based pci devices
  genirq/msi: Export functions to allow MSI domains in modules
  irqchip/mbigen: Implement the mbigen irq chip operation functions
  irqchip/mbigen: Create irq domain for each mbigen device
  irqchip/mgigen: Add platform device driver for mbigen device
  dt-bindings: Documents the mbigen bindings
  ...

12 files changed, 840 insertions, 109 deletions

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e5d982..11fc2a27fa2e 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -8,6 +8,11 @@ config ARM_GIC
         select IRQ_DOMAIN_HIERARCHY
         select MULTI_IRQ_HANDLER
 
+config ARM_GIC_MAX_NR
+        int
+        default 2 if ARCH_REALVIEW
+        default 1
+
 config ARM_GIC_V2M
         bool
         depends on ARM_GIC
@@ -27,6 +32,14 @@ config ARM_GIC_V3_ITS
         bool
         select PCI_MSI_IRQ_DOMAIN
 
+config HISILICON_IRQ_MBIGEN
+        bool "Support mbigen interrupt controller"
+        default n
+        depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN
+        help
+         Enable the mbigen interrupt controller used on
+         Hisilicon platform.
+
 config ARM_NVIC
         bool
         select IRQ_DOMAIN
@@ -138,6 +151,12 @@ config TB10X_IRQC
         select IRQ_DOMAIN
         select GENERIC_IRQ_CHIP
 
+config TS4800_IRQ
+        tristate "TS-4800 IRQ controller"
+        select IRQ_DOMAIN
+        help
+          Support for the TS-4800 FPGA IRQ controller
+
 config VERSATILE_FPGA_IRQ
         bool
         select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f6e6d6..d4c2e4ebc308 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -21,9 +21,11 @@ obj-$(CONFIG_ARCH_SUNXI)		+= irq-sun4i.o
 obj-$(CONFIG_ARCH_SUNXI)                += irq-sunxi-nmi.o
 obj-$(CONFIG_ARCH_SPEAR3XX)             += spear-shirq.o
 obj-$(CONFIG_ARM_GIC)                   += irq-gic.o irq-gic-common.o
+obj-$(CONFIG_REALVIEW_DT)               += irq-gic-realview.o
 obj-$(CONFIG_ARM_GIC_V2M)               += irq-gic-v2m.o
 obj-$(CONFIG_ARM_GIC_V3)                += irq-gic-v3.o irq-gic-common.o
 obj-$(CONFIG_ARM_GIC_V3_ITS)            += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o
+obj-$(CONFIG_HISILICON_IRQ_MBIGEN)      += irq-mbigen.o
 obj-$(CONFIG_ARM_NVIC)                  += irq-nvic.o
 obj-$(CONFIG_ARM_VIC)                   += irq-vic.o
 obj-$(CONFIG_ATMEL_AIC_IRQ)             += irq-atmel-aic-common.o irq-atmel-aic.o
@@ -39,6 +41,7 @@ obj-$(CONFIG_ARCH_NSPIRE)		+= irq-zevio.o
 obj-$(CONFIG_ARCH_VT8500)               += irq-vt8500.o
 obj-$(CONFIG_ST_IRQCHIP)                += irq-st.o
 obj-$(CONFIG_TB10X_IRQC)                += irq-tb10x.o
+obj-$(CONFIG_TS4800_IRQ)                += irq-ts4800.o
 obj-$(CONFIG_XTENSA)                    += irq-xtensa-pic.o
 obj-$(CONFIG_XTENSA_MX)                 += irq-xtensa-mx.o
 obj-$(CONFIG_IRQ_CROSSBAR)              += irq-crossbar.o
diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c
index f68708281fcf..963065a0d774 100644
--- a/drivers/irqchip/irq-bcm2836.c
+++ b/drivers/irqchip/irq-bcm2836.c
@@ -21,6 +21,9 @@
 #include <linux/irqdomain.h>
 #include <asm/exception.h>
 
+#define LOCAL_CONTROL                   0x000
+#define LOCAL_PRESCALER                 0x008
+
 /*
  * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
  * next 2 bits identify the CPU that the GPU FIQ goes to.
@@ -50,14 +53,16 @@
 /* Same status bits as above, but for FIQ. */
 #define LOCAL_FIQ_PENDING0              0x070
 /*
- * Mailbox0 write-to-set bits.  There are 16 mailboxes, 4 per CPU, and
+ * Mailbox write-to-set bits.  There are 16 mailboxes, 4 per CPU, and
  * these bits are organized by mailbox number and then CPU number.  We
  * use mailbox 0 for IPIs.  The mailbox's interrupt is raised while
  * any bit is set.
  */
 #define LOCAL_MAILBOX0_SET0             0x080
-/* Mailbox0 write-to-clear bits. */
+#define LOCAL_MAILBOX3_SET0             0x08c
+/* Mailbox write-to-clear bits. */
 #define LOCAL_MAILBOX0_CLR0             0x0c0
+#define LOCAL_MAILBOX3_CLR0             0x0cc
 
 #define LOCAL_IRQ_CNTPSIRQ      0
 #define LOCAL_IRQ_CNTPNSIRQ     1
@@ -162,7 +167,7 @@ __exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
         u32 stat;
 
         stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
-        if (stat & 0x10) {
+        if (stat & BIT(LOCAL_IRQ_MAILBOX0)) {
 #ifdef CONFIG_SMP
                 void __iomem *mailbox0 = (intc.base +
                                           LOCAL_MAILBOX0_CLR0 + 16 * cpu);
@@ -172,7 +177,7 @@ __exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
                 writel(1 << ipi, mailbox0);
                 handle_IPI(ipi, regs);
 #endif
-        } else {
+        } else if (stat) {
                 u32 hwirq = ffs(stat) - 1;
 
                 handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs);
@@ -217,6 +222,24 @@ static struct notifier_block bcm2836_arm_irqchip_cpu_notifier = {
         .notifier_call = bcm2836_arm_irqchip_cpu_notify,
         .priority = 100,
 };
+
+int __init bcm2836_smp_boot_secondary(unsigned int cpu,
+                                      struct task_struct *idle)
+{
+        unsigned long secondary_startup_phys =
+                (unsigned long)virt_to_phys((void *)secondary_startup);
+
+        dsb();
+        writel(secondary_startup_phys,
+               intc.base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
+
+        return 0;
+}
+
+static const struct smp_operations bcm2836_smp_ops __initconst = {
+        .smp_boot_secondary     = bcm2836_smp_boot_secondary,
+};
+
 #endif
 
 static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
@@ -234,9 +257,31 @@ bcm2836_arm_irqchip_smp_init(void)
         register_cpu_notifier(&bcm2836_arm_irqchip_cpu_notifier);
 
         set_smp_cross_call(bcm2836_arm_irqchip_send_ipi);
+        smp_set_ops(&bcm2836_smp_ops);
 #endif
 }
 
+/*
+ * The LOCAL_IRQ_CNT* timer firings are based off of the external
+ * oscillator with some scaling.  The firmware sets up CNTFRQ to
+ * report 19.2Mhz, but doesn't set up the scaling registers.
+ */
+static void bcm2835_init_local_timer_frequency(void)
+{
+        /*
+         * Set the timer to source from the 19.2Mhz crystal clock (bit
+         * 8 unset), and only increment by 1 instead of 2 (bit 9
+         * unset).
+         */
+        writel(0, intc.base + LOCAL_CONTROL);
+
+        /*
+         * Set the timer prescaler to 1:1 (timer freq = input freq *
+         * 2**31 / prescaler)
+         */
+        writel(0x80000000, intc.base + LOCAL_PRESCALER);
+}
+
 static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
                                                       struct device_node *parent)
 {
@@ -246,6 +291,8 @@ static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
                         node->full_name);
         }
 
+        bcm2835_init_local_timer_frequency();
+
         intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
                                             &bcm2836_arm_irqchip_intc_ops,
                                             NULL);
diff --git a/drivers/irqchip/irq-gic-realview.c b/drivers/irqchip/irq-gic-realview.c
new file mode 100644
index 000000000000..aa46eb280a7f
--- /dev/null
+++ b/drivers/irqchip/irq-gic-realview.c
@@ -0,0 +1,43 @@
+/*
+ * Special GIC quirks for the ARM RealView
+ * Copyright (C) 2015 Linus Walleij
+ */
+#include <linux/of.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/bitops.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-gic.h>
+
+#define REALVIEW_SYS_LOCK_OFFSET        0x20
+#define REALVIEW_PB11MP_SYS_PLD_CTRL1   0x74
+#define VERSATILE_LOCK_VAL              0xA05F
+#define PLD_INTMODE_MASK                BIT(22)|BIT(23)|BIT(24)
+#define PLD_INTMODE_LEGACY              0x0
+#define PLD_INTMODE_NEW_DCC             BIT(22)
+#define PLD_INTMODE_NEW_NO_DCC          BIT(23)
+#define PLD_INTMODE_FIQ_ENABLE          BIT(24)
+
+static int __init
+realview_gic_of_init(struct device_node *node, struct device_node *parent)
+{
+        static struct regmap *map;
+
+        /* The PB11MPCore GIC needs to be configured in the syscon */
+        map = syscon_regmap_lookup_by_compatible("arm,realview-pb11mp-syscon");
+        if (!IS_ERR(map)) {
+                /* new irq mode with no DCC */
+                regmap_write(map, REALVIEW_SYS_LOCK_OFFSET,
+                             VERSATILE_LOCK_VAL);
+                regmap_update_bits(map, REALVIEW_PB11MP_SYS_PLD_CTRL1,
+                                   PLD_INTMODE_NEW_NO_DCC,
+                                   PLD_INTMODE_MASK);
+                regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, 0x0000);
+                pr_info("TC11MP GIC: set up interrupt controller to NEW mode, no DCC\n");
+        } else {
+                pr_err("TC11MP GIC setup: could not find syscon\n");
+                return -ENXIO;
+        }
+        return gic_of_init(node, parent);
+}
+IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init);
diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c
index 87f8d104acab..c779f83e511d 100644
--- a/drivers/irqchip/irq-gic-v2m.c
+++ b/drivers/irqchip/irq-gic-v2m.c
@@ -15,9 +15,11 @@
 
 #define pr_fmt(fmt) "GICv2m: " fmt
 
+#include <linux/acpi.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
 #include <linux/kernel.h>
+#include <linux/msi.h>
 #include <linux/of_address.h>
 #include <linux/of_pci.h>
 #include <linux/slab.h>
@@ -55,7 +57,7 @@ static DEFINE_SPINLOCK(v2m_lock);
 
 struct v2m_data {
         struct list_head entry;
-        struct device_node *node;
+        struct fwnode_handle *fwnode;
         struct resource res;    /* GICv2m resource */
         void __iomem *base;     /* GICv2m virt address */
         u32 spi_start;          /* The SPI number that MSIs start */
@@ -138,6 +140,11 @@ static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
                 fwspec.param[0] = 0;
                 fwspec.param[1] = hwirq - 32;
                 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
+        } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
+                fwspec.fwnode = domain->parent->fwnode;
+                fwspec.param_count = 2;
+                fwspec.param[0] = hwirq;
+                fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
         } else {
                 return -EINVAL;
         }
@@ -254,7 +261,9 @@ static void gicv2m_teardown(void)
                 list_del(&v2m->entry);
                 kfree(v2m->bm);
                 iounmap(v2m->base);
-                of_node_put(v2m->node);
+                of_node_put(to_of_node(v2m->fwnode));
+                if (is_fwnode_irqchip(v2m->fwnode))
+                        irq_domain_free_fwnode(v2m->fwnode);
                 kfree(v2m);
         }
 }
@@ -268,7 +277,7 @@ static int gicv2m_allocate_domains(struct irq_domain *parent)
         if (!v2m)
                 return 0;
 
-        inner_domain = irq_domain_create_tree(of_node_to_fwnode(v2m->node),
+        inner_domain = irq_domain_create_tree(v2m->fwnode,
                                               &gicv2m_domain_ops, v2m);
         if (!inner_domain) {
                 pr_err("Failed to create GICv2m domain\n");
@@ -277,10 +286,10 @@ static int gicv2m_allocate_domains(struct irq_domain *parent)
 
         inner_domain->bus_token = DOMAIN_BUS_NEXUS;
         inner_domain->parent = parent;
-        pci_domain = pci_msi_create_irq_domain(of_node_to_fwnode(v2m->node),
+        pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
                                                &gicv2m_msi_domain_info,
                                                inner_domain);
-        plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(v2m->node),
+        plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
                                                      &gicv2m_pmsi_domain_info,
                                                      inner_domain);
         if (!pci_domain || !plat_domain) {
@@ -296,8 +305,9 @@ static int gicv2m_allocate_domains(struct irq_domain *parent)
         return 0;
 }
 
-static int __init gicv2m_init_one(struct device_node *node,
-                                  struct irq_domain *parent)
+static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
+                                  u32 spi_start, u32 nr_spis,
+                                  struct resource *res)
 {
         int ret;
         struct v2m_data *v2m;
@@ -309,13 +319,9 @@ static int __init gicv2m_init_one(struct device_node *node,
         }
 
         INIT_LIST_HEAD(&v2m->entry);
-        v2m->node = node;
+        v2m->fwnode = fwnode;
 
-        ret = of_address_to_resource(node, 0, &v2m->res);
-        if (ret) {
-                pr_err("Failed to allocate v2m resource.\n");
-                goto err_free_v2m;
-        }
+        memcpy(&v2m->res, res, sizeof(struct resource));
 
         v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
         if (!v2m->base) {
@@ -324,10 +330,9 @@ static int __init gicv2m_init_one(struct device_node *node,
                 goto err_free_v2m;
         }
 
-        if (!of_property_read_u32(node, "arm,msi-base-spi", &v2m->spi_start) &&
-            !of_property_read_u32(node, "arm,msi-num-spis", &v2m->nr_spis)) {
-                pr_info("Overriding V2M MSI_TYPER (base:%u, num:%u)\n",
-                        v2m->spi_start, v2m->nr_spis);
+        if (spi_start && nr_spis) {
+                v2m->spi_start = spi_start;
+                v2m->nr_spis = nr_spis;
         } else {
                 u32 typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
 
@@ -359,10 +364,9 @@ static int __init gicv2m_init_one(struct device_node *node,
         }
 
         list_add_tail(&v2m->entry, &v2m_nodes);
-        pr_info("Node %s: range[%#lx:%#lx], SPI[%d:%d]\n", node->name,
-                (unsigned long)v2m->res.start, (unsigned long)v2m->res.end,
-                v2m->spi_start, (v2m->spi_start + v2m->nr_spis));
 
+        pr_info("range%pR, SPI[%d:%d]\n", res,
+                v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
         return 0;
 
 err_iounmap:
@@ -377,19 +381,36 @@ static struct of_device_id gicv2m_device_id[] = {
         {},
 };
 
-int __init gicv2m_of_init(struct device_node *node, struct irq_domain *parent)
+static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
+                                 struct irq_domain *parent)
 {
         int ret = 0;
+        struct device_node *node = to_of_node(parent_handle);
         struct device_node *child;
 
         for (child = of_find_matching_node(node, gicv2m_device_id); child;
              child = of_find_matching_node(child, gicv2m_device_id)) {
+                u32 spi_start = 0, nr_spis = 0;
+                struct resource res;
+
                 if (!of_find_property(child, "msi-controller", NULL))
                         continue;
 
-                ret = gicv2m_init_one(child, parent);
+                ret = of_address_to_resource(child, 0, &res);
+                if (ret) {
+                        pr_err("Failed to allocate v2m resource.\n");
+                        break;
+                }
+
+                if (!of_property_read_u32(child, "arm,msi-base-spi",
+                                          &spi_start) &&
+                    !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
+                        pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
+                                spi_start, nr_spis);
+
+                ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, &res);
                 if (ret) {
-                        of_node_put(node);
+                        of_node_put(child);
                         break;
                 }
         }
@@ -400,3 +421,101 @@ int __init gicv2m_of_init(struct device_node *node, struct irq_domain *parent)
                 gicv2m_teardown();
         return ret;
 }
+
+#ifdef CONFIG_ACPI
+static int acpi_num_msi;
+
+static struct fwnode_handle *gicv2m_get_fwnode(struct device *dev)
+{
+        struct v2m_data *data;
+
+        if (WARN_ON(acpi_num_msi <= 0))
+                return NULL;
+
+        /* We only return the fwnode of the first MSI frame. */
+        data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
+        if (!data)
+                return NULL;
+
+        return data->fwnode;
+}
+
+static int __init
+acpi_parse_madt_msi(struct acpi_subtable_header *header,
+                    const unsigned long end)
+{
+        int ret;
+        struct resource res;
+        u32 spi_start = 0, nr_spis = 0;
+        struct acpi_madt_generic_msi_frame *m;
+        struct fwnode_handle *fwnode;
+
+        m = (struct acpi_madt_generic_msi_frame *)header;
+        if (BAD_MADT_ENTRY(m, end))
+                return -EINVAL;
+
+        res.start = m->base_address;
+        res.end = m->base_address + SZ_4K - 1;
+        res.flags = IORESOURCE_MEM;
+
+        if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
+                spi_start = m->spi_base;
+                nr_spis = m->spi_count;
+
+                pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
+                        spi_start, nr_spis);
+        }
+
+        fwnode = irq_domain_alloc_fwnode((void *)m->base_address);
+        if (!fwnode) {
+                pr_err("Unable to allocate GICv2m domain token\n");
+                return -EINVAL;
+        }
+
+        ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res);
+        if (ret)
+                irq_domain_free_fwnode(fwnode);
+
+        return ret;
+}
+
+static int __init gicv2m_acpi_init(struct irq_domain *parent)
+{
+        int ret;
+
+        if (acpi_num_msi > 0)
+                return 0;
+
+        acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
+                                      acpi_parse_madt_msi, 0);
+
+        if (acpi_num_msi <= 0)
+                goto err_out;
+
+        ret = gicv2m_allocate_domains(parent);
+        if (ret)
+                goto err_out;
+
+        pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);
+
+        return 0;
+
+err_out:
+        gicv2m_teardown();
+        return -EINVAL;
+}
+#else /* CONFIG_ACPI */
+static int __init gicv2m_acpi_init(struct irq_domain *parent)
+{
+        return -EINVAL;
+}
+#endif /* CONFIG_ACPI */
+
+int __init gicv2m_init(struct fwnode_handle *parent_handle,
+                       struct irq_domain *parent)
+{
+        if (is_of_node(parent_handle))
+                return gicv2m_of_init(parent_handle, parent);
+
+        return gicv2m_acpi_init(parent);
+}
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index abf2ffaed392..911758c056c1 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -69,6 +69,7 @@ union gic_base {
 };
 
 struct gic_chip_data {
+        struct irq_chip chip;
         union gic_base dist_base;
         union gic_base cpu_base;
 #ifdef CONFIG_CPU_PM
@@ -99,11 +100,7 @@ static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
 
 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
 
-#ifndef MAX_GIC_NR
-#define MAX_GIC_NR      1
-#endif
-
-static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
+static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
 
 #ifdef CONFIG_GIC_NON_BANKED
 static void __iomem *gic_get_percpu_base(union gic_base *base)
@@ -336,7 +333,7 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
                 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
                 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
 
-                if (likely(irqnr > 15 && irqnr < 1021)) {
+                if (likely(irqnr > 15 && irqnr < 1020)) {
                         if (static_key_true(&supports_deactivate))
                                 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
                         handle_domain_irq(gic->domain, irqnr, regs);
@@ -383,7 +380,6 @@ static void gic_handle_cascade_irq(struct irq_desc *desc)
 }
 
 static struct irq_chip gic_chip = {
-        .name                   = "GIC",
         .irq_mask               = gic_mask_irq,
         .irq_unmask             = gic_unmask_irq,
         .irq_eoi                = gic_eoi_irq,
@@ -417,8 +413,7 @@ static struct irq_chip gic_eoimode1_chip = {
 
 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
 {
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
+        BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
         irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
                                          &gic_data[gic_nr]);
 }
@@ -524,7 +519,7 @@ int gic_cpu_if_down(unsigned int gic_nr)
         void __iomem *cpu_base;
         u32 val = 0;
 
-        if (gic_nr >= MAX_GIC_NR)
+        if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
                 return -EINVAL;
 
         cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
@@ -548,8 +543,7 @@ static void gic_dist_save(unsigned int gic_nr)
         void __iomem *dist_base;
         int i;
 
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
+        BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 
         gic_irqs = gic_data[gic_nr].gic_irqs;
         dist_base = gic_data_dist_base(&gic_data[gic_nr]);
@@ -587,8 +581,7 @@ static void gic_dist_restore(unsigned int gic_nr)
         unsigned int i;
         void __iomem *dist_base;
 
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
+        BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 
         gic_irqs = gic_data[gic_nr].gic_irqs;
         dist_base = gic_data_dist_base(&gic_data[gic_nr]);
@@ -634,8 +627,7 @@ static void gic_cpu_save(unsigned int gic_nr)
         void __iomem *dist_base;
         void __iomem *cpu_base;
 
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
+        BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 
         dist_base = gic_data_dist_base(&gic_data[gic_nr]);
         cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
@@ -664,8 +656,7 @@ static void gic_cpu_restore(unsigned int gic_nr)
         void __iomem *dist_base;
         void __iomem *cpu_base;
 
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
+        BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 
         dist_base = gic_data_dist_base(&gic_data[gic_nr]);
         cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
@@ -703,7 +694,7 @@ static int gic_notifier(struct notifier_block *self, unsigned long cmd,	void *v)
 {
         int i;
 
-        for (i = 0; i < MAX_GIC_NR; i++) {
+        for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
 #ifdef CONFIG_GIC_NON_BANKED
                 /* Skip over unused GICs */
                 if (!gic_data[i].get_base)
@@ -835,8 +826,7 @@ void gic_migrate_target(unsigned int new_cpu_id)
         int i, ror_val, cpu = smp_processor_id();
         u32 val, cur_target_mask, active_mask;
 
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
+        BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 
         dist_base = gic_data_dist_base(&gic_data[gic_nr]);
         if (!dist_base)
@@ -925,20 +915,15 @@ void __init gic_init_physaddr(struct device_node *node)
 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
                                 irq_hw_number_t hw)
 {
-        struct irq_chip *chip = &gic_chip;
-
-        if (static_key_true(&supports_deactivate)) {
-                if (d->host_data == (void *)&gic_data[0])
-                        chip = &gic_eoimode1_chip;
-        }
+        struct gic_chip_data *gic = d->host_data;
 
         if (hw < 32) {
                 irq_set_percpu_devid(irq);
-                irq_domain_set_info(d, irq, hw, chip, d->host_data,
+                irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
                                     handle_percpu_devid_irq, NULL, NULL);
                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
         } else {
-                irq_domain_set_info(d, irq, hw, chip, d->host_data,
+                irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
                                     handle_fasteoi_irq, NULL, NULL);
                 irq_set_probe(irq);
         }
@@ -972,7 +957,7 @@ static int gic_irq_domain_translate(struct irq_domain *d,
                 return 0;
         }
 
-        if (fwspec->fwnode->type == FWNODE_IRQCHIP) {
+        if (is_fwnode_irqchip(fwspec->fwnode)) {
                 if(fwspec->param_count != 2)
                         return -EINVAL;
 
@@ -1040,11 +1025,20 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
         struct gic_chip_data *gic;
         int gic_irqs, irq_base, i;
 
-        BUG_ON(gic_nr >= MAX_GIC_NR);
+        BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 
         gic_check_cpu_features();
 
         gic = &gic_data[gic_nr];
+
+        /* Initialize irq_chip */
+        if (static_key_true(&supports_deactivate) && gic_nr == 0) {
+                gic->chip = gic_eoimode1_chip;
+        } else {
+                gic->chip = gic_chip;
+                gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr);
+        }
+
 #ifdef CONFIG_GIC_NON_BANKED
         if (percpu_offset) { /* Frankein-GIC without banked registers... */
                 unsigned int cpu;
@@ -1196,7 +1190,7 @@ static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
         return true;
 }
 
-static int __init
+int __init
 gic_of_init(struct device_node *node, struct device_node *parent)
 {
         void __iomem *cpu_base;
@@ -1234,7 +1228,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
         }
 
         if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
-                gicv2m_of_init(node, gic_data[gic_cnt].domain);
+                gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
 
         gic_cnt++;
         return 0;
@@ -1359,6 +1353,10 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
         __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle);
 
         acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
+
+        if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
+                gicv2m_init(NULL, gic_data[0].domain);
+
         return 0;
 }
 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
new file mode 100644
index 000000000000..4dd3eb8a40b3
--- /dev/null
+++ b/drivers/irqchip/irq-mbigen.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright (C) 2015 Hisilicon Limited, All Rights Reserved.
+ * Author: Jun Ma <majun258@huawei.com>
+ * Author: Yun Wu <wuyun.wu@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irqchip.h>
+#include <linux/module.h>
+#include <linux/msi.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+/* Interrupt numbers per mbigen node supported */
+#define IRQS_PER_MBIGEN_NODE            128
+
+/* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
+#define RESERVED_IRQ_PER_MBIGEN_CHIP    64
+
+/* The maximum IRQ pin number of mbigen chip(start from 0) */
+#define MAXIMUM_IRQ_PIN_NUM             1407
+
+/**
+ * In mbigen vector register
+ * bit[21:12]:  event id value
+ * bit[11:0]:   device id
+ */
+#define IRQ_EVENT_ID_SHIFT              12
+#define IRQ_EVENT_ID_MASK               0x3ff
+
+/* register range of each mbigen node */
+#define MBIGEN_NODE_OFFSET              0x1000
+
+/* offset of vector register in mbigen node */
+#define REG_MBIGEN_VEC_OFFSET           0x200
+
+/**
+ * offset of clear register in mbigen node
+ * This register is used to clear the status
+ * of interrupt
+ */
+#define REG_MBIGEN_CLEAR_OFFSET         0xa000
+
+/**
+ * offset of interrupt type register
+ * This register is used to configure interrupt
+ * trigger type
+ */
+#define REG_MBIGEN_TYPE_OFFSET          0x0
+
+/**
+ * struct mbigen_device - holds the information of mbigen device.
+ *
+ * @pdev:               pointer to the platform device structure of mbigen chip.
+ * @base:               mapped address of this mbigen chip.
+ */
+struct mbigen_device {
+        struct platform_device  *pdev;
+        void __iomem            *base;
+};
+
+static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
+{
+        unsigned int nid, pin;
+
+        hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
+        nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
+        pin = hwirq % IRQS_PER_MBIGEN_NODE;
+
+        return pin * 4 + nid * MBIGEN_NODE_OFFSET
+                        + REG_MBIGEN_VEC_OFFSET;
+}
+
+static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
+                                        u32 *mask, u32 *addr)
+{
+        unsigned int nid, irq_ofst, ofst;
+
+        hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
+        nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
+        irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
+
+        *mask = 1 << (irq_ofst % 32);
+        ofst = irq_ofst / 32 * 4;
+
+        *addr = ofst + nid * MBIGEN_NODE_OFFSET
+                + REG_MBIGEN_TYPE_OFFSET;
+}
+
+static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
+                                        u32 *mask, u32 *addr)
+{
+        unsigned int ofst;
+
+        hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
+        ofst = hwirq / 32 * 4;
+
+        *mask = 1 << (hwirq % 32);
+        *addr = ofst + REG_MBIGEN_CLEAR_OFFSET;
+}
+
+static void mbigen_eoi_irq(struct irq_data *data)
+{
+        void __iomem *base = data->chip_data;
+        u32 mask, addr;
+
+        get_mbigen_clear_reg(data->hwirq, &mask, &addr);
+
+        writel_relaxed(mask, base + addr);
+
+        irq_chip_eoi_parent(data);
+}
+
+static int mbigen_set_type(struct irq_data *data, unsigned int type)
+{
+        void __iomem *base = data->chip_data;
+        u32 mask, addr, val;
+
+        if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
+                return -EINVAL;
+
+        get_mbigen_type_reg(data->hwirq, &mask, &addr);
+
+        val = readl_relaxed(base + addr);
+
+        if (type == IRQ_TYPE_LEVEL_HIGH)
+                val |= mask;
+        else
+                val &= ~mask;
+
+        writel_relaxed(val, base + addr);
+
+        return 0;
+}
+
+static struct irq_chip mbigen_irq_chip = {
+        .name =                 "mbigen-v2",
+        .irq_mask =             irq_chip_mask_parent,
+        .irq_unmask =           irq_chip_unmask_parent,
+        .irq_eoi =              mbigen_eoi_irq,
+        .irq_set_type =         mbigen_set_type,
+        .irq_set_affinity =     irq_chip_set_affinity_parent,
+};
+
+static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
+{
+        struct irq_data *d = irq_get_irq_data(desc->irq);
+        void __iomem *base = d->chip_data;
+        u32 val;
+
+        base += get_mbigen_vec_reg(d->hwirq);
+        val = readl_relaxed(base);
+
+        val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
+        val |= (msg->data << IRQ_EVENT_ID_SHIFT);
+
+        /* The address of doorbell is encoded in mbigen register by default
+         * So,we don't need to program the doorbell address at here
+         */
+        writel_relaxed(val, base);
+}
+
+static int mbigen_domain_translate(struct irq_domain *d,
+                                    struct irq_fwspec *fwspec,
+                                    unsigned long *hwirq,
+                                    unsigned int *type)
+{
+        if (is_of_node(fwspec->fwnode)) {
+                if (fwspec->param_count != 2)
+                        return -EINVAL;
+
+                if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
+                        (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
+                        return -EINVAL;
+                else
+                        *hwirq = fwspec->param[0];
+
+                /* If there is no valid irq type, just use the default type */
+                if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) ||
+                        (fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
+                        *type = fwspec->param[1];
+                else
+                        return -EINVAL;
+
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static int mbigen_irq_domain_alloc(struct irq_domain *domain,
+                                        unsigned int virq,
+                                        unsigned int nr_irqs,
+                                        void *args)
+{
+        struct irq_fwspec *fwspec = args;
+        irq_hw_number_t hwirq;
+        unsigned int type;
+        struct mbigen_device *mgn_chip;
+        int i, err;
+
+        err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
+        if (err)
+                return err;
+
+        err = platform_msi_domain_alloc(domain, virq, nr_irqs);
+        if (err)
+                return err;
+
+        mgn_chip = platform_msi_get_host_data(domain);
+
+        for (i = 0; i < nr_irqs; i++)
+                irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
+                                      &mbigen_irq_chip, mgn_chip->base);
+
+        return 0;
+}
+
+static struct irq_domain_ops mbigen_domain_ops = {
+        .translate      = mbigen_domain_translate,
+        .alloc          = mbigen_irq_domain_alloc,
+        .free           = irq_domain_free_irqs_common,
+};
+
+static int mbigen_device_probe(struct platform_device *pdev)
+{
+        struct mbigen_device *mgn_chip;
+        struct resource *res;
+        struct irq_domain *domain;
+        u32 num_pins;
+
+        mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
+        if (!mgn_chip)
+                return -ENOMEM;
+
+        mgn_chip->pdev = pdev;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        mgn_chip->base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(mgn_chip->base))
+                return PTR_ERR(mgn_chip->base);
+
+        if (of_property_read_u32(pdev->dev.of_node, "num-pins", &num_pins) < 0) {
+                dev_err(&pdev->dev, "No num-pins property\n");
+                return -EINVAL;
+        }
+
+        domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
+                                                        mbigen_write_msg,
+                                                        &mbigen_domain_ops,
+                                                        mgn_chip);
+
+        if (!domain)
+                return -ENOMEM;
+
+        platform_set_drvdata(pdev, mgn_chip);
+
+        dev_info(&pdev->dev, "Allocated %d MSIs\n", num_pins);
+
+        return 0;
+}
+
+static const struct of_device_id mbigen_of_match[] = {
+        { .compatible = "hisilicon,mbigen-v2" },
+        { /* END */ }
+};
+MODULE_DEVICE_TABLE(of, mbigen_of_match);
+
+static struct platform_driver mbigen_platform_driver = {
+        .driver = {
+                .name           = "Hisilicon MBIGEN-V2",
+                .owner          = THIS_MODULE,
+                .of_match_table = mbigen_of_match,
+        },
+        .probe                  = mbigen_device_probe,
+};
+
+module_platform_driver(mbigen_platform_driver);
+
+MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
+MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Hisilicon MBI Generator driver");
diff --git a/drivers/irqchip/irq-omap-intc.c b/drivers/irqchip/irq-omap-intc.c
index 8587d0f8d8c0..9d1bcfc33e4c 100644
--- a/drivers/irqchip/irq-omap-intc.c
+++ b/drivers/irqchip/irq-omap-intc.c
@@ -47,6 +47,7 @@
 #define INTC_ILR0               0x0100
 
 #define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
+#define SPURIOUSIRQ_MASK        (0x1ffffff << 7)
 #define INTCPS_NR_ILR_REGS      128
 #define INTCPS_NR_MIR_REGS      4
 
@@ -207,7 +208,6 @@ static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
                 ct = gc->chip_types;
 
                 ct->type = IRQ_TYPE_LEVEL_MASK;
-                ct->handler = handle_level_irq;
 
                 ct->chip.irq_ack = omap_mask_ack_irq;
                 ct->chip.irq_mask = irq_gc_mask_disable_reg;
@@ -330,11 +330,35 @@ static int __init omap_init_irq(u32 base, struct device_node *node)
 static asmlinkage void __exception_irq_entry
 omap_intc_handle_irq(struct pt_regs *regs)
 {
+        extern unsigned long irq_err_count;
         u32 irqnr;
 
         irqnr = intc_readl(INTC_SIR);
+
+        /*
+         * A spurious IRQ can result if interrupt that triggered the
+         * sorting is no longer active during the sorting (10 INTC
+         * functional clock cycles after interrupt assertion). Or a
+         * change in interrupt mask affected the result during sorting
+         * time. There is no special handling required except ignoring
+         * the SIR register value just read and retrying.
+         * See section 6.2.5 of AM335x TRM Literature Number: SPRUH73K
+         *
+         * Many a times, a spurious interrupt situation has been fixed
+         * by adding a flush for the posted write acking the IRQ in
+         * the device driver. Typically, this is going be the device
+         * driver whose interrupt was handled just before the spurious
+         * IRQ occurred. Pay attention to those device drivers if you
+         * run into hitting the spurious IRQ condition below.
+         */
+        if (unlikely((irqnr & SPURIOUSIRQ_MASK) == SPURIOUSIRQ_MASK)) {
+                pr_err_once("%s: spurious irq!\n", __func__);
+                irq_err_count++;
+                omap_ack_irq(NULL);
+                return;
+        }
+
         irqnr &= ACTIVEIRQ_MASK;
-        WARN_ONCE(!irqnr, "Spurious IRQ ?\n");
         handle_domain_irq(domain, irqnr, regs);
 }
 
diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
index c325806561be..713177d97c7a 100644
--- a/drivers/irqchip/irq-renesas-intc-irqpin.c
+++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
@@ -31,7 +31,6 @@
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
-#include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <linux/pm_runtime.h>
 
 #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
@@ -75,18 +74,20 @@ struct intc_irqpin_irq {
 struct intc_irqpin_priv {
         struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
         struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
-        struct renesas_intc_irqpin_config config;
-        unsigned int number_of_irqs;
+        unsigned int sense_bitfield_width;
         struct platform_device *pdev;
         struct irq_chip irq_chip;
         struct irq_domain *irq_domain;
         struct clk *clk;
-        bool shared_irqs;
+        unsigned shared_irqs:1;
+        unsigned needs_clk:1;
         u8 shared_irq_mask;
 };
 
-struct intc_irqpin_irlm_config {
+struct intc_irqpin_config {
         unsigned int irlm_bit;
+        unsigned needs_irlm:1;
+        unsigned needs_clk:1;
 };
 
 static unsigned long intc_irqpin_read32(void __iomem *iomem)
@@ -171,7 +172,7 @@ static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
 static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
 {
         /* The SENSE register is assumed to be 32-bit. */
-        int bitfield_width = p->config.sense_bitfield_width;
+        int bitfield_width = p->sense_bitfield_width;
         int shift = 32 - (irq + 1) * bitfield_width;
 
         dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
@@ -361,8 +362,15 @@ static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
         .xlate  = irq_domain_xlate_twocell,
 };
 
-static const struct intc_irqpin_irlm_config intc_irqpin_irlm_r8a777x = {
+static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
         .irlm_bit = 23, /* ICR0.IRLM0 */
+        .needs_irlm = 1,
+        .needs_clk = 0,
+};
+
+static const struct intc_irqpin_config intc_irqpin_rmobile = {
+        .needs_irlm = 0,
+        .needs_clk = 1,
 };
 
 static const struct of_device_id intc_irqpin_dt_ids[] = {
@@ -371,14 +379,18 @@ static const struct of_device_id intc_irqpin_dt_ids[] = {
           .data = &intc_irqpin_irlm_r8a777x },
         { .compatible = "renesas,intc-irqpin-r8a7779",
           .data = &intc_irqpin_irlm_r8a777x },
+        { .compatible = "renesas,intc-irqpin-r8a7740",
+          .data = &intc_irqpin_rmobile },
+        { .compatible = "renesas,intc-irqpin-sh73a0",
+          .data = &intc_irqpin_rmobile },
         {},
 };
 MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
 
 static int intc_irqpin_probe(struct platform_device *pdev)
 {
+        const struct intc_irqpin_config *config = NULL;
         struct device *dev = &pdev->dev;
-        struct renesas_intc_irqpin_config *pdata = dev->platform_data;
         const struct of_device_id *of_id;
         struct intc_irqpin_priv *p;
         struct intc_irqpin_iomem *i;
@@ -388,6 +400,8 @@ static int intc_irqpin_probe(struct platform_device *pdev)
         void (*enable_fn)(struct irq_data *d);
         void (*disable_fn)(struct irq_data *d);
         const char *name = dev_name(dev);
+        bool control_parent;
+        unsigned int nirqs;
         int ref_irq;
         int ret;
         int k;
@@ -399,23 +413,28 @@ static int intc_irqpin_probe(struct platform_device *pdev)
         }
 
         /* deal with driver instance configuration */
-        if (pdata) {
-                memcpy(&p->config, pdata, sizeof(*pdata));
-        } else {
-                of_property_read_u32(dev->of_node, "sense-bitfield-width",
-                                     &p->config.sense_bitfield_width);
-                p->config.control_parent = of_property_read_bool(dev->of_node,
-                                                                 "control-parent");
-        }
-        if (!p->config.sense_bitfield_width)
-                p->config.sense_bitfield_width = 4; /* default to 4 bits */
+        of_property_read_u32(dev->of_node, "sense-bitfield-width",
+                             &p->sense_bitfield_width);
+        control_parent = of_property_read_bool(dev->of_node, "control-parent");
+        if (!p->sense_bitfield_width)
+                p->sense_bitfield_width = 4; /* default to 4 bits */
 
         p->pdev = pdev;
         platform_set_drvdata(pdev, p);
 
+        of_id = of_match_device(intc_irqpin_dt_ids, dev);
+        if (of_id && of_id->data) {
+                config = of_id->data;
+                p->needs_clk = config->needs_clk;
+        }
+
         p->clk = devm_clk_get(dev, NULL);
         if (IS_ERR(p->clk)) {
-                dev_warn(dev, "unable to get clock\n");
+                if (p->needs_clk) {
+                        dev_err(dev, "unable to get clock\n");
+                        ret = PTR_ERR(p->clk);
+                        goto err0;
+                }
                 p->clk = NULL;
         }
 
@@ -443,8 +462,8 @@ static int intc_irqpin_probe(struct platform_device *pdev)
                 p->irq[k].requested_irq = irq->start;
         }
 
-        p->number_of_irqs = k;
-        if (p->number_of_irqs < 1) {
+        nirqs = k;
+        if (nirqs < 1) {
                 dev_err(dev, "not enough IRQ resources\n");
                 ret = -EINVAL;
                 goto err0;
@@ -485,20 +504,16 @@ static int intc_irqpin_probe(struct platform_device *pdev)
         }
 
         /* configure "individual IRQ mode" where needed */
-        of_id = of_match_device(intc_irqpin_dt_ids, dev);
-        if (of_id && of_id->data) {
-                const struct intc_irqpin_irlm_config *irlm_config = of_id->data;
-
+        if (config && config->needs_irlm) {
                 if (io[INTC_IRQPIN_REG_IRLM])
                         intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
-                                                      irlm_config->irlm_bit,
-                                                      1, 1);
+                                                      config->irlm_bit, 1, 1);
                 else
                         dev_warn(dev, "unable to select IRLM mode\n");
         }
 
         /* mask all interrupts using priority */
-        for (k = 0; k < p->number_of_irqs; k++)
+        for (k = 0; k < nirqs; k++)
                 intc_irqpin_mask_unmask_prio(p, k, 1);
 
         /* clear all pending interrupts */
@@ -506,16 +521,16 @@ static int intc_irqpin_probe(struct platform_device *pdev)
 
         /* scan for shared interrupt lines */
         ref_irq = p->irq[0].requested_irq;
-        p->shared_irqs = true;
-        for (k = 1; k < p->number_of_irqs; k++) {
+        p->shared_irqs = 1;
+        for (k = 1; k < nirqs; k++) {
                 if (ref_irq != p->irq[k].requested_irq) {
-                        p->shared_irqs = false;
+                        p->shared_irqs = 0;
                         break;
                 }
         }
 
         /* use more severe masking method if requested */
-        if (p->config.control_parent) {
+        if (control_parent) {
                 enable_fn = intc_irqpin_irq_enable_force;
                 disable_fn = intc_irqpin_irq_disable_force;
         } else if (!p->shared_irqs) {
@@ -534,9 +549,7 @@ static int intc_irqpin_probe(struct platform_device *pdev)
         irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
         irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
 
-        p->irq_domain = irq_domain_add_simple(dev->of_node,
-                                              p->number_of_irqs,
-                                              p->config.irq_base,
+        p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
                                               &intc_irqpin_irq_domain_ops, p);
         if (!p->irq_domain) {
                 ret = -ENXIO;
@@ -555,7 +568,7 @@ static int intc_irqpin_probe(struct platform_device *pdev)
                 }
         } else {
                 /* request interrupts one by one */
-                for (k = 0; k < p->number_of_irqs; k++) {
+                for (k = 0; k < nirqs; k++) {
                         if (devm_request_irq(dev, p->irq[k].requested_irq,
                                              intc_irqpin_irq_handler, 0, name,
                                              &p->irq[k])) {
@@ -567,17 +580,10 @@ static int intc_irqpin_probe(struct platform_device *pdev)
         }
 
         /* unmask all interrupts on prio level */
-        for (k = 0; k < p->number_of_irqs; k++)
+        for (k = 0; k < nirqs; k++)
                 intc_irqpin_mask_unmask_prio(p, k, 0);
 
-        dev_info(dev, "driving %d irqs\n", p->number_of_irqs);
-
-        /* warn in case of mismatch if irq base is specified */
-        if (p->config.irq_base) {
-                if (p->config.irq_base != p->irq[0].domain_irq)
-                        dev_warn(dev, "irq base mismatch (%d/%d)\n",
-                                 p->config.irq_base, p->irq[0].domain_irq);
-        }
+        dev_info(dev, "driving %d irqs\n", nirqs);
 
         return 0;
 
diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
index 4ef178078e5b..0820f67cc9a7 100644
--- a/drivers/irqchip/irq-sunxi-nmi.c
+++ b/drivers/irqchip/irq-sunxi-nmi.c
@@ -50,6 +50,12 @@ static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = {
         .enable = 0x34,
 };
 
+static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs = {
+        .ctrl   = 0x00,
+        .pend   = 0x08,
+        .enable = 0x04,
+};
+
 static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
                                       u32 val)
 {
@@ -207,3 +213,10 @@ static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
         return sunxi_sc_nmi_irq_init(node, &sun7i_reg_offs);
 }
 IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);
+
+static int __init sun9i_nmi_irq_init(struct device_node *node,
+                                     struct device_node *parent)
+{
+        return sunxi_sc_nmi_irq_init(node, &sun9i_reg_offs);
+}
+IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi", sun9i_nmi_irq_init);
diff --git a/drivers/irqchip/irq-ts4800.c b/drivers/irqchip/irq-ts4800.c
new file mode 100644
index 000000000000..4192bdcd2734
--- /dev/null
+++ b/drivers/irqchip/irq-ts4800.c
@@ -0,0 +1,163 @@
+/*
+ * Multiplexed-IRQs driver for TS-4800's FPGA
+ *
+ * Copyright (c) 2015 - Savoir-faire Linux
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+
+#define IRQ_MASK        0x4
+#define IRQ_STATUS      0x8
+
+struct ts4800_irq_data {
+        void __iomem            *base;
+        struct irq_domain       *domain;
+        struct irq_chip         irq_chip;
+};
+
+static void ts4800_irq_mask(struct irq_data *d)
+{
+        struct ts4800_irq_data *data = irq_data_get_irq_chip_data(d);
+        u16 reg = readw(data->base + IRQ_MASK);
+        u16 mask = 1 << d->hwirq;
+
+        writew(reg | mask, data->base + IRQ_MASK);
+}
+
+static void ts4800_irq_unmask(struct irq_data *d)
+{
+        struct ts4800_irq_data *data = irq_data_get_irq_chip_data(d);
+        u16 reg = readw(data->base + IRQ_MASK);
+        u16 mask = 1 << d->hwirq;
+
+        writew(reg & ~mask, data->base + IRQ_MASK);
+}
+
+static int ts4800_irqdomain_map(struct irq_domain *d, unsigned int irq,
+                                irq_hw_number_t hwirq)
+{
+        struct ts4800_irq_data *data = d->host_data;
+
+        irq_set_chip_and_handler(irq, &data->irq_chip, handle_simple_irq);
+        irq_set_chip_data(irq, data);
+        irq_set_noprobe(irq);
+
+        return 0;
+}
+
+struct irq_domain_ops ts4800_ic_ops = {
+        .map = ts4800_irqdomain_map,
+        .xlate = irq_domain_xlate_onecell,
+};
+
+static void ts4800_ic_chained_handle_irq(struct irq_desc *desc)
+{
+        struct ts4800_irq_data *data = irq_desc_get_handler_data(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        u16 status = readw(data->base + IRQ_STATUS);
+
+        chained_irq_enter(chip, desc);
+
+        if (unlikely(status == 0)) {
+                handle_bad_irq(desc);
+                goto out;
+        }
+
+        do {
+                unsigned int bit = __ffs(status);
+                int irq = irq_find_mapping(data->domain, bit);
+
+                status &= ~(1 << bit);
+                generic_handle_irq(irq);
+        } while (status);
+
+out:
+        chained_irq_exit(chip, desc);
+}
+
+static int ts4800_ic_probe(struct platform_device *pdev)
+{
+        struct device_node *node = pdev->dev.of_node;
+        struct ts4800_irq_data *data;
+        struct irq_chip *irq_chip;
+        struct resource *res;
+        int parent_irq;
+
+        data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+        if (!data)
+                return -ENOMEM;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        data->base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(data->base))
+                return PTR_ERR(data->base);
+
+        writew(0xFFFF, data->base + IRQ_MASK);
+
+        parent_irq = irq_of_parse_and_map(node, 0);
+        if (!parent_irq) {
+                dev_err(&pdev->dev, "failed to get parent IRQ\n");
+                return -EINVAL;
+        }
+
+        irq_chip = &data->irq_chip;
+        irq_chip->name = dev_name(&pdev->dev);
+        irq_chip->irq_mask = ts4800_irq_mask;
+        irq_chip->irq_unmask = ts4800_irq_unmask;
+
+        data->domain = irq_domain_add_linear(node, 8, &ts4800_ic_ops, data);
+        if (!data->domain) {
+                dev_err(&pdev->dev, "cannot add IRQ domain\n");
+                return -ENOMEM;
+        }
+
+        irq_set_chained_handler_and_data(parent_irq,
+                                         ts4800_ic_chained_handle_irq, data);
+
+        platform_set_drvdata(pdev, data);
+
+        return 0;
+}
+
+static int ts4800_ic_remove(struct platform_device *pdev)
+{
+        struct ts4800_irq_data *data = platform_get_drvdata(pdev);
+
+        irq_domain_remove(data->domain);
+
+        return 0;
+}
+
+static const struct of_device_id ts4800_ic_of_match[] = {
+        { .compatible = "technologic,ts4800-irqc", },
+        {},
+};
+MODULE_DEVICE_TABLE(of, ts4800_ic_of_match);
+
+static struct platform_driver ts4800_ic_driver = {
+        .probe  = ts4800_ic_probe,
+        .remove = ts4800_ic_remove,
+        .driver = {
+                .name = "ts4800-irqc",
+                .of_match_table = ts4800_ic_of_match,
+        },
+};
+module_platform_driver(ts4800_ic_driver);
+
+MODULE_AUTHOR("Damien Riegel <damien.riegel@savoirfairelinux.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:ts4800_irqc");
diff --git a/drivers/irqchip/irq-zevio.c b/drivers/irqchip/irq-zevio.c
index 4c48fa88a03d..cb9d8ec37507 100644
--- a/drivers/irqchip/irq-zevio.c
+++ b/drivers/irqchip/irq-zevio.c
@@ -43,8 +43,7 @@ static void __iomem *zevio_irq_io;
 static void zevio_irq_ack(struct irq_data *irqd)
 {
         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(irqd);
-        struct irq_chip_regs *regs =
-                &container_of(irqd->chip, struct irq_chip_type, chip)->regs;
+        struct irq_chip_regs *regs = &irq_data_get_chip_type(irqd)->regs;
 
         readl(gc->reg_base + regs->ack);
 }