diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2015-05-18 17:59:13 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2015-05-18 17:59:33 -0400 |
commit | 939ef66848ea2b069d938146332fe07e8b6c84af (patch) | |
tree | 8d69247238065db0437970fe512a9ecfec3a5541 /drivers/irqchip/irq-vf610-mscm-ir.c | |
parent | 3c646f2c6aa9e918d7fc77867df7f430059f9ccc (diff) | |
parent | b5cc5cbc116975812917db6de023cde928935910 (diff) |
Merge branch 'irq/for-arm' into irq/core
Pull in the branch which can be consumed by ARM to build their changes
on top.
Diffstat (limited to 'drivers/irqchip/irq-vf610-mscm-ir.c')
-rw-r--r-- | drivers/irqchip/irq-vf610-mscm-ir.c | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/drivers/irqchip/irq-vf610-mscm-ir.c b/drivers/irqchip/irq-vf610-mscm-ir.c index d0f940a3516d..f5c01cbcc73a 100644 --- a/drivers/irqchip/irq-vf610-mscm-ir.c +++ b/drivers/irqchip/irq-vf610-mscm-ir.c | |||
@@ -47,6 +47,7 @@ struct vf610_mscm_ir_chip_data { | |||
47 | void __iomem *mscm_ir_base; | 47 | void __iomem *mscm_ir_base; |
48 | u16 cpu_mask; | 48 | u16 cpu_mask; |
49 | u16 saved_irsprc[MSCM_IRSPRC_NUM]; | 49 | u16 saved_irsprc[MSCM_IRSPRC_NUM]; |
50 | bool is_nvic; | ||
50 | }; | 51 | }; |
51 | 52 | ||
52 | static struct vf610_mscm_ir_chip_data *mscm_ir_data; | 53 | static struct vf610_mscm_ir_chip_data *mscm_ir_data; |
@@ -101,7 +102,7 @@ static void vf610_mscm_ir_enable(struct irq_data *data) | |||
101 | writew_relaxed(chip_data->cpu_mask, | 102 | writew_relaxed(chip_data->cpu_mask, |
102 | chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq)); | 103 | chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq)); |
103 | 104 | ||
104 | irq_chip_unmask_parent(data); | 105 | irq_chip_enable_parent(data); |
105 | } | 106 | } |
106 | 107 | ||
107 | static void vf610_mscm_ir_disable(struct irq_data *data) | 108 | static void vf610_mscm_ir_disable(struct irq_data *data) |
@@ -111,7 +112,7 @@ static void vf610_mscm_ir_disable(struct irq_data *data) | |||
111 | 112 | ||
112 | writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq)); | 113 | writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq)); |
113 | 114 | ||
114 | irq_chip_mask_parent(data); | 115 | irq_chip_disable_parent(data); |
115 | } | 116 | } |
116 | 117 | ||
117 | static struct irq_chip vf610_mscm_ir_irq_chip = { | 118 | static struct irq_chip vf610_mscm_ir_irq_chip = { |
@@ -143,10 +144,17 @@ static int vf610_mscm_ir_domain_alloc(struct irq_domain *domain, unsigned int vi | |||
143 | domain->host_data); | 144 | domain->host_data); |
144 | 145 | ||
145 | gic_data.np = domain->parent->of_node; | 146 | gic_data.np = domain->parent->of_node; |
146 | gic_data.args_count = 3; | 147 | |
147 | gic_data.args[0] = GIC_SPI; | 148 | if (mscm_ir_data->is_nvic) { |
148 | gic_data.args[1] = irq_data->args[0]; | 149 | gic_data.args_count = 1; |
149 | gic_data.args[2] = irq_data->args[1]; | 150 | gic_data.args[0] = irq_data->args[0]; |
151 | } else { | ||
152 | gic_data.args_count = 3; | ||
153 | gic_data.args[0] = GIC_SPI; | ||
154 | gic_data.args[1] = irq_data->args[0]; | ||
155 | gic_data.args[2] = irq_data->args[1]; | ||
156 | } | ||
157 | |||
150 | return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data); | 158 | return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data); |
151 | } | 159 | } |
152 | 160 | ||
@@ -198,6 +206,9 @@ static int __init vf610_mscm_ir_of_init(struct device_node *node, | |||
198 | goto out_unmap; | 206 | goto out_unmap; |
199 | } | 207 | } |
200 | 208 | ||
209 | if (of_device_is_compatible(domain->parent->of_node, "arm,armv7m-nvic")) | ||
210 | mscm_ir_data->is_nvic = true; | ||
211 | |||
201 | cpu_pm_register_notifier(&mscm_ir_notifier_block); | 212 | cpu_pm_register_notifier(&mscm_ir_notifier_block); |
202 | 213 | ||
203 | return 0; | 214 | return 0; |