qed*: Refactoring and rearranging FW API with no functional impact

This patch refactors and reorders the FW API files in preparation of
upgrading the code to support new FW.

- Make use of the BIT macro in appropriate places.
- Whitespace changes to align values and code blocks.
- Comments are updated (spelling mistakes, removed if not clear).
- Group together code blocks which are related or deal with similar
 matters.

Signed-off-by: Ariel Elior <Ariel.Elior@cavium.com>
Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com>
Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 54 insertions, 54 deletions

diff --git a/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h b/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
index b7587f10e7de..b67a89b39553 100644
--- a/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
+++ b/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
@@ -180,12 +180,12 @@ struct rdma_pwm_val32_data {
         __le16 icid;
         u8 agg_flags;
         u8 params;
-#define RDMA_PWM_VAL32_DATA_AGG_CMD_MASK    0x3
-#define RDMA_PWM_VAL32_DATA_AGG_CMD_SHIFT   0
-#define RDMA_PWM_VAL32_DATA_BYPASS_EN_MASK  0x1
-#define RDMA_PWM_VAL32_DATA_BYPASS_EN_SHIFT 2
-#define RDMA_PWM_VAL32_DATA_RESERVED_MASK   0x1F
-#define RDMA_PWM_VAL32_DATA_RESERVED_SHIFT  3
+#define RDMA_PWM_VAL32_DATA_AGG_CMD_MASK                0x3
+#define RDMA_PWM_VAL32_DATA_AGG_CMD_SHIFT               0
+#define RDMA_PWM_VAL32_DATA_BYPASS_EN_MASK              0x1
+#define RDMA_PWM_VAL32_DATA_BYPASS_EN_SHIFT             2
+#define RDMA_PWM_VAL32_DATA_RESERVED_MASK               0x1F
+#define RDMA_PWM_VAL32_DATA_RESERVED_SHIFT              3
         __le32 value;
 };
 
@@ -478,23 +478,23 @@ struct rdma_sq_fmr_wqe {
         __le16 dif_app_tag_mask;
         __le16 dif_runt_crc_value;
         __le16 dif_flags;
-#define RDMA_SQ_FMR_WQE_DIF_IO_DIRECTION_FLG_MASK    0x1
-#define RDMA_SQ_FMR_WQE_DIF_IO_DIRECTION_FLG_SHIFT   0
-#define RDMA_SQ_FMR_WQE_DIF_BLOCK_SIZE_MASK          0x1
-#define RDMA_SQ_FMR_WQE_DIF_BLOCK_SIZE_SHIFT         1
-#define RDMA_SQ_FMR_WQE_DIF_RUNT_VALID_FLG_MASK      0x1
-#define RDMA_SQ_FMR_WQE_DIF_RUNT_VALID_FLG_SHIFT     2
-#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_CRC_GUARD_MASK  0x1
-#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_CRC_GUARD_SHIFT 3
-#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_REF_TAG_MASK    0x1
-#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_REF_TAG_SHIFT   4
-#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_APP_TAG_MASK    0x1
-#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_APP_TAG_SHIFT   5
-#define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_MASK            0x1
-#define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_SHIFT           6
-#define RDMA_SQ_FMR_WQE_RESERVED4_MASK               0x1FF
-#define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT              7
-        __le32 Reserved5;
+#define RDMA_SQ_FMR_WQE_DIF_IO_DIRECTION_FLG_MASK       0x1
+#define RDMA_SQ_FMR_WQE_DIF_IO_DIRECTION_FLG_SHIFT      0
+#define RDMA_SQ_FMR_WQE_DIF_BLOCK_SIZE_MASK             0x1
+#define RDMA_SQ_FMR_WQE_DIF_BLOCK_SIZE_SHIFT            1
+#define RDMA_SQ_FMR_WQE_DIF_RUNT_VALID_FLG_MASK         0x1
+#define RDMA_SQ_FMR_WQE_DIF_RUNT_VALID_FLG_SHIFT        2
+#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_CRC_GUARD_MASK     0x1
+#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_CRC_GUARD_SHIFT    3
+#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_REF_TAG_MASK       0x1
+#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_REF_TAG_SHIFT      4
+#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_APP_TAG_MASK       0x1
+#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_APP_TAG_SHIFT      5
+#define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_MASK               0x1
+#define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_SHIFT              6
+#define RDMA_SQ_FMR_WQE_RESERVED4_MASK                  0x1FF
+#define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT                 7
+        __le32 reserved5;
 };
 
 /* First element (16 bytes) of fmr wqe */
@@ -558,23 +558,23 @@ struct rdma_sq_fmr_wqe_3rd {
         __le16 dif_app_tag_mask;
         __le16 dif_runt_crc_value;
         __le16 dif_flags;
-#define RDMA_SQ_FMR_WQE_3RD_DIF_IO_DIRECTION_FLG_MASK    0x1
-#define RDMA_SQ_FMR_WQE_3RD_DIF_IO_DIRECTION_FLG_SHIFT   0
-#define RDMA_SQ_FMR_WQE_3RD_DIF_BLOCK_SIZE_MASK          0x1
-#define RDMA_SQ_FMR_WQE_3RD_DIF_BLOCK_SIZE_SHIFT         1
-#define RDMA_SQ_FMR_WQE_3RD_DIF_RUNT_VALID_FLG_MASK      0x1
-#define RDMA_SQ_FMR_WQE_3RD_DIF_RUNT_VALID_FLG_SHIFT     2
-#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_CRC_GUARD_MASK  0x1
-#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_CRC_GUARD_SHIFT 3
-#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_REF_TAG_MASK    0x1
-#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_REF_TAG_SHIFT   4
-#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_APP_TAG_MASK    0x1
-#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_APP_TAG_SHIFT   5
-#define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_MASK            0x1
-#define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_SHIFT           6
-#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_MASK               0x1FF
-#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_SHIFT              7
-        __le32 Reserved5;
+#define RDMA_SQ_FMR_WQE_3RD_DIF_IO_DIRECTION_FLG_MASK           0x1
+#define RDMA_SQ_FMR_WQE_3RD_DIF_IO_DIRECTION_FLG_SHIFT          0
+#define RDMA_SQ_FMR_WQE_3RD_DIF_BLOCK_SIZE_MASK                 0x1
+#define RDMA_SQ_FMR_WQE_3RD_DIF_BLOCK_SIZE_SHIFT                1
+#define RDMA_SQ_FMR_WQE_3RD_DIF_RUNT_VALID_FLG_MASK             0x1
+#define RDMA_SQ_FMR_WQE_3RD_DIF_RUNT_VALID_FLG_SHIFT            2
+#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_CRC_GUARD_MASK         0x1
+#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_CRC_GUARD_SHIFT        3
+#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_REF_TAG_MASK           0x1
+#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_REF_TAG_SHIFT          4
+#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_APP_TAG_MASK           0x1
+#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_APP_TAG_SHIFT          5
+#define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_MASK                   0x1
+#define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_SHIFT                  6
+#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_MASK                      0x1FF
+#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_SHIFT                     7
+        __le32 reserved5;
 };
 
 struct rdma_sq_local_inv_wqe {
@@ -606,20 +606,20 @@ struct rdma_sq_rdma_wqe {
         __le32 xrc_srq;
         u8 req_type;
         u8 flags;
-#define RDMA_SQ_RDMA_WQE_COMP_FLG_MASK                  0x1
-#define RDMA_SQ_RDMA_WQE_COMP_FLG_SHIFT                 0
-#define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_MASK              0x1
-#define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_SHIFT             1
-#define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_MASK             0x1
-#define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_SHIFT            2
-#define RDMA_SQ_RDMA_WQE_SE_FLG_MASK                    0x1
-#define RDMA_SQ_RDMA_WQE_SE_FLG_SHIFT                   3
-#define RDMA_SQ_RDMA_WQE_INLINE_FLG_MASK                0x1
-#define RDMA_SQ_RDMA_WQE_INLINE_FLG_SHIFT               4
-#define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_MASK           0x1
-#define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_SHIFT          5
-#define RDMA_SQ_RDMA_WQE_RESERVED0_MASK                 0x3
-#define RDMA_SQ_RDMA_WQE_RESERVED0_SHIFT                6
+#define RDMA_SQ_RDMA_WQE_COMP_FLG_MASK          0x1
+#define RDMA_SQ_RDMA_WQE_COMP_FLG_SHIFT         0
+#define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_MASK      0x1
+#define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_SHIFT     1
+#define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_MASK     0x1
+#define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_SHIFT    2
+#define RDMA_SQ_RDMA_WQE_SE_FLG_MASK            0x1
+#define RDMA_SQ_RDMA_WQE_SE_FLG_SHIFT           3
+#define RDMA_SQ_RDMA_WQE_INLINE_FLG_MASK        0x1
+#define RDMA_SQ_RDMA_WQE_INLINE_FLG_SHIFT       4
+#define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_MASK   0x1
+#define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_SHIFT  5
+#define RDMA_SQ_RDMA_WQE_RESERVED0_MASK         0x3
+#define RDMA_SQ_RDMA_WQE_RESERVED0_SHIFT        6
         u8 wqe_size;
         u8 prev_wqe_size;
         struct regpair remote_va;