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authorMichał Mirosław <mirq-linux@rere.qmqm.pl>2017-09-17 11:01:04 -0400
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2017-10-09 15:50:06 -0400
commit1540d0106bcbc4e52013d759a0a0752ae7b4a09d (patch)
tree593cf7e6a49fc305950c23e95537f863052d50ab /drivers/iio
parentd2ff1956ba279bc1400924b20f85e25c4d4ca989 (diff)
iio: accel: kxcjk1013: add support for KXTF9
KXTF9 has mostly compatible register layout to KXCJK accelerometer. There is no motion direction interrupt support, but there is tap direction detection instead (not implemented in this patch). Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/iio')
-rw-r--r--drivers/iio/accel/Kconfig4
-rw-r--r--drivers/iio/accel/kxcjk-1013.c115
2 files changed, 104 insertions, 15 deletions
diff --git a/drivers/iio/accel/Kconfig b/drivers/iio/accel/Kconfig
index 15de262015df..0be352a7b6f4 100644
--- a/drivers/iio/accel/Kconfig
+++ b/drivers/iio/accel/Kconfig
@@ -219,8 +219,8 @@ config KXCJK1013
219 select IIO_TRIGGERED_BUFFER 219 select IIO_TRIGGERED_BUFFER
220 help 220 help
221 Say Y here if you want to build a driver for the Kionix KXCJK-1013 221 Say Y here if you want to build a driver for the Kionix KXCJK-1013
222 triaxial acceleration sensor. This driver also supports KXCJ9-1008 222 triaxial acceleration sensor. This driver also supports KXCJ9-1008,
223 and KXTJ2-1009. 223 KXTJ2-1009 and KXTF9.
224 224
225 To compile this driver as a module, choose M here: the module will 225 To compile this driver as a module, choose M here: the module will
226 be called kxcjk-1013. 226 be called kxcjk-1013.
diff --git a/drivers/iio/accel/kxcjk-1013.c b/drivers/iio/accel/kxcjk-1013.c
index cc068b6bc114..af53a1084ee5 100644
--- a/drivers/iio/accel/kxcjk-1013.c
+++ b/drivers/iio/accel/kxcjk-1013.c
@@ -34,6 +34,13 @@
34#define KXCJK1013_DRV_NAME "kxcjk1013" 34#define KXCJK1013_DRV_NAME "kxcjk1013"
35#define KXCJK1013_IRQ_NAME "kxcjk1013_event" 35#define KXCJK1013_IRQ_NAME "kxcjk1013_event"
36 36
37#define KXTF9_REG_HP_XOUT_L 0x00
38#define KXTF9_REG_HP_XOUT_H 0x01
39#define KXTF9_REG_HP_YOUT_L 0x02
40#define KXTF9_REG_HP_YOUT_H 0x03
41#define KXTF9_REG_HP_ZOUT_L 0x04
42#define KXTF9_REG_HP_ZOUT_H 0x05
43
37#define KXCJK1013_REG_XOUT_L 0x06 44#define KXCJK1013_REG_XOUT_L 0x06
38/* 45/*
39 * From low byte X axis register, all the other addresses of Y and Z can be 46 * From low byte X axis register, all the other addresses of Y and Z can be
@@ -48,17 +55,33 @@
48 55
49#define KXCJK1013_REG_DCST_RESP 0x0C 56#define KXCJK1013_REG_DCST_RESP 0x0C
50#define KXCJK1013_REG_WHO_AM_I 0x0F 57#define KXCJK1013_REG_WHO_AM_I 0x0F
51#define KXCJK1013_REG_INT_SRC1 0x16 58#define KXTF9_REG_TILT_POS_CUR 0x10
59#define KXTF9_REG_TILT_POS_PREV 0x11
60#define KXTF9_REG_INT_SRC1 0x15
61#define KXCJK1013_REG_INT_SRC1 0x16 /* compatible, but called INT_SRC2 in KXTF9 ds */
52#define KXCJK1013_REG_INT_SRC2 0x17 62#define KXCJK1013_REG_INT_SRC2 0x17
53#define KXCJK1013_REG_STATUS_REG 0x18 63#define KXCJK1013_REG_STATUS_REG 0x18
54#define KXCJK1013_REG_INT_REL 0x1A 64#define KXCJK1013_REG_INT_REL 0x1A
55#define KXCJK1013_REG_CTRL1 0x1B 65#define KXCJK1013_REG_CTRL1 0x1B
56#define KXCJK1013_REG_CTRL2 0x1D 66#define KXTF9_REG_CTRL2 0x1C
67#define KXCJK1013_REG_CTRL2 0x1D /* mostly compatible, CTRL_REG3 in KTXF9 ds */
57#define KXCJK1013_REG_INT_CTRL1 0x1E 68#define KXCJK1013_REG_INT_CTRL1 0x1E
58#define KXCJK1013_REG_INT_CTRL2 0x1F 69#define KXCJK1013_REG_INT_CTRL2 0x1F
70#define KXTF9_REG_INT_CTRL3 0x20
59#define KXCJK1013_REG_DATA_CTRL 0x21 71#define KXCJK1013_REG_DATA_CTRL 0x21
72#define KXTF9_REG_TILT_TIMER 0x28
60#define KXCJK1013_REG_WAKE_TIMER 0x29 73#define KXCJK1013_REG_WAKE_TIMER 0x29
74#define KXTF9_REG_TDT_TIMER 0x2B
75#define KXTF9_REG_TDT_THRESH_H 0x2C
76#define KXTF9_REG_TDT_THRESH_L 0x2D
77#define KXTF9_REG_TDT_TAP_TIMER 0x2E
78#define KXTF9_REG_TDT_TOTAL_TIMER 0x2F
79#define KXTF9_REG_TDT_LATENCY_TIMER 0x30
80#define KXTF9_REG_TDT_WINDOW_TIMER 0x31
61#define KXCJK1013_REG_SELF_TEST 0x3A 81#define KXCJK1013_REG_SELF_TEST 0x3A
82#define KXTF9_REG_WAKE_THRESH 0x5A
83#define KXTF9_REG_TILT_ANGLE 0x5C
84#define KXTF9_REG_HYST_SET 0x5F
62#define KXCJK1013_REG_WAKE_THRES 0x6A 85#define KXCJK1013_REG_WAKE_THRES 0x6A
63 86
64#define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7) 87#define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7)
@@ -68,18 +91,32 @@
68#define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3) 91#define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3)
69#define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1) 92#define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1)
70 93
94#define KXCJK1013_REG_INT_CTRL1_BIT_IEU BIT(2) /* KXTF9 */
71#define KXCJK1013_REG_INT_CTRL1_BIT_IEL BIT(3) 95#define KXCJK1013_REG_INT_CTRL1_BIT_IEL BIT(3)
72#define KXCJK1013_REG_INT_CTRL1_BIT_IEA BIT(4) 96#define KXCJK1013_REG_INT_CTRL1_BIT_IEA BIT(4)
73#define KXCJK1013_REG_INT_CTRL1_BIT_IEN BIT(5) 97#define KXCJK1013_REG_INT_CTRL1_BIT_IEN BIT(5)
74 98
99#define KXTF9_REG_TILT_BIT_LEFT_EDGE BIT(5)
100#define KXTF9_REG_TILT_BIT_RIGHT_EDGE BIT(4)
101#define KXTF9_REG_TILT_BIT_LOWER_EDGE BIT(3)
102#define KXTF9_REG_TILT_BIT_UPPER_EDGE BIT(2)
103#define KXTF9_REG_TILT_BIT_FACE_DOWN BIT(1)
104#define KXTF9_REG_TILT_BIT_FACE_UP BIT(0)
105
75#define KXCJK1013_DATA_MASK_12_BIT 0x0FFF 106#define KXCJK1013_DATA_MASK_12_BIT 0x0FFF
76#define KXCJK1013_MAX_STARTUP_TIME_US 100000 107#define KXCJK1013_MAX_STARTUP_TIME_US 100000
77 108
78#define KXCJK1013_SLEEP_DELAY_MS 2000 109#define KXCJK1013_SLEEP_DELAY_MS 2000
79 110
111#define KXCJK1013_REG_INT_SRC1_BIT_TPS BIT(0) /* KXTF9 */
80#define KXCJK1013_REG_INT_SRC1_BIT_WUFS BIT(1) 112#define KXCJK1013_REG_INT_SRC1_BIT_WUFS BIT(1)
113#define KXCJK1013_REG_INT_SRC1_MASK_TDTS (BIT(2) | BIT(3)) /* KXTF9 */
114#define KXCJK1013_REG_INT_SRC1_TAP_NONE 0
115#define KXCJK1013_REG_INT_SRC1_TAP_SINGLE BIT(2)
116#define KXCJK1013_REG_INT_SRC1_TAP_DOUBLE BIT(3)
81#define KXCJK1013_REG_INT_SRC1_BIT_DRDY BIT(4) 117#define KXCJK1013_REG_INT_SRC1_BIT_DRDY BIT(4)
82 118
119/* KXCJK: INT_SOURCE2: motion detect, KXTF9: INT_SRC_REG1: tap detect */
83#define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0) 120#define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0)
84#define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1) 121#define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1)
85#define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2) 122#define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2)
@@ -93,6 +130,7 @@ enum kx_chipset {
93 KXCJK1013, 130 KXCJK1013,
94 KXCJ91008, 131 KXCJ91008,
95 KXTJ21009, 132 KXTJ21009,
133 KXTF9,
96 KX_MAX_CHIPS /* this must be last */ 134 KX_MAX_CHIPS /* this must be last */
97}; 135};
98 136
@@ -158,6 +196,18 @@ static const struct kx_odr_map samp_freq_table[] = {
158static const char *const kxcjk1013_samp_freq_avail = 196static const char *const kxcjk1013_samp_freq_avail =
159 "0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600"; 197 "0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600";
160 198
199static const struct kx_odr_map kxtf9_samp_freq_table[] = {
200 { 25, 0, 0x01, 0x00 },
201 { 50, 0, 0x02, 0x01 },
202 { 100, 0, 0x03, 0x01 },
203 { 200, 0, 0x04, 0x01 },
204 { 400, 0, 0x05, 0x01 },
205 { 800, 0, 0x06, 0x01 },
206};
207
208static const char *const kxtf9_samp_freq_avail =
209 "25 50 100 200 400 800";
210
161/* Refer to section 4 of the specification */ 211/* Refer to section 4 of the specification */
162static const struct { 212static const struct {
163 int odr_bits; 213 int odr_bits;
@@ -208,6 +258,15 @@ static const struct {
208 {0x06, 3000}, 258 {0x06, 3000},
209 {0x07, 2000}, 259 {0x07, 2000},
210 }, 260 },
261 /* KXTF9 */
262 {
263 {0x01, 81000},
264 {0x02, 41000},
265 {0x03, 21000},
266 {0x04, 11000},
267 {0x05, 5100},
268 {0x06, 2700},
269 },
211}; 270};
212 271
213static const struct { 272static const struct {
@@ -404,7 +463,7 @@ static int kxcjk1013_set_power_state(struct kxcjk1013_data *data, bool on)
404 463
405static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data) 464static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data)
406{ 465{
407 int ret; 466 int waketh_reg, ret;
408 467
409 ret = i2c_smbus_write_byte_data(data->client, 468 ret = i2c_smbus_write_byte_data(data->client,
410 KXCJK1013_REG_WAKE_TIMER, 469 KXCJK1013_REG_WAKE_TIMER,
@@ -415,8 +474,9 @@ static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data)
415 return ret; 474 return ret;
416 } 475 }
417 476
418 ret = i2c_smbus_write_byte_data(data->client, 477 waketh_reg = data->chipset == KXTF9 ?
419 KXCJK1013_REG_WAKE_THRES, 478 KXTF9_REG_WAKE_THRESH : KXCJK1013_REG_WAKE_THRES;
479 ret = i2c_smbus_write_byte_data(data->client, waketh_reg,
420 data->wake_thres); 480 data->wake_thres);
421 if (ret < 0) { 481 if (ret < 0) {
422 dev_err(&data->client->dev, "Error writing reg_wake_thres\n"); 482 dev_err(&data->client->dev, "Error writing reg_wake_thres\n");
@@ -590,9 +650,14 @@ static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
590 if (ret < 0) 650 if (ret < 0)
591 return ret; 651 return ret;
592 652
593 odr_setting = kxcjk1013_find_odr_value(samp_freq_table, 653 if (data->chipset == KXTF9)
594 ARRAY_SIZE(samp_freq_table), 654 odr_setting = kxcjk1013_find_odr_value(kxtf9_samp_freq_table,
595 val, val2); 655 ARRAY_SIZE(kxtf9_samp_freq_table),
656 val, val2);
657 else
658 odr_setting = kxcjk1013_find_odr_value(samp_freq_table,
659 ARRAY_SIZE(samp_freq_table),
660 val, val2);
596 661
597 if (IS_ERR(odr_setting)) 662 if (IS_ERR(odr_setting))
598 return PTR_ERR(odr_setting); 663 return PTR_ERR(odr_setting);
@@ -629,9 +694,14 @@ static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
629 694
630static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2) 695static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2)
631{ 696{
632 return kxcjk1013_convert_odr_value(samp_freq_table, 697 if (data->chipset == KXTF9)
633 ARRAY_SIZE(samp_freq_table), 698 return kxcjk1013_convert_odr_value(kxtf9_samp_freq_table,
634 data->odr_bits, val, val2); 699 ARRAY_SIZE(kxtf9_samp_freq_table),
700 data->odr_bits, val, val2);
701 else
702 return kxcjk1013_convert_odr_value(samp_freq_table,
703 ARRAY_SIZE(samp_freq_table),
704 data->odr_bits, val, val2);
635} 705}
636 706
637static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis) 707static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis)
@@ -886,7 +956,16 @@ static ssize_t kxcjk1013_get_samp_freq_avail(struct device *dev,
886 struct device_attribute *attr, 956 struct device_attribute *attr,
887 char *buf) 957 char *buf)
888{ 958{
889 return sprintf(buf, "%s\n", kxcjk1013_samp_freq_avail); 959 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
960 struct kxcjk1013_data *data = iio_priv(indio_dev);
961 const char *str;
962
963 if (data->chipset == KXTF9)
964 str = kxtf9_samp_freq_avail;
965 else
966 str = kxcjk1013_samp_freq_avail;
967
968 return sprintf(buf, "%s\n", str);
890} 969}
891 970
892static IIO_DEVICE_ATTR(in_accel_sampling_frequency_available, S_IRUGO, 971static IIO_DEVICE_ATTR(in_accel_sampling_frequency_available, S_IRUGO,
@@ -1119,7 +1198,16 @@ static irqreturn_t kxcjk1013_event_handler(int irq, void *private)
1119 } 1198 }
1120 1199
1121 if (ret & KXCJK1013_REG_INT_SRC1_BIT_WUFS) { 1200 if (ret & KXCJK1013_REG_INT_SRC1_BIT_WUFS) {
1122 kxcjk1013_report_motion_event(indio_dev); 1201 if (data->chipset == KXTF9)
1202 iio_push_event(indio_dev,
1203 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1204 0,
1205 IIO_MOD_X_AND_Y_AND_Z,
1206 IIO_EV_TYPE_THRESH,
1207 IIO_EV_DIR_RISING),
1208 data->timestamp);
1209 else
1210 kxcjk1013_report_motion_event(indio_dev);
1123 } 1211 }
1124 1212
1125ack_intr: 1213ack_intr:
@@ -1412,6 +1500,7 @@ static const struct i2c_device_id kxcjk1013_id[] = {
1412 {"kxcjk1013", KXCJK1013}, 1500 {"kxcjk1013", KXCJK1013},
1413 {"kxcj91008", KXCJ91008}, 1501 {"kxcj91008", KXCJ91008},
1414 {"kxtj21009", KXTJ21009}, 1502 {"kxtj21009", KXTJ21009},
1503 {"kxtf9", KXTF9},
1415 {"SMO8500", KXCJ91008}, 1504 {"SMO8500", KXCJ91008},
1416 {} 1505 {}
1417}; 1506};