diff options
author | Bitan Biswas <bbiswas@nvidia.com> | 2019-06-11 06:51:10 -0400 |
---|---|---|
committer | Wolfram Sang <wsa@the-dreams.de> | 2019-06-12 06:20:12 -0400 |
commit | 26955a7bbfca698b024e1ff750b2d8e3d3f74118 (patch) | |
tree | 1b2e65bc41f8a8650c53cf3fd645e580664a1d53 /drivers/i2c/busses | |
parent | 233d0ab6ffdc1a1ada5d393c1b6ba55dbc669764 (diff) |
i2c: tegra: fix alignment and spacing violations
Fix checkpatch.pl alignment and blank line check(s) in i2c-tegra.c
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'drivers/i2c/busses')
-rw-r--r-- | drivers/i2c/busses/i2c-tegra.c | 35 |
1 files changed, 19 insertions, 16 deletions
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index c3de6d0d8d19..343b09a109b3 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c | |||
@@ -295,7 +295,7 @@ static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) | |||
295 | * to the I2C block inside the DVC block | 295 | * to the I2C block inside the DVC block |
296 | */ | 296 | */ |
297 | static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, | 297 | static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, |
298 | unsigned long reg) | 298 | unsigned long reg) |
299 | { | 299 | { |
300 | if (i2c_dev->is_dvc) | 300 | if (i2c_dev->is_dvc) |
301 | reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; | 301 | reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; |
@@ -303,7 +303,7 @@ static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, | |||
303 | } | 303 | } |
304 | 304 | ||
305 | static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, | 305 | static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, |
306 | unsigned long reg) | 306 | unsigned long reg) |
307 | { | 307 | { |
308 | writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); | 308 | writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); |
309 | 309 | ||
@@ -318,13 +318,13 @@ static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) | |||
318 | } | 318 | } |
319 | 319 | ||
320 | static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, | 320 | static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, |
321 | unsigned long reg, int len) | 321 | unsigned long reg, int len) |
322 | { | 322 | { |
323 | writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); | 323 | writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); |
324 | } | 324 | } |
325 | 325 | ||
326 | static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, | 326 | static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, |
327 | unsigned long reg, int len) | 327 | unsigned long reg, int len) |
328 | { | 328 | { |
329 | readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); | 329 | readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); |
330 | } | 330 | } |
@@ -669,10 +669,11 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) | |||
669 | i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); | 669 | i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); |
670 | if (in_interrupt()) | 670 | if (in_interrupt()) |
671 | err = readl_poll_timeout_atomic(addr, val, val == 0, | 671 | err = readl_poll_timeout_atomic(addr, val, val == 0, |
672 | 1000, I2C_CONFIG_LOAD_TIMEOUT); | 672 | 1000, |
673 | I2C_CONFIG_LOAD_TIMEOUT); | ||
673 | else | 674 | else |
674 | err = readl_poll_timeout(addr, val, val == 0, | 675 | err = readl_poll_timeout(addr, val, val == 0, 1000, |
675 | 1000, I2C_CONFIG_LOAD_TIMEOUT); | 676 | I2C_CONFIG_LOAD_TIMEOUT); |
676 | 677 | ||
677 | if (err) { | 678 | if (err) { |
678 | dev_warn(i2c_dev->dev, | 679 | dev_warn(i2c_dev->dev, |
@@ -1013,7 +1014,8 @@ static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) | |||
1013 | } | 1014 | } |
1014 | 1015 | ||
1015 | static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, | 1016 | static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, |
1016 | struct i2c_msg *msg, enum msg_end_type end_state) | 1017 | struct i2c_msg *msg, |
1018 | enum msg_end_type end_state) | ||
1017 | { | 1019 | { |
1018 | u32 packet_header; | 1020 | u32 packet_header; |
1019 | u32 int_mask; | 1021 | u32 int_mask; |
@@ -1150,9 +1152,8 @@ unlock: | |||
1150 | if (err) | 1152 | if (err) |
1151 | return err; | 1153 | return err; |
1152 | 1154 | ||
1153 | time_left = wait_for_completion_timeout( | 1155 | time_left = wait_for_completion_timeout(&i2c_dev->dma_complete, |
1154 | &i2c_dev->dma_complete, | 1156 | msecs_to_jiffies(xfer_time)); |
1155 | msecs_to_jiffies(xfer_time)); | ||
1156 | if (time_left == 0) { | 1157 | if (time_left == 0) { |
1157 | dev_err(i2c_dev->dev, "DMA transfer timeout\n"); | 1158 | dev_err(i2c_dev->dev, "DMA transfer timeout\n"); |
1158 | dmaengine_terminate_sync(i2c_dev->msg_read ? | 1159 | dmaengine_terminate_sync(i2c_dev->msg_read ? |
@@ -1214,7 +1215,7 @@ unlock: | |||
1214 | } | 1215 | } |
1215 | 1216 | ||
1216 | static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], | 1217 | static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], |
1217 | int num) | 1218 | int num) |
1218 | { | 1219 | { |
1219 | struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); | 1220 | struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); |
1220 | int i; | 1221 | int i; |
@@ -1260,14 +1261,15 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) | |||
1260 | { | 1261 | { |
1261 | struct device_node *np = i2c_dev->dev->of_node; | 1262 | struct device_node *np = i2c_dev->dev->of_node; |
1262 | int ret; | 1263 | int ret; |
1264 | bool multi_mode; | ||
1263 | 1265 | ||
1264 | ret = of_property_read_u32(np, "clock-frequency", | 1266 | ret = of_property_read_u32(np, "clock-frequency", |
1265 | &i2c_dev->bus_clk_rate); | 1267 | &i2c_dev->bus_clk_rate); |
1266 | if (ret) | 1268 | if (ret) |
1267 | i2c_dev->bus_clk_rate = 100000; /* default clock rate */ | 1269 | i2c_dev->bus_clk_rate = 100000; /* default clock rate */ |
1268 | 1270 | ||
1269 | i2c_dev->is_multimaster_mode = of_property_read_bool(np, | 1271 | multi_mode = of_property_read_bool(np, "multi-master"); |
1270 | "multi-master"); | 1272 | i2c_dev->is_multimaster_mode = multi_mode; |
1271 | } | 1273 | } |
1272 | 1274 | ||
1273 | static const struct i2c_algorithm tegra_i2c_algo = { | 1275 | static const struct i2c_algorithm tegra_i2c_algo = { |
@@ -1611,7 +1613,7 @@ static int tegra_i2c_probe(struct platform_device *pdev) | |||
1611 | } | 1613 | } |
1612 | 1614 | ||
1613 | ret = devm_request_irq(&pdev->dev, i2c_dev->irq, | 1615 | ret = devm_request_irq(&pdev->dev, i2c_dev->irq, |
1614 | tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); | 1616 | tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); |
1615 | if (ret) { | 1617 | if (ret) { |
1616 | dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); | 1618 | dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); |
1617 | goto release_dma; | 1619 | goto release_dma; |
@@ -1680,6 +1682,7 @@ static const struct dev_pm_ops tegra_i2c_pm = { | |||
1680 | SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, | 1682 | SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, |
1681 | NULL) | 1683 | NULL) |
1682 | }; | 1684 | }; |
1685 | |||
1683 | #define TEGRA_I2C_PM (&tegra_i2c_pm) | 1686 | #define TEGRA_I2C_PM (&tegra_i2c_pm) |
1684 | #else | 1687 | #else |
1685 | #define TEGRA_I2C_PM NULL | 1688 | #define TEGRA_I2C_PM NULL |