drm/amdgpu/gfx9: use reset default for PA_SC_FIFO_SIZE

Recommended by the hw team.

Reviewed-and-Tested-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

1 files changed, 0 insertions, 19 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index b610e3b30d95..2f18c64d531f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1959,25 +1959,6 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
         mutex_unlock(&adev->srbm_mutex);
 
         gfx_v9_0_init_compute_vmid(adev);
-
-        mutex_lock(&adev->grbm_idx_mutex);
-        /*
-         * making sure that the following register writes will be broadcasted
-         * to all the shaders
-         */
-        gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
-
-        WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
-                   (adev->gfx.config.sc_prim_fifo_size_frontend <<
-                        PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
-                   (adev->gfx.config.sc_prim_fifo_size_backend <<
-                        PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
-                   (adev->gfx.config.sc_hiz_tile_fifo_size <<
-                        PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
-                   (adev->gfx.config.sc_earlyz_tile_fifo_size <<
-                        PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
-        mutex_unlock(&adev->grbm_idx_mutex);
-
 }
 
 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)