Merge branch 'drm-fixes-4.6' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

some misc radeon fixes.

* 'drm-fixes-4.6' of git://people.freedesktop.org/~agd5f/linux:
  drm/amd/amdgpu: fix irq domain remove for tonga ih
  drm/radeon: use helper for mst connector dpms.
  drm/radeon/mst: port some MST setup code from DAL.
  drm/amdgpu: add invisible pin size statistic

6 files changed, 33 insertions, 17 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 62a778012fe0..b77489dec6e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -2034,6 +2034,7 @@ struct amdgpu_device {
 
         /* tracking pinned memory */
         u64 vram_pin_size;
+        u64 invisible_pin_size;
         u64 gart_pin_size;
 
         /* amdkfd interface */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 598eb0cd5aab..aef70db16832 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -384,7 +384,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                 vram_gtt.vram_size = adev->mc.real_vram_size;
                 vram_gtt.vram_size -= adev->vram_pin_size;
                 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
-                vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size;
+                vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
                 vram_gtt.gtt_size  = adev->mc.gtt_size;
                 vram_gtt.gtt_size -= adev->gart_pin_size;
                 return copy_to_user(out, &vram_gtt,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5b6639faa731..e557fc1f17c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -424,9 +424,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
                 bo->pin_count = 1;
                 if (gpu_addr != NULL)
                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
-                if (domain == AMDGPU_GEM_DOMAIN_VRAM)
+                if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
                         bo->adev->vram_pin_size += amdgpu_bo_size(bo);
-                else
+                        if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
+                                bo->adev->invisible_pin_size += amdgpu_bo_size(bo);
+                } else
                         bo->adev->gart_pin_size += amdgpu_bo_size(bo);
         } else {
                 dev_err(bo->adev->dev, "%p pin failed\n", bo);
@@ -456,9 +458,11 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
         }
         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
         if (likely(r == 0)) {
-                if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
+                if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
                         bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
-                else
+                        if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
+                                bo->adev->invisible_pin_size -= amdgpu_bo_size(bo);
+                } else
                         bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
         } else {
                 dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index b6f7d7bff929..0f14199cf716 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -307,7 +307,7 @@ static int tonga_ih_sw_fini(void *handle)
 
         amdgpu_irq_fini(adev);
         amdgpu_ih_ring_fini(adev);
-        amdgpu_irq_add_domain(adev);
+        amdgpu_irq_remove_domain(adev);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/radeon/ni_reg.h b/drivers/gpu/drm/radeon/ni_reg.h
index da310a70c0f0..827ccc87cbc3 100644
--- a/drivers/gpu/drm/radeon/ni_reg.h
+++ b/drivers/gpu/drm/radeon/ni_reg.h
@@ -109,6 +109,8 @@
 #define NI_DP_MSE_SAT2                                 0x7398
 
 #define NI_DP_MSE_SAT_UPDATE                           0x739c
+#       define NI_DP_MSE_SAT_UPDATE_MASK               0x3
+#       define NI_DP_MSE_16_MTP_KEEPOUT                0x100
 
 #define NI_DIG_BE_CNTL                                 0x7140
 #       define NI_DIG_FE_SOURCE_SELECT(x)              (((x) & 0x7f) << 8)
diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c
index 43cffb526b0c..de504ea29c06 100644
--- a/drivers/gpu/drm/radeon/radeon_dp_mst.c
+++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c
@@ -89,8 +89,16 @@ static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
         WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
 
         do {
+                unsigned value1, value2;
+                udelay(10);
                 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
-        } while ((temp & 0x1) && retries++ < 10000);
+
+                value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
+                value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
+
+                if (!value1 && !value2)
+                        break;
+        } while (retries++ < 50);
 
         if (retries == 10000)
                 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
@@ -150,7 +158,7 @@ static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn
         return 0;
 }
 
-static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, uint32_t y)
+static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
 {
         struct drm_device *dev = mst->base.dev;
         struct radeon_device *rdev = dev->dev_private;
@@ -158,6 +166,8 @@ static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, ui
         uint32_t val, temp;
         uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
         int retries = 0;
+        uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
+        uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
 
         val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
 
@@ -165,6 +175,7 @@ static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, ui
 
         do {
                 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
+                udelay(10);
         } while ((temp & 0x1) && (retries++ < 10000));
 
         if (retries >= 10000)
@@ -246,14 +257,8 @@ radeon_dp_mst_connector_destroy(struct drm_connector *connector)
         kfree(radeon_connector);
 }
 
-static int radeon_connector_dpms(struct drm_connector *connector, int mode)
-{
-        DRM_DEBUG_KMS("\n");
-        return 0;
-}
-
 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
-        .dpms = radeon_connector_dpms,
+        .dpms = drm_helper_connector_dpms,
         .detect = radeon_dp_mst_detect,
         .fill_modes = drm_helper_probe_single_connector_modes,
         .destroy = radeon_dp_mst_connector_destroy,
@@ -394,7 +399,7 @@ radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
         struct drm_crtc *crtc;
         struct radeon_crtc *radeon_crtc;
         int ret, slots;
-
+        s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
         if (!ASIC_IS_DCE5(rdev)) {
                 DRM_ERROR("got mst dpms on non-DCE5\n");
                 return;
@@ -456,7 +461,11 @@ radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
 
                 mst_enc->enc_active = true;
                 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
-                radeon_dp_mst_set_vcp_size(radeon_encoder, slots, 0);
+
+                fixed_pbn = drm_int2fixp(mst_enc->pbn);
+                fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
+                avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
+                radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
 
                 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
                                             mst_enc->fe);