Merge branch 'drm-next-4.11' of git://people.freedesktop.org/~agd5f/linux into drm-next

Some ttm/amd fixes.

* 'drm-next-4.11' of git://people.freedesktop.org/~agd5f/linux:
  drm/amd/powerplay: fix PSI feature on Polars12.
  drm/amdgpu: refuse to reserve io mem for split VRAM buffers
  drm/ttm: fix use-after-free races in vm fault handling
  drm/amd/amdgpu: post card if there is real hw resetting performed

12 files changed, 71 insertions, 13 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e9af03113fc3..c1b913541739 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1482,6 +1482,9 @@ struct amdgpu_device {
         spinlock_t                      gtt_list_lock;
         struct list_head                gtt_list;
 
+        /* record hw reset is performed */
+        bool has_hw_reset;
+
 };
 
 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
@@ -1700,7 +1703,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 int amdgpu_gpu_reset(struct amdgpu_device *adev);
 bool amdgpu_need_backup(struct amdgpu_device *adev);
 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
-bool amdgpu_card_posted(struct amdgpu_device *adev);
+bool amdgpu_need_post(struct amdgpu_device *adev);
 void amdgpu_update_display_priority(struct amdgpu_device *adev);
 
 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index d9def01f276e..821f7cc2051f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -100,7 +100,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
         resource_size_t size = 256 * 1024; /* ??? */
 
         if (!(adev->flags & AMD_IS_APU))
-                if (!amdgpu_card_posted(adev))
+                if (amdgpu_need_post(adev))
                         return false;
 
         adev->bios = NULL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 944ba0d3874a..6abb238b25c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -619,25 +619,29 @@ void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
  * GPU helpers function.
  */
 /**
- * amdgpu_card_posted - check if the hw has already been initialized
+ * amdgpu_need_post - check if the hw need post or not
  *
  * @adev: amdgpu_device pointer
  *
- * Check if the asic has been initialized (all asics).
- * Used at driver startup.
- * Returns true if initialized or false if not.
+ * Check if the asic has been initialized (all asics) at driver startup
+ * or post is needed if  hw reset is performed.
+ * Returns true if need or false if not.
  */
-bool amdgpu_card_posted(struct amdgpu_device *adev)
+bool amdgpu_need_post(struct amdgpu_device *adev)
 {
         uint32_t reg;
 
+        if (adev->has_hw_reset) {
+                adev->has_hw_reset = false;
+                return true;
+        }
         /* then check MEM_SIZE, in case the crtcs are off */
         reg = RREG32(mmCONFIG_MEMSIZE);
 
         if (reg)
-                return true;
+                return false;
 
-        return false;
+        return true;
 
 }
 
@@ -665,7 +669,7 @@ static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
                                 return true;
                 }
         }
-        return !amdgpu_card_posted(adev);
+        return amdgpu_need_post(adev);
 }
 
 /**
@@ -2071,7 +2075,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
         amdgpu_atombios_scratch_regs_restore(adev);
 
         /* post card */
-        if (!amdgpu_card_posted(adev) || !resume) {
+        if (amdgpu_need_post(adev)) {
                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
                 if (r)
                         DRM_ERROR("amdgpu asic init failed\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 1154b0a8881d..4c6094eefc51 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -529,6 +529,9 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_
         case TTM_PL_TT:
                 break;
         case TTM_PL_VRAM:
+                if (mem->start == AMDGPU_BO_INVALID_OFFSET)
+                        return -EINVAL;
+
                 mem->bus.offset = mem->start << PAGE_SHIFT;
                 /* check if it's visible */
                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 7c39b538dc0e..c4d4b35e54ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1176,6 +1176,7 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)
                 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
                         /* enable BM */
                         pci_set_master(adev->pdev);
+                        adev->has_hw_reset = true;
                         r = 0;
                         break;
                 }
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 4922fff08c3c..50bdb24ef8d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -721,6 +721,7 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
                 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
                         /* enable BM */
                         pci_set_master(adev->pdev);
+                        adev->has_hw_reset = true;
                         return 0;
                 }
                 udelay(1);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
index 4b0a94cc995e..953e0c9ad7cd 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
@@ -1396,3 +1396,25 @@ int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
 
         return 0;
 }
+
+int  atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
+                                uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,
+                                uint16_t *load_line)
+{
+        ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
+                (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device);
+
+        const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;
+
+        PP_ASSERT_WITH_CODE((NULL != voltage_info),
+                        "Could not find Voltage Table in BIOS.", return -EINVAL);
+
+        voltage_object = atomctrl_lookup_voltage_type_v3
+                (voltage_info, voltage_type,  VOLTAGE_OBJ_SVID2);
+
+        *svd_gpio_id = voltage_object->asSVID2Obj.ucSVDGpioId;
+        *svc_gpio_id = voltage_object->asSVID2Obj.ucSVCGpioId;
+        *load_line = voltage_object->asSVID2Obj.usLoadLine_PSI;
+
+        return 0;
+}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
index fc898afce002..e9fe2e84006b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
@@ -311,5 +311,8 @@ extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_a
 
 extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param);
 
+extern int  atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
+                                uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,
+                                uint16_t *load_line);
 #endif
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index b1de9e8ccdbc..f75ee33ec5bb 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -1383,6 +1383,15 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
         data->force_pcie_gen = PP_PCIEGenInvalid;
         data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
 
+        if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->smumgr->is_kicker) {
+                uint8_t tmp1, tmp2;
+                uint16_t tmp3 = 0;
+                atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
+                                                &tmp3);
+                tmp3 = (tmp3 >> 5) & 0x3;
+                data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
+        }
+
         data->fast_watermark_threshold = 100;
         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index 27e7f76ad8a6..f221e17b67e7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -268,7 +268,7 @@ struct smu7_hwmgr {
         uint32_t                       fast_watermark_threshold;
 
         /* ---- Phase Shedding ---- */
-        bool                           vddc_phase_shed_control;
+        uint8_t                           vddc_phase_shed_control;
 
         /* ---- DI/DT ---- */
         struct smu7_display_timing        display_timing;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
index c6c3c5751ac7..80e2329a1b9e 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
@@ -503,7 +503,7 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
         state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 
-        if (smumgr->is_kicker)
+        if (smumgr->chip_id == CHIP_POLARIS12 || smumgr->is_kicker)
                 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
         else
                 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
index 68ef993ab431..88169141bef5 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
@@ -66,8 +66,11 @@ static int ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo,
                 if (vmf->flags & FAULT_FLAG_RETRY_NOWAIT)
                         goto out_unlock;
 
+                ttm_bo_reference(bo);
                 up_read(&vma->vm_mm->mmap_sem);
                 (void) dma_fence_wait(bo->moving, true);
+                ttm_bo_unreserve(bo);
+                ttm_bo_unref(&bo);
                 goto out_unlock;
         }
 
@@ -120,8 +123,10 @@ static int ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 
                 if (vmf->flags & FAULT_FLAG_ALLOW_RETRY) {
                         if (!(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) {
+                                ttm_bo_reference(bo);
                                 up_read(&vma->vm_mm->mmap_sem);
                                 (void) ttm_bo_wait_unreserved(bo);
+                                ttm_bo_unref(&bo);
                         }
 
                         return VM_FAULT_RETRY;
@@ -166,6 +171,13 @@ static int ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
         ret = ttm_bo_vm_fault_idle(bo, vma, vmf);
         if (unlikely(ret != 0)) {
                 retval = ret;
+
+                if (retval == VM_FAULT_RETRY &&
+                    !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) {
+                        /* The BO has already been unreserved. */
+                        return retval;
+                }
+
                 goto out_unlock;
         }