diff options
author | Philipp Zabel <p.zabel@pengutronix.de> | 2013-09-17 09:48:46 -0400 |
---|---|---|
committer | Philipp Zabel <p.zabel@pengutronix.de> | 2016-03-01 02:33:38 -0500 |
commit | 86bdb09f044e1604add914e94d4f472052780ad9 (patch) | |
tree | aa5f9213fefdc4d83774a77240d20181093aa78f /drivers/gpu/ipu-v3 | |
parent | 16450616790af5ef5dda79e3081916af723756da (diff) |
gpu: ipu-v3: ipu-dc: Simplify display controller microcode setup
This cleans up the display controller microcode setup in ipu_dc_init_sync
a little bit. The microcode template words for DI0 and DI1 are properly
separated to avoid a clash when DI1 is active in interlaced mode at the
same time as DI0 in non-interlaced mode.
A comment is added to explain the meaning of the sync counter.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'drivers/gpu/ipu-v3')
-rw-r--r-- | drivers/gpu/ipu-v3/ipu-dc.c | 53 |
1 files changed, 26 insertions, 27 deletions
diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c index d3ad5347342c..2f29780e7c68 100644 --- a/drivers/gpu/ipu-v3/ipu-dc.c +++ b/drivers/gpu/ipu-v3/ipu-dc.c | |||
@@ -171,6 +171,7 @@ int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, | |||
171 | u32 bus_format, u32 width) | 171 | u32 bus_format, u32 width) |
172 | { | 172 | { |
173 | struct ipu_dc_priv *priv = dc->priv; | 173 | struct ipu_dc_priv *priv = dc->priv; |
174 | int addr, sync; | ||
174 | u32 reg = 0; | 175 | u32 reg = 0; |
175 | int map; | 176 | int map; |
176 | 177 | ||
@@ -182,41 +183,39 @@ int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, | |||
182 | return map; | 183 | return map; |
183 | } | 184 | } |
184 | 185 | ||
185 | if (interlaced) { | 186 | /* |
186 | int addr; | 187 | * In interlaced mode we need more counters to create the asymmetric |
187 | 188 | * per-field VSYNC signals. The pixel active signal synchronising DC | |
188 | if (dc->di) | 189 | * to DI moves to signal generator #6 (see ipu-di.c). In progressive |
189 | addr = 1; | 190 | * mode counter #5 is used. |
190 | else | 191 | */ |
191 | addr = 0; | 192 | sync = interlaced ? 6 : 5; |
193 | |||
194 | /* Reserve 5 microcode template words for each DI */ | ||
195 | if (dc->di) | ||
196 | addr = 5; | ||
197 | else | ||
198 | addr = 0; | ||
192 | 199 | ||
200 | if (interlaced) { | ||
193 | dc_link_event(dc, DC_EVT_NL, addr, 3); | 201 | dc_link_event(dc, DC_EVT_NL, addr, 3); |
194 | dc_link_event(dc, DC_EVT_EOL, addr, 2); | 202 | dc_link_event(dc, DC_EVT_EOL, addr, 2); |
195 | dc_link_event(dc, DC_EVT_NEW_DATA, addr, 1); | 203 | dc_link_event(dc, DC_EVT_NEW_DATA, addr, 1); |
196 | 204 | ||
197 | /* Init template microcode */ | 205 | /* Init template microcode */ |
198 | dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, 6, 1); | 206 | dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1); |
199 | } else { | 207 | } else { |
200 | if (dc->di) { | 208 | dc_link_event(dc, DC_EVT_NL, addr + 2, 3); |
201 | dc_link_event(dc, DC_EVT_NL, 2, 3); | 209 | dc_link_event(dc, DC_EVT_EOL, addr + 3, 2); |
202 | dc_link_event(dc, DC_EVT_EOL, 3, 2); | 210 | dc_link_event(dc, DC_EVT_NEW_DATA, addr + 1, 1); |
203 | dc_link_event(dc, DC_EVT_NEW_DATA, 1, 1); | 211 | |
204 | /* Init template microcode */ | 212 | /* Init template microcode */ |
205 | dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1); | 213 | dc_write_tmpl(dc, addr + 2, WROD(0), 0, map, SYNC_WAVE, 8, sync, 1); |
206 | dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0); | 214 | dc_write_tmpl(dc, addr + 3, WROD(0), 0, map, SYNC_WAVE, 4, sync, 0); |
207 | dc_write_tmpl(dc, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1); | 215 | dc_write_tmpl(dc, addr + 4, WRG, 0, map, NULL_WAVE, 0, 0, 1); |
208 | dc_write_tmpl(dc, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1); | 216 | dc_write_tmpl(dc, addr + 1, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1); |
209 | } else { | ||
210 | dc_link_event(dc, DC_EVT_NL, 5, 3); | ||
211 | dc_link_event(dc, DC_EVT_EOL, 6, 2); | ||
212 | dc_link_event(dc, DC_EVT_NEW_DATA, 8, 1); | ||
213 | /* Init template microcode */ | ||
214 | dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1); | ||
215 | dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0); | ||
216 | dc_write_tmpl(dc, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1); | ||
217 | dc_write_tmpl(dc, 8, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1); | ||
218 | } | ||
219 | } | 217 | } |
218 | |||
220 | dc_link_event(dc, DC_EVT_NF, 0, 0); | 219 | dc_link_event(dc, DC_EVT_NF, 0, 0); |
221 | dc_link_event(dc, DC_EVT_NFIELD, 0, 0); | 220 | dc_link_event(dc, DC_EVT_NFIELD, 0, 0); |
222 | dc_link_event(dc, DC_EVT_EOF, 0, 0); | 221 | dc_link_event(dc, DC_EVT_EOF, 0, 0); |