diff options
author | Linus Walleij <linus.walleij@linaro.org> | 2019-09-03 10:04:19 -0400 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2019-09-03 10:04:19 -0400 |
commit | 8a6abcd04e4cdf6088f11212570c3e5ec36ee5c3 (patch) | |
tree | 21dfb07a1789424d20c2a8f2f8989f8c19ef48b3 /drivers/gpio | |
parent | f6a7053ddcf1c05c443715d627507f0ab9a0b491 (diff) | |
parent | f2ee73147a3f23cc4b032a76b5677b4b8441ba74 (diff) |
Merge tag 'gpio-v5.4-updates-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel
gpio: updates for v5.4
- use a helper variable for &pdev->dev in gpio-em
- tweak the ifdefs in GPIO headers
- fix function links in HTML docs
- remove an unneeded error message from ixp4xx
- use the optional clk_get in gpio-mxc instead of checking the return value
- a couple improvements in pca953x
- allow to build gpio-lpc32xx on non-lpc32xx targets
Diffstat (limited to 'drivers/gpio')
-rw-r--r-- | drivers/gpio/Kconfig | 7 | ||||
-rw-r--r-- | drivers/gpio/Makefile | 2 | ||||
-rw-r--r-- | drivers/gpio/gpio-em.c | 37 | ||||
-rw-r--r-- | drivers/gpio/gpio-ixp4xx.c | 4 | ||||
-rw-r--r-- | drivers/gpio/gpio-lpc32xx.c | 118 | ||||
-rw-r--r-- | drivers/gpio/gpio-mxc.c | 9 | ||||
-rw-r--r-- | drivers/gpio/gpio-pca953x.c | 70 |
7 files changed, 132 insertions, 115 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8137f3e3a108..e193c76948c4 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig | |||
@@ -311,6 +311,13 @@ config GPIO_LPC18XX | |||
311 | Select this option to enable GPIO driver for | 311 | Select this option to enable GPIO driver for |
312 | NXP LPC18XX/43XX devices. | 312 | NXP LPC18XX/43XX devices. |
313 | 313 | ||
314 | config GPIO_LPC32XX | ||
315 | tristate "NXP LPC32XX GPIO support" | ||
316 | depends on OF_GPIO && (ARCH_LPC32XX || COMPILE_TEST) | ||
317 | help | ||
318 | Select this option to enable GPIO driver for | ||
319 | NXP LPC32XX devices. | ||
320 | |||
314 | config GPIO_LYNXPOINT | 321 | config GPIO_LYNXPOINT |
315 | tristate "Intel Lynxpoint GPIO support" | 322 | tristate "Intel Lynxpoint GPIO support" |
316 | depends on ACPI && X86 | 323 | depends on ACPI && X86 |
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 65d74084c9b2..f3e051fb50e6 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile | |||
@@ -73,7 +73,7 @@ obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o | |||
73 | obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o | 73 | obj-$(CONFIG_GPIO_LP873X) += gpio-lp873x.o |
74 | obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o | 74 | obj-$(CONFIG_GPIO_LP87565) += gpio-lp87565.o |
75 | obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o | 75 | obj-$(CONFIG_GPIO_LPC18XX) += gpio-lpc18xx.o |
76 | obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o | 76 | obj-$(CONFIG_GPIO_LPC32XX) += gpio-lpc32xx.o |
77 | obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o | 77 | obj-$(CONFIG_GPIO_LYNXPOINT) += gpio-lynxpoint.o |
78 | obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o | 78 | obj-$(CONFIG_GPIO_MADERA) += gpio-madera.o |
79 | obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o | 79 | obj-$(CONFIG_GPIO_MAX3191X) += gpio-max3191x.o |
diff --git a/drivers/gpio/gpio-em.c b/drivers/gpio/gpio-em.c index a87951293aaa..620f25b7efb4 100644 --- a/drivers/gpio/gpio-em.c +++ b/drivers/gpio/gpio-em.c | |||
@@ -272,11 +272,12 @@ static int em_gio_probe(struct platform_device *pdev) | |||
272 | struct resource *io[2], *irq[2]; | 272 | struct resource *io[2], *irq[2]; |
273 | struct gpio_chip *gpio_chip; | 273 | struct gpio_chip *gpio_chip; |
274 | struct irq_chip *irq_chip; | 274 | struct irq_chip *irq_chip; |
275 | const char *name = dev_name(&pdev->dev); | 275 | struct device *dev = &pdev->dev; |
276 | const char *name = dev_name(dev); | ||
276 | unsigned int ngpios; | 277 | unsigned int ngpios; |
277 | int ret; | 278 | int ret; |
278 | 279 | ||
279 | p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); | 280 | p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); |
280 | if (!p) | 281 | if (!p) |
281 | return -ENOMEM; | 282 | return -ENOMEM; |
282 | 283 | ||
@@ -290,27 +291,27 @@ static int em_gio_probe(struct platform_device *pdev) | |||
290 | irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | 291 | irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1); |
291 | 292 | ||
292 | if (!io[0] || !io[1] || !irq[0] || !irq[1]) { | 293 | if (!io[0] || !io[1] || !irq[0] || !irq[1]) { |
293 | dev_err(&pdev->dev, "missing IRQ or IOMEM\n"); | 294 | dev_err(dev, "missing IRQ or IOMEM\n"); |
294 | return -EINVAL; | 295 | return -EINVAL; |
295 | } | 296 | } |
296 | 297 | ||
297 | p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start, | 298 | p->base0 = devm_ioremap_nocache(dev, io[0]->start, |
298 | resource_size(io[0])); | 299 | resource_size(io[0])); |
299 | if (!p->base0) | 300 | if (!p->base0) |
300 | return -ENOMEM; | 301 | return -ENOMEM; |
301 | 302 | ||
302 | p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start, | 303 | p->base1 = devm_ioremap_nocache(dev, io[1]->start, |
303 | resource_size(io[1])); | 304 | resource_size(io[1])); |
304 | if (!p->base1) | 305 | if (!p->base1) |
305 | return -ENOMEM; | 306 | return -ENOMEM; |
306 | 307 | ||
307 | if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { | 308 | if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) { |
308 | dev_err(&pdev->dev, "Missing ngpios OF property\n"); | 309 | dev_err(dev, "Missing ngpios OF property\n"); |
309 | return -EINVAL; | 310 | return -EINVAL; |
310 | } | 311 | } |
311 | 312 | ||
312 | gpio_chip = &p->gpio_chip; | 313 | gpio_chip = &p->gpio_chip; |
313 | gpio_chip->of_node = pdev->dev.of_node; | 314 | gpio_chip->of_node = dev->of_node; |
314 | gpio_chip->direction_input = em_gio_direction_input; | 315 | gpio_chip->direction_input = em_gio_direction_input; |
315 | gpio_chip->get = em_gio_get; | 316 | gpio_chip->get = em_gio_get; |
316 | gpio_chip->direction_output = em_gio_direction_output; | 317 | gpio_chip->direction_output = em_gio_direction_output; |
@@ -319,7 +320,7 @@ static int em_gio_probe(struct platform_device *pdev) | |||
319 | gpio_chip->request = em_gio_request; | 320 | gpio_chip->request = em_gio_request; |
320 | gpio_chip->free = em_gio_free; | 321 | gpio_chip->free = em_gio_free; |
321 | gpio_chip->label = name; | 322 | gpio_chip->label = name; |
322 | gpio_chip->parent = &pdev->dev; | 323 | gpio_chip->parent = dev; |
323 | gpio_chip->owner = THIS_MODULE; | 324 | gpio_chip->owner = THIS_MODULE; |
324 | gpio_chip->base = -1; | 325 | gpio_chip->base = -1; |
325 | gpio_chip->ngpio = ngpios; | 326 | gpio_chip->ngpio = ngpios; |
@@ -333,33 +334,33 @@ static int em_gio_probe(struct platform_device *pdev) | |||
333 | irq_chip->irq_release_resources = em_gio_irq_relres; | 334 | irq_chip->irq_release_resources = em_gio_irq_relres; |
334 | irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; | 335 | irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; |
335 | 336 | ||
336 | p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, ngpios, 0, | 337 | p->irq_domain = irq_domain_add_simple(dev->of_node, ngpios, 0, |
337 | &em_gio_irq_domain_ops, p); | 338 | &em_gio_irq_domain_ops, p); |
338 | if (!p->irq_domain) { | 339 | if (!p->irq_domain) { |
339 | dev_err(&pdev->dev, "cannot initialize irq domain\n"); | 340 | dev_err(dev, "cannot initialize irq domain\n"); |
340 | return -ENXIO; | 341 | return -ENXIO; |
341 | } | 342 | } |
342 | 343 | ||
343 | ret = devm_add_action_or_reset(&pdev->dev, em_gio_irq_domain_remove, | 344 | ret = devm_add_action_or_reset(dev, em_gio_irq_domain_remove, |
344 | p->irq_domain); | 345 | p->irq_domain); |
345 | if (ret) | 346 | if (ret) |
346 | return ret; | 347 | return ret; |
347 | 348 | ||
348 | if (devm_request_irq(&pdev->dev, irq[0]->start, | 349 | if (devm_request_irq(dev, irq[0]->start, |
349 | em_gio_irq_handler, 0, name, p)) { | 350 | em_gio_irq_handler, 0, name, p)) { |
350 | dev_err(&pdev->dev, "failed to request low IRQ\n"); | 351 | dev_err(dev, "failed to request low IRQ\n"); |
351 | return -ENOENT; | 352 | return -ENOENT; |
352 | } | 353 | } |
353 | 354 | ||
354 | if (devm_request_irq(&pdev->dev, irq[1]->start, | 355 | if (devm_request_irq(dev, irq[1]->start, |
355 | em_gio_irq_handler, 0, name, p)) { | 356 | em_gio_irq_handler, 0, name, p)) { |
356 | dev_err(&pdev->dev, "failed to request high IRQ\n"); | 357 | dev_err(dev, "failed to request high IRQ\n"); |
357 | return -ENOENT; | 358 | return -ENOENT; |
358 | } | 359 | } |
359 | 360 | ||
360 | ret = devm_gpiochip_add_data(&pdev->dev, gpio_chip, p); | 361 | ret = devm_gpiochip_add_data(dev, gpio_chip, p); |
361 | if (ret) { | 362 | if (ret) { |
362 | dev_err(&pdev->dev, "failed to add GPIO controller\n"); | 363 | dev_err(dev, "failed to add GPIO controller\n"); |
363 | return ret; | 364 | return ret; |
364 | } | 365 | } |
365 | 366 | ||
diff --git a/drivers/gpio/gpio-ixp4xx.c b/drivers/gpio/gpio-ixp4xx.c index 1a57e74fdb91..b3b050604e0b 100644 --- a/drivers/gpio/gpio-ixp4xx.c +++ b/drivers/gpio/gpio-ixp4xx.c | |||
@@ -204,10 +204,8 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) | |||
204 | 204 | ||
205 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 205 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
206 | g->base = devm_ioremap_resource(dev, res); | 206 | g->base = devm_ioremap_resource(dev, res); |
207 | if (IS_ERR(g->base)) { | 207 | if (IS_ERR(g->base)) |
208 | dev_err(dev, "ioremap error\n"); | ||
209 | return PTR_ERR(g->base); | 208 | return PTR_ERR(g->base); |
210 | } | ||
211 | 209 | ||
212 | /* | 210 | /* |
213 | * When we convert to device tree we will simply look up the | 211 | * When we convert to device tree we will simply look up the |
diff --git a/drivers/gpio/gpio-lpc32xx.c b/drivers/gpio/gpio-lpc32xx.c index 24885b3db3d5..4e626c4235c2 100644 --- a/drivers/gpio/gpio-lpc32xx.c +++ b/drivers/gpio/gpio-lpc32xx.c | |||
@@ -16,36 +16,33 @@ | |||
16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
17 | #include <linux/module.h> | 17 | #include <linux/module.h> |
18 | 18 | ||
19 | #include <mach/hardware.h> | 19 | #define LPC32XX_GPIO_P3_INP_STATE (0x000) |
20 | #include <mach/platform.h> | 20 | #define LPC32XX_GPIO_P3_OUTP_SET (0x004) |
21 | 21 | #define LPC32XX_GPIO_P3_OUTP_CLR (0x008) | |
22 | #define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000) | 22 | #define LPC32XX_GPIO_P3_OUTP_STATE (0x00C) |
23 | #define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004) | 23 | #define LPC32XX_GPIO_P2_DIR_SET (0x010) |
24 | #define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008) | 24 | #define LPC32XX_GPIO_P2_DIR_CLR (0x014) |
25 | #define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C) | 25 | #define LPC32XX_GPIO_P2_DIR_STATE (0x018) |
26 | #define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010) | 26 | #define LPC32XX_GPIO_P2_INP_STATE (0x01C) |
27 | #define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014) | 27 | #define LPC32XX_GPIO_P2_OUTP_SET (0x020) |
28 | #define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018) | 28 | #define LPC32XX_GPIO_P2_OUTP_CLR (0x024) |
29 | #define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C) | 29 | #define LPC32XX_GPIO_P2_MUX_SET (0x028) |
30 | #define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020) | 30 | #define LPC32XX_GPIO_P2_MUX_CLR (0x02C) |
31 | #define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024) | 31 | #define LPC32XX_GPIO_P2_MUX_STATE (0x030) |
32 | #define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) | 32 | #define LPC32XX_GPIO_P0_INP_STATE (0x040) |
33 | #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) | 33 | #define LPC32XX_GPIO_P0_OUTP_SET (0x044) |
34 | #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) | 34 | #define LPC32XX_GPIO_P0_OUTP_CLR (0x048) |
35 | #define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040) | 35 | #define LPC32XX_GPIO_P0_OUTP_STATE (0x04C) |
36 | #define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044) | 36 | #define LPC32XX_GPIO_P0_DIR_SET (0x050) |
37 | #define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048) | 37 | #define LPC32XX_GPIO_P0_DIR_CLR (0x054) |
38 | #define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C) | 38 | #define LPC32XX_GPIO_P0_DIR_STATE (0x058) |
39 | #define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050) | 39 | #define LPC32XX_GPIO_P1_INP_STATE (0x060) |
40 | #define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054) | 40 | #define LPC32XX_GPIO_P1_OUTP_SET (0x064) |
41 | #define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058) | 41 | #define LPC32XX_GPIO_P1_OUTP_CLR (0x068) |
42 | #define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060) | 42 | #define LPC32XX_GPIO_P1_OUTP_STATE (0x06C) |
43 | #define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064) | 43 | #define LPC32XX_GPIO_P1_DIR_SET (0x070) |
44 | #define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068) | 44 | #define LPC32XX_GPIO_P1_DIR_CLR (0x074) |
45 | #define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C) | 45 | #define LPC32XX_GPIO_P1_DIR_STATE (0x078) |
46 | #define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070) | ||
47 | #define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074) | ||
48 | #define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078) | ||
49 | 46 | ||
50 | #define GPIO012_PIN_TO_BIT(x) (1 << (x)) | 47 | #define GPIO012_PIN_TO_BIT(x) (1 << (x)) |
51 | #define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25)) | 48 | #define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25)) |
@@ -72,12 +69,12 @@ | |||
72 | #define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX) | 69 | #define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX) |
73 | 70 | ||
74 | struct gpio_regs { | 71 | struct gpio_regs { |
75 | void __iomem *inp_state; | 72 | unsigned long inp_state; |
76 | void __iomem *outp_state; | 73 | unsigned long outp_state; |
77 | void __iomem *outp_set; | 74 | unsigned long outp_set; |
78 | void __iomem *outp_clr; | 75 | unsigned long outp_clr; |
79 | void __iomem *dir_set; | 76 | unsigned long dir_set; |
80 | void __iomem *dir_clr; | 77 | unsigned long dir_clr; |
81 | }; | 78 | }; |
82 | 79 | ||
83 | /* | 80 | /* |
@@ -165,16 +162,27 @@ static struct gpio_regs gpio_grp_regs_p3 = { | |||
165 | struct lpc32xx_gpio_chip { | 162 | struct lpc32xx_gpio_chip { |
166 | struct gpio_chip chip; | 163 | struct gpio_chip chip; |
167 | struct gpio_regs *gpio_grp; | 164 | struct gpio_regs *gpio_grp; |
165 | void __iomem *reg_base; | ||
168 | }; | 166 | }; |
169 | 167 | ||
168 | static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset) | ||
169 | { | ||
170 | return __raw_readl(group->reg_base + offset); | ||
171 | } | ||
172 | |||
173 | static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset) | ||
174 | { | ||
175 | __raw_writel(val, group->reg_base + offset); | ||
176 | } | ||
177 | |||
170 | static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, | 178 | static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, |
171 | unsigned pin, int input) | 179 | unsigned pin, int input) |
172 | { | 180 | { |
173 | if (input) | 181 | if (input) |
174 | __raw_writel(GPIO012_PIN_TO_BIT(pin), | 182 | gpreg_write(group, GPIO012_PIN_TO_BIT(pin), |
175 | group->gpio_grp->dir_clr); | 183 | group->gpio_grp->dir_clr); |
176 | else | 184 | else |
177 | __raw_writel(GPIO012_PIN_TO_BIT(pin), | 185 | gpreg_write(group, GPIO012_PIN_TO_BIT(pin), |
178 | group->gpio_grp->dir_set); | 186 | group->gpio_grp->dir_set); |
179 | } | 187 | } |
180 | 188 | ||
@@ -184,19 +192,19 @@ static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group, | |||
184 | u32 u = GPIO3_PIN_TO_BIT(pin); | 192 | u32 u = GPIO3_PIN_TO_BIT(pin); |
185 | 193 | ||
186 | if (input) | 194 | if (input) |
187 | __raw_writel(u, group->gpio_grp->dir_clr); | 195 | gpreg_write(group, u, group->gpio_grp->dir_clr); |
188 | else | 196 | else |
189 | __raw_writel(u, group->gpio_grp->dir_set); | 197 | gpreg_write(group, u, group->gpio_grp->dir_set); |
190 | } | 198 | } |
191 | 199 | ||
192 | static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, | 200 | static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, |
193 | unsigned pin, int high) | 201 | unsigned pin, int high) |
194 | { | 202 | { |
195 | if (high) | 203 | if (high) |
196 | __raw_writel(GPIO012_PIN_TO_BIT(pin), | 204 | gpreg_write(group, GPIO012_PIN_TO_BIT(pin), |
197 | group->gpio_grp->outp_set); | 205 | group->gpio_grp->outp_set); |
198 | else | 206 | else |
199 | __raw_writel(GPIO012_PIN_TO_BIT(pin), | 207 | gpreg_write(group, GPIO012_PIN_TO_BIT(pin), |
200 | group->gpio_grp->outp_clr); | 208 | group->gpio_grp->outp_clr); |
201 | } | 209 | } |
202 | 210 | ||
@@ -206,31 +214,31 @@ static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group, | |||
206 | u32 u = GPIO3_PIN_TO_BIT(pin); | 214 | u32 u = GPIO3_PIN_TO_BIT(pin); |
207 | 215 | ||
208 | if (high) | 216 | if (high) |
209 | __raw_writel(u, group->gpio_grp->outp_set); | 217 | gpreg_write(group, u, group->gpio_grp->outp_set); |
210 | else | 218 | else |
211 | __raw_writel(u, group->gpio_grp->outp_clr); | 219 | gpreg_write(group, u, group->gpio_grp->outp_clr); |
212 | } | 220 | } |
213 | 221 | ||
214 | static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, | 222 | static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, |
215 | unsigned pin, int high) | 223 | unsigned pin, int high) |
216 | { | 224 | { |
217 | if (high) | 225 | if (high) |
218 | __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); | 226 | gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); |
219 | else | 227 | else |
220 | __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); | 228 | gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); |
221 | } | 229 | } |
222 | 230 | ||
223 | static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, | 231 | static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, |
224 | unsigned pin) | 232 | unsigned pin) |
225 | { | 233 | { |
226 | return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), | 234 | return GPIO012_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), |
227 | pin); | 235 | pin); |
228 | } | 236 | } |
229 | 237 | ||
230 | static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, | 238 | static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, |
231 | unsigned pin) | 239 | unsigned pin) |
232 | { | 240 | { |
233 | int state = __raw_readl(group->gpio_grp->inp_state); | 241 | int state = gpreg_read(group, group->gpio_grp->inp_state); |
234 | 242 | ||
235 | /* | 243 | /* |
236 | * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped | 244 | * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped |
@@ -242,13 +250,13 @@ static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, | |||
242 | static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, | 250 | static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, |
243 | unsigned pin) | 251 | unsigned pin) |
244 | { | 252 | { |
245 | return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin); | 253 | return GPI3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin); |
246 | } | 254 | } |
247 | 255 | ||
248 | static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group, | 256 | static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group, |
249 | unsigned pin) | 257 | unsigned pin) |
250 | { | 258 | { |
251 | return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin); | 259 | return GPO3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->outp_state), pin); |
252 | } | 260 | } |
253 | 261 | ||
254 | /* | 262 | /* |
@@ -497,12 +505,18 @@ static int lpc32xx_of_xlate(struct gpio_chip *gc, | |||
497 | static int lpc32xx_gpio_probe(struct platform_device *pdev) | 505 | static int lpc32xx_gpio_probe(struct platform_device *pdev) |
498 | { | 506 | { |
499 | int i; | 507 | int i; |
508 | void __iomem *reg_base; | ||
509 | |||
510 | reg_base = devm_platform_ioremap_resource(pdev, 0); | ||
511 | if (IS_ERR(reg_base)) | ||
512 | return PTR_ERR(reg_base); | ||
500 | 513 | ||
501 | for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) { | 514 | for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) { |
502 | if (pdev->dev.of_node) { | 515 | if (pdev->dev.of_node) { |
503 | lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate; | 516 | lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate; |
504 | lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3; | 517 | lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3; |
505 | lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node; | 518 | lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node; |
519 | lpc32xx_gpiochip[i].reg_base = reg_base; | ||
506 | } | 520 | } |
507 | devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip, | 521 | devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip, |
508 | &lpc32xx_gpiochip[i]); | 522 | &lpc32xx_gpiochip[i]); |
@@ -527,3 +541,7 @@ static struct platform_driver lpc32xx_gpio_driver = { | |||
527 | }; | 541 | }; |
528 | 542 | ||
529 | module_platform_driver(lpc32xx_gpio_driver); | 543 | module_platform_driver(lpc32xx_gpio_driver); |
544 | |||
545 | MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); | ||
546 | MODULE_LICENSE("GPL"); | ||
547 | MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC"); | ||
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index b2813580c582..7907a8755866 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c | |||
@@ -435,12 +435,9 @@ static int mxc_gpio_probe(struct platform_device *pdev) | |||
435 | return port->irq; | 435 | return port->irq; |
436 | 436 | ||
437 | /* the controller clock is optional */ | 437 | /* the controller clock is optional */ |
438 | port->clk = devm_clk_get(&pdev->dev, NULL); | 438 | port->clk = devm_clk_get_optional(&pdev->dev, NULL); |
439 | if (IS_ERR(port->clk)) { | 439 | if (IS_ERR(port->clk)) |
440 | if (PTR_ERR(port->clk) == -EPROBE_DEFER) | 440 | return PTR_ERR(port->clk); |
441 | return -EPROBE_DEFER; | ||
442 | port->clk = NULL; | ||
443 | } | ||
444 | 441 | ||
445 | err = clk_prepare_enable(port->clk); | 442 | err = clk_prepare_enable(port->clk); |
446 | if (err) { | 443 | if (err) { |
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index 378b206d2dc9..64d02ca60f53 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c | |||
@@ -9,6 +9,7 @@ | |||
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/acpi.h> | 11 | #include <linux/acpi.h> |
12 | #include <linux/bits.h> | ||
12 | #include <linux/gpio/driver.h> | 13 | #include <linux/gpio/driver.h> |
13 | #include <linux/gpio/consumer.h> | 14 | #include <linux/gpio/consumer.h> |
14 | #include <linux/i2c.h> | 15 | #include <linux/i2c.h> |
@@ -28,9 +29,9 @@ | |||
28 | #define PCA953X_INVERT 0x02 | 29 | #define PCA953X_INVERT 0x02 |
29 | #define PCA953X_DIRECTION 0x03 | 30 | #define PCA953X_DIRECTION 0x03 |
30 | 31 | ||
31 | #define REG_ADDR_MASK 0x3f | 32 | #define REG_ADDR_MASK GENMASK(5, 0) |
32 | #define REG_ADDR_EXT 0x40 | 33 | #define REG_ADDR_EXT BIT(6) |
33 | #define REG_ADDR_AI 0x80 | 34 | #define REG_ADDR_AI BIT(7) |
34 | 35 | ||
35 | #define PCA957X_IN 0x00 | 36 | #define PCA957X_IN 0x00 |
36 | #define PCA957X_INVRT 0x01 | 37 | #define PCA957X_INVRT 0x01 |
@@ -55,17 +56,17 @@ | |||
55 | #define PCAL6524_OUT_INDCONF 0x2c | 56 | #define PCAL6524_OUT_INDCONF 0x2c |
56 | #define PCAL6524_DEBOUNCE 0x2d | 57 | #define PCAL6524_DEBOUNCE 0x2d |
57 | 58 | ||
58 | #define PCA_GPIO_MASK 0x00FF | 59 | #define PCA_GPIO_MASK GENMASK(7, 0) |
59 | 60 | ||
60 | #define PCAL_GPIO_MASK 0x1f | 61 | #define PCAL_GPIO_MASK GENMASK(4, 0) |
61 | #define PCAL_PINCTRL_MASK 0x60 | 62 | #define PCAL_PINCTRL_MASK GENMASK(6, 5) |
62 | 63 | ||
63 | #define PCA_INT 0x0100 | 64 | #define PCA_INT BIT(8) |
64 | #define PCA_PCAL 0x0200 | 65 | #define PCA_PCAL BIT(9) |
65 | #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) | 66 | #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) |
66 | #define PCA953X_TYPE 0x1000 | 67 | #define PCA953X_TYPE BIT(12) |
67 | #define PCA957X_TYPE 0x2000 | 68 | #define PCA957X_TYPE BIT(13) |
68 | #define PCA_TYPE_MASK 0xF000 | 69 | #define PCA_TYPE_MASK GENMASK(15, 12) |
69 | 70 | ||
70 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) | 71 | #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) |
71 | 72 | ||
@@ -565,7 +566,7 @@ static void pca953x_irq_mask(struct irq_data *d) | |||
565 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | 566 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
566 | struct pca953x_chip *chip = gpiochip_get_data(gc); | 567 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
567 | 568 | ||
568 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); | 569 | chip->irq_mask[d->hwirq / BANK_SZ] &= ~BIT(d->hwirq % BANK_SZ); |
569 | } | 570 | } |
570 | 571 | ||
571 | static void pca953x_irq_unmask(struct irq_data *d) | 572 | static void pca953x_irq_unmask(struct irq_data *d) |
@@ -573,7 +574,7 @@ static void pca953x_irq_unmask(struct irq_data *d) | |||
573 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | 574 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
574 | struct pca953x_chip *chip = gpiochip_get_data(gc); | 575 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
575 | 576 | ||
576 | chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); | 577 | chip->irq_mask[d->hwirq / BANK_SZ] |= BIT(d->hwirq % BANK_SZ); |
577 | } | 578 | } |
578 | 579 | ||
579 | static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) | 580 | static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) |
@@ -641,7 +642,7 @@ static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) | |||
641 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | 642 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
642 | struct pca953x_chip *chip = gpiochip_get_data(gc); | 643 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
643 | int bank_nb = d->hwirq / BANK_SZ; | 644 | int bank_nb = d->hwirq / BANK_SZ; |
644 | u8 mask = 1 << (d->hwirq % BANK_SZ); | 645 | u8 mask = BIT(d->hwirq % BANK_SZ); |
645 | 646 | ||
646 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { | 647 | if (!(type & IRQ_TYPE_EDGE_BOTH)) { |
647 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", | 648 | dev_err(&chip->client->dev, "irq %d: unsupported type %d\n", |
@@ -666,7 +667,7 @@ static void pca953x_irq_shutdown(struct irq_data *d) | |||
666 | { | 667 | { |
667 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | 668 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
668 | struct pca953x_chip *chip = gpiochip_get_data(gc); | 669 | struct pca953x_chip *chip = gpiochip_get_data(gc); |
669 | u8 mask = 1 << (d->hwirq % BANK_SZ); | 670 | u8 mask = BIT(d->hwirq % BANK_SZ); |
670 | 671 | ||
671 | chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask; | 672 | chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask; |
672 | chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask; | 673 | chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask; |
@@ -849,12 +850,12 @@ static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert) | |||
849 | 850 | ||
850 | ret = regcache_sync_region(chip->regmap, chip->regs->output, | 851 | ret = regcache_sync_region(chip->regmap, chip->regs->output, |
851 | chip->regs->output + NBANK(chip)); | 852 | chip->regs->output + NBANK(chip)); |
852 | if (ret != 0) | 853 | if (ret) |
853 | goto out; | 854 | goto out; |
854 | 855 | ||
855 | ret = regcache_sync_region(chip->regmap, chip->regs->direction, | 856 | ret = regcache_sync_region(chip->regmap, chip->regs->direction, |
856 | chip->regs->direction + NBANK(chip)); | 857 | chip->regs->direction + NBANK(chip)); |
857 | if (ret != 0) | 858 | if (ret) |
858 | goto out; | 859 | goto out; |
859 | 860 | ||
860 | /* set platform specific polarity inversion */ | 861 | /* set platform specific polarity inversion */ |
@@ -949,19 +950,15 @@ static int pca953x_probe(struct i2c_client *client, | |||
949 | if (i2c_id) { | 950 | if (i2c_id) { |
950 | chip->driver_data = i2c_id->driver_data; | 951 | chip->driver_data = i2c_id->driver_data; |
951 | } else { | 952 | } else { |
952 | const struct acpi_device_id *acpi_id; | 953 | const void *match; |
953 | struct device *dev = &client->dev; | 954 | |
954 | 955 | match = device_get_match_data(&client->dev); | |
955 | chip->driver_data = (uintptr_t)of_device_get_match_data(dev); | 956 | if (!match) { |
956 | if (!chip->driver_data) { | 957 | ret = -ENODEV; |
957 | acpi_id = acpi_match_device(pca953x_acpi_ids, dev); | 958 | goto err_exit; |
958 | if (!acpi_id) { | ||
959 | ret = -ENODEV; | ||
960 | goto err_exit; | ||
961 | } | ||
962 | |||
963 | chip->driver_data = acpi_id->driver_data; | ||
964 | } | 959 | } |
960 | |||
961 | chip->driver_data = (uintptr_t)match; | ||
965 | } | 962 | } |
966 | 963 | ||
967 | i2c_set_clientdata(client, chip); | 964 | i2c_set_clientdata(client, chip); |
@@ -1041,8 +1038,7 @@ static int pca953x_remove(struct i2c_client *client) | |||
1041 | ret = pdata->teardown(client, chip->gpio_chip.base, | 1038 | ret = pdata->teardown(client, chip->gpio_chip.base, |
1042 | chip->gpio_chip.ngpio, pdata->context); | 1039 | chip->gpio_chip.ngpio, pdata->context); |
1043 | if (ret < 0) | 1040 | if (ret < 0) |
1044 | dev_err(&client->dev, "%s failed, %d\n", | 1041 | dev_err(&client->dev, "teardown failed, %d\n", ret); |
1045 | "teardown", ret); | ||
1046 | } else { | 1042 | } else { |
1047 | ret = 0; | 1043 | ret = 0; |
1048 | } | 1044 | } |
@@ -1064,14 +1060,14 @@ static int pca953x_regcache_sync(struct device *dev) | |||
1064 | */ | 1060 | */ |
1065 | ret = regcache_sync_region(chip->regmap, chip->regs->direction, | 1061 | ret = regcache_sync_region(chip->regmap, chip->regs->direction, |
1066 | chip->regs->direction + NBANK(chip)); | 1062 | chip->regs->direction + NBANK(chip)); |
1067 | if (ret != 0) { | 1063 | if (ret) { |
1068 | dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); | 1064 | dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); |
1069 | return ret; | 1065 | return ret; |
1070 | } | 1066 | } |
1071 | 1067 | ||
1072 | ret = regcache_sync_region(chip->regmap, chip->regs->output, | 1068 | ret = regcache_sync_region(chip->regmap, chip->regs->output, |
1073 | chip->regs->output + NBANK(chip)); | 1069 | chip->regs->output + NBANK(chip)); |
1074 | if (ret != 0) { | 1070 | if (ret) { |
1075 | dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); | 1071 | dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); |
1076 | return ret; | 1072 | return ret; |
1077 | } | 1073 | } |
@@ -1080,7 +1076,7 @@ static int pca953x_regcache_sync(struct device *dev) | |||
1080 | if (chip->driver_data & PCA_PCAL) { | 1076 | if (chip->driver_data & PCA_PCAL) { |
1081 | ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH, | 1077 | ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH, |
1082 | PCAL953X_IN_LATCH + NBANK(chip)); | 1078 | PCAL953X_IN_LATCH + NBANK(chip)); |
1083 | if (ret != 0) { | 1079 | if (ret) { |
1084 | dev_err(dev, "Failed to sync INT latch registers: %d\n", | 1080 | dev_err(dev, "Failed to sync INT latch registers: %d\n", |
1085 | ret); | 1081 | ret); |
1086 | return ret; | 1082 | return ret; |
@@ -1088,7 +1084,7 @@ static int pca953x_regcache_sync(struct device *dev) | |||
1088 | 1084 | ||
1089 | ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK, | 1085 | ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK, |
1090 | PCAL953X_INT_MASK + NBANK(chip)); | 1086 | PCAL953X_INT_MASK + NBANK(chip)); |
1091 | if (ret != 0) { | 1087 | if (ret) { |
1092 | dev_err(dev, "Failed to sync INT mask registers: %d\n", | 1088 | dev_err(dev, "Failed to sync INT mask registers: %d\n", |
1093 | ret); | 1089 | ret); |
1094 | return ret; | 1090 | return ret; |
@@ -1120,7 +1116,7 @@ static int pca953x_resume(struct device *dev) | |||
1120 | 1116 | ||
1121 | if (!atomic_read(&chip->wakeup_path)) { | 1117 | if (!atomic_read(&chip->wakeup_path)) { |
1122 | ret = regulator_enable(chip->regulator); | 1118 | ret = regulator_enable(chip->regulator); |
1123 | if (ret != 0) { | 1119 | if (ret) { |
1124 | dev_err(dev, "Failed to enable regulator: %d\n", ret); | 1120 | dev_err(dev, "Failed to enable regulator: %d\n", ret); |
1125 | return 0; | 1121 | return 0; |
1126 | } | 1122 | } |
@@ -1133,7 +1129,7 @@ static int pca953x_resume(struct device *dev) | |||
1133 | return ret; | 1129 | return ret; |
1134 | 1130 | ||
1135 | ret = regcache_sync(chip->regmap); | 1131 | ret = regcache_sync(chip->regmap); |
1136 | if (ret != 0) { | 1132 | if (ret) { |
1137 | dev_err(dev, "Failed to restore register map: %d\n", ret); | 1133 | dev_err(dev, "Failed to restore register map: %d\n", ret); |
1138 | return ret; | 1134 | return ret; |
1139 | } | 1135 | } |