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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2018-08-27 11:35:54 -0400
committerChanwoo Choi <cw00.choi@samsung.com>2018-08-27 22:21:15 -0400
commit001d3eccf9fc9b598b155f94b5f727ee825252d9 (patch)
tree261fe1606cfbe7bfe128c3eac6930995fa57205c /drivers/extcon/extcon-intel-cht-wc.c
parent962341b54b99965ebec5f70c8d39f1c382eea833 (diff)
extcon: cht-wc: Fix definition names according to spec
There is no suffix MASK in the spec and other small spelling fixes. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Diffstat (limited to 'drivers/extcon/extcon-intel-cht-wc.c')
-rw-r--r--drivers/extcon/extcon-intel-cht-wc.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/extcon/extcon-intel-cht-wc.c b/drivers/extcon/extcon-intel-cht-wc.c
index bdb67878179e..71b1126dbb0b 100644
--- a/drivers/extcon/extcon-intel-cht-wc.c
+++ b/drivers/extcon/extcon-intel-cht-wc.c
@@ -32,10 +32,10 @@
32#define CHT_WC_CHGRCTRL0_EMRGCHREN BIT(1) 32#define CHT_WC_CHGRCTRL0_EMRGCHREN BIT(1)
33#define CHT_WC_CHGRCTRL0_EXTCHRDIS BIT(2) 33#define CHT_WC_CHGRCTRL0_EXTCHRDIS BIT(2)
34#define CHT_WC_CHGRCTRL0_SWCONTROL BIT(3) 34#define CHT_WC_CHGRCTRL0_SWCONTROL BIT(3)
35#define CHT_WC_CHGRCTRL0_TTLCK_MASK BIT(4) 35#define CHT_WC_CHGRCTRL0_TTLCK BIT(4)
36#define CHT_WC_CHGRCTRL0_CCSM_OFF_MASK BIT(5) 36#define CHT_WC_CHGRCTRL0_CCSM_OFF BIT(5)
37#define CHT_WC_CHGRCTRL0_DBPOFF_MASK BIT(6) 37#define CHT_WC_CHGRCTRL0_DBPOFF BIT(6)
38#define CHT_WC_CHGRCTRL0_WDT_NOKICK BIT(7) 38#define CHT_WC_CHGRCTRL0_CHR_WDT_NOKICK BIT(7)
39 39
40#define CHT_WC_CHGRCTRL1 0x5e17 40#define CHT_WC_CHGRCTRL1 0x5e17
41 41
@@ -52,7 +52,7 @@
52#define CHT_WC_USBSRC_TYPE_ACA 4 52#define CHT_WC_USBSRC_TYPE_ACA 4
53#define CHT_WC_USBSRC_TYPE_SE1 5 53#define CHT_WC_USBSRC_TYPE_SE1 5
54#define CHT_WC_USBSRC_TYPE_MHL 6 54#define CHT_WC_USBSRC_TYPE_MHL 6
55#define CHT_WC_USBSRC_TYPE_FLOAT_DP_DN 7 55#define CHT_WC_USBSRC_TYPE_FLOATING 7
56#define CHT_WC_USBSRC_TYPE_OTHER 8 56#define CHT_WC_USBSRC_TYPE_OTHER 8
57#define CHT_WC_USBSRC_TYPE_DCP_EXTPHY 9 57#define CHT_WC_USBSRC_TYPE_DCP_EXTPHY 9
58 58
@@ -61,7 +61,7 @@
61#define CHT_WC_PWRSRC_STS 0x6e1e 61#define CHT_WC_PWRSRC_STS 0x6e1e
62#define CHT_WC_PWRSRC_VBUS BIT(0) 62#define CHT_WC_PWRSRC_VBUS BIT(0)
63#define CHT_WC_PWRSRC_DC BIT(1) 63#define CHT_WC_PWRSRC_DC BIT(1)
64#define CHT_WC_PWRSRC_BAT BIT(2) 64#define CHT_WC_PWRSRC_BATT BIT(2)
65#define CHT_WC_PWRSRC_ID_GND BIT(3) 65#define CHT_WC_PWRSRC_ID_GND BIT(3)
66#define CHT_WC_PWRSRC_ID_FLOAT BIT(4) 66#define CHT_WC_PWRSRC_ID_FLOAT BIT(4)
67 67
@@ -158,7 +158,7 @@ static int cht_wc_extcon_get_charger(struct cht_wc_extcon_data *ext,
158 ret); 158 ret);
159 return EXTCON_CHG_USB_SDP; 159 return EXTCON_CHG_USB_SDP;
160 case CHT_WC_USBSRC_TYPE_SDP: 160 case CHT_WC_USBSRC_TYPE_SDP:
161 case CHT_WC_USBSRC_TYPE_FLOAT_DP_DN: 161 case CHT_WC_USBSRC_TYPE_FLOATING:
162 case CHT_WC_USBSRC_TYPE_OTHER: 162 case CHT_WC_USBSRC_TYPE_OTHER:
163 return EXTCON_CHG_USB_SDP; 163 return EXTCON_CHG_USB_SDP;
164 case CHT_WC_USBSRC_TYPE_CDP: 164 case CHT_WC_USBSRC_TYPE_CDP:
@@ -279,7 +279,7 @@ static int cht_wc_extcon_sw_control(struct cht_wc_extcon_data *ext, bool enable)
279{ 279{
280 int ret, mask, val; 280 int ret, mask, val;
281 281
282 mask = CHT_WC_CHGRCTRL0_SWCONTROL | CHT_WC_CHGRCTRL0_CCSM_OFF_MASK; 282 mask = CHT_WC_CHGRCTRL0_SWCONTROL | CHT_WC_CHGRCTRL0_CCSM_OFF;
283 val = enable ? mask : 0; 283 val = enable ? mask : 0;
284 ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val); 284 ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val);
285 if (ret) 285 if (ret)