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authorBorislav Petkov <bp@suse.de>2018-05-18 07:13:31 -0400
committerBorislav Petkov <bp@suse.de>2018-05-21 06:18:57 -0400
commiteaa3a1d46cfdbf1af50311e7a22f5d38c0418b56 (patch)
treef02b9c210b84ff303bce451ab3449f81d8200a06 /drivers/edac
parent9ef20753e044f7468c4113e5aecd785419b0b3cc (diff)
EDAC, ghes: Make platform-based whitelisting x86-only
ARM machines all have DMI tables so if they request hw error reporting through GHES, then the driver should be able to detect DIMMs and report errors successfully (famous last words :)). Make the platform-based list x86-specific so that ghes_edac can load on ARM. Reported-by: Qiang Zheng <zhengqiang10@huawei.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: James Morse <james.morse@arm.com> Tested-by: James Morse <james.morse@arm.com> Tested-by: Qiang Zheng <zhengqiang10@huawei.com> Link: https://lkml.kernel.org/r/1526039543-180996-1-git-send-email-zhengqiang10@huawei.com
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/ghes_edac.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c
index 863fbf3db29f..473aeec4b1da 100644
--- a/drivers/edac/ghes_edac.c
+++ b/drivers/edac/ghes_edac.c
@@ -440,12 +440,16 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev)
440 struct mem_ctl_info *mci; 440 struct mem_ctl_info *mci;
441 struct edac_mc_layer layers[1]; 441 struct edac_mc_layer layers[1];
442 struct ghes_edac_dimm_fill dimm_fill; 442 struct ghes_edac_dimm_fill dimm_fill;
443 int idx; 443 int idx = -1;
444 444
445 /* Check if safe to enable on this system */ 445 if (IS_ENABLED(CONFIG_X86)) {
446 idx = acpi_match_platform_list(plat_list); 446 /* Check if safe to enable on this system */
447 if (!force_load && idx < 0) 447 idx = acpi_match_platform_list(plat_list);
448 return -ENODEV; 448 if (!force_load && idx < 0)
449 return -ENODEV;
450 } else {
451 idx = 0;
452 }
449 453
450 /* 454 /*
451 * We have only one logical memory controller to which all DIMMs belong. 455 * We have only one logical memory controller to which all DIMMs belong.