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authorStephen Douthit <stephend@silicom-usa.com>2019-08-09 10:18:02 -0400
committerTony Luck <tony.luck@intel.com>2019-08-09 13:19:07 -0400
commit29a3388bfcce7a6d087051376ea02bf8326a957b (patch)
tree2ea8c3ed2964db077bb3894731e3e9e987b3c403 /drivers/edac
parent82413e562ea6eadfb6de946dcc6f74af31d64e7f (diff)
EDAC, pnd2: Fix ioremap() size in dnv_rd_reg()
Depending on how BIOS has marked the reserved region containing the 32KB MCHBAR you can get warnings like: resource sanity check: requesting [mem 0xfed10000-0xfed1ffff], which spans more than reserved [mem 0xfed10000-0xfed17fff] caller dnv_rd_reg+0xc8/0x240 [pnd2_edac] mapping multiple BARs Not all of the mmio regions used in dnv_rd_reg() are the same size. The MCHBAR window is 32KB and the sideband ports are 64KB. Pass the correct size to ioremap() depending on which resource we're reading from. Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/pnd2_edac.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/edac/pnd2_edac.c b/drivers/edac/pnd2_edac.c
index ca25f8fe57ef..1ad538baaa4a 100644
--- a/drivers/edac/pnd2_edac.c
+++ b/drivers/edac/pnd2_edac.c
@@ -260,11 +260,14 @@ static u64 get_sideband_reg_base_addr(void)
260 } 260 }
261} 261}
262 262
263#define DNV_MCHBAR_SIZE 0x8000
264#define DNV_SB_PORT_SIZE 0x10000
263static int dnv_rd_reg(int port, int off, int op, void *data, size_t sz, char *name) 265static int dnv_rd_reg(int port, int off, int op, void *data, size_t sz, char *name)
264{ 266{
265 struct pci_dev *pdev; 267 struct pci_dev *pdev;
266 char *base; 268 char *base;
267 u64 addr; 269 u64 addr;
270 unsigned long size;
268 271
269 if (op == 4) { 272 if (op == 4) {
270 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x1980, NULL); 273 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x1980, NULL);
@@ -279,15 +282,17 @@ static int dnv_rd_reg(int port, int off, int op, void *data, size_t sz, char *na
279 addr = get_mem_ctrl_hub_base_addr(); 282 addr = get_mem_ctrl_hub_base_addr();
280 if (!addr) 283 if (!addr)
281 return -ENODEV; 284 return -ENODEV;
285 size = DNV_MCHBAR_SIZE;
282 } else { 286 } else {
283 /* MMIO via sideband register base address */ 287 /* MMIO via sideband register base address */
284 addr = get_sideband_reg_base_addr(); 288 addr = get_sideband_reg_base_addr();
285 if (!addr) 289 if (!addr)
286 return -ENODEV; 290 return -ENODEV;
287 addr += (port << 16); 291 addr += (port << 16);
292 size = DNV_SB_PORT_SIZE;
288 } 293 }
289 294
290 base = ioremap((resource_size_t)addr, 0x10000); 295 base = ioremap((resource_size_t)addr, size);
291 if (!base) 296 if (!base)
292 return -ENODEV; 297 return -ENODEV;
293 298