dmaengine: xilinx_dma: properly configure the SG mode bit in the driver for cdma

If the hardware is configured for Scatter Gather(SG) mode,
and hardware is idle, in the control register SG mode bit
must be set to a 0 then back to 1 by the software, to force
the CDMA SG engine to use a new value written to the CURDESC_PNTR
register, failure to do so could result errors from the dmaengine.

This patch updates the same.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

1 files changed, 10 insertions, 0 deletions

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 88d317de6908..e32ebe0837af 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -1204,6 +1204,12 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
         }
 
         if (chan->has_sg) {
+                dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
+                             XILINX_CDMA_CR_SGMODE);
+
+                dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
+                             XILINX_CDMA_CR_SGMODE);
+
                 xilinx_write(chan, XILINX_DMA_REG_CURDESC,
                              head_desc->async_tx.phys);
 
@@ -2052,6 +2058,10 @@ static int xilinx_dma_terminate_all(struct dma_chan *dchan)
                 chan->cyclic = false;
         }
 
+        if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
+                dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
+                             XILINX_CDMA_CR_SGMODE);
+
         return 0;
 }