Merge tag 'dmaengine-4.4-rc1' of git://git.infradead.org/users/vkoul/slave-dma

Pull dmaengine updates from Vinod Koul:
 "This time we have a very typical update which is mostly fixes and
  updates to drivers and no new drivers.

   - the biggest change is coming from Peter for edma cleanup which even
     caused some last minute regression, things seem settled now
   - idma64 and dw updates
   - iotdma updates
   - module autoload fixes for various drivers
   - scatter gather support for hdmac"

* tag 'dmaengine-4.4-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (77 commits)
  dmaengine: edma: Add dummy driver skeleton for edma3-tptc
  Revert "ARM: DTS: am33xx: Use the new DT bindings for the eDMA3"
  Revert "ARM: DTS: am437x: Use the new DT bindings for the eDMA3"
  dmaengine: dw: some Intel devices has no memcpy support
  dmaengine: dw: platform: provide platform data for Intel
  dmaengine: dw: don't override platform data with autocfg
  dmaengine: hdmac: Add scatter-gathered memset support
  dmaengine: hdmac: factorise memset descriptor allocation
  dmaengine: virt-dma: Fix kernel-doc annotations
  ARM: DTS: am437x: Use the new DT bindings for the eDMA3
  ARM: DTS: am33xx: Use the new DT bindings for the eDMA3
  dmaengine: edma: New device tree binding
  dmaengine: Kconfig: edma: Select TI_DMA_CROSSBAR in case of ARCH_OMAP
  dmaengine: ti-dma-crossbar: Add support for crossbar on AM33xx/AM43xx
  dmaengine: edma: Merge the of parsing functions
  dmaengine: edma: Do not allocate memory for edma_rsv_info in case of DT boot
  dmaengine: edma: Refactor the dma device and channel struct initialization
  dmaengine: edma: Get qDMA channel information from HW also
  dmaengine: edma: Merge map_dmach_to_queue into assign_channel_eventq
  dmaengine: edma: Correct PaRAM access function names (_parm_ to _param_)
  ...

1 files changed, 2 insertions, 61 deletions

diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index 8d57b1b12e41..9dfa2b0fa5da 100644
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -547,14 +547,12 @@ static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor(
         struct xgene_dma_desc_sw *desc;
         dma_addr_t phys;
 
-        desc = dma_pool_alloc(chan->desc_pool, GFP_NOWAIT, &phys);
+        desc = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys);
         if (!desc) {
                 chan_err(chan, "Failed to allocate LDs\n");
                 return NULL;
         }
 
-        memset(desc, 0, sizeof(*desc));
-
         INIT_LIST_HEAD(&desc->tx_list);
         desc->tx.phys = phys;
         desc->tx.tx_submit = xgene_dma_tx_submit;
@@ -894,60 +892,6 @@ static void xgene_dma_free_chan_resources(struct dma_chan *dchan)
         chan->desc_pool = NULL;
 }
 
-static struct dma_async_tx_descriptor *xgene_dma_prep_memcpy(
-        struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src,
-        size_t len, unsigned long flags)
-{
-        struct xgene_dma_desc_sw *first = NULL, *new;
-        struct xgene_dma_chan *chan;
-        size_t copy;
-
-        if (unlikely(!dchan || !len))
-                return NULL;
-
-        chan = to_dma_chan(dchan);
-
-        do {
-                /* Allocate the link descriptor from DMA pool */
-                new = xgene_dma_alloc_descriptor(chan);
-                if (!new)
-                        goto fail;
-
-                /* Create the largest transaction possible */
-                copy = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT);
-
-                /* Prepare DMA descriptor */
-                xgene_dma_prep_cpy_desc(chan, new, dst, src, copy);
-
-                if (!first)
-                        first = new;
-
-                new->tx.cookie = 0;
-                async_tx_ack(&new->tx);
-
-                /* Update metadata */
-                len -= copy;
-                dst += copy;
-                src += copy;
-
-                /* Insert the link descriptor to the LD ring */
-                list_add_tail(&new->node, &first->tx_list);
-        } while (len);
-
-        new->tx.flags = flags; /* client is in control of this ack */
-        new->tx.cookie = -EBUSY;
-        list_splice(&first->tx_list, &new->tx_list);
-
-        return &new->tx;
-
-fail:
-        if (!first)
-                return NULL;
-
-        xgene_dma_free_desc_list(chan, &first->tx_list);
-        return NULL;
-}
-
 static struct dma_async_tx_descriptor *xgene_dma_prep_sg(
         struct dma_chan *dchan, struct scatterlist *dst_sg,
         u32 dst_nents, struct scatterlist *src_sg,
@@ -1707,7 +1651,6 @@ static void xgene_dma_set_caps(struct xgene_dma_chan *chan,
         dma_cap_zero(dma_dev->cap_mask);
 
         /* Set DMA device capability */
-        dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
         dma_cap_set(DMA_SG, dma_dev->cap_mask);
 
         /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR
@@ -1734,7 +1677,6 @@ static void xgene_dma_set_caps(struct xgene_dma_chan *chan,
         dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources;
         dma_dev->device_issue_pending = xgene_dma_issue_pending;
         dma_dev->device_tx_status = xgene_dma_tx_status;
-        dma_dev->device_prep_dma_memcpy = xgene_dma_prep_memcpy;
         dma_dev->device_prep_dma_sg = xgene_dma_prep_sg;
 
         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
@@ -1787,8 +1729,7 @@ static int xgene_dma_async_register(struct xgene_dma *pdma, int id)
 
         /* DMA capability info */
         dev_info(pdma->dev,
-                 "%s: CAPABILITY ( %s%s%s%s)\n", dma_chan_name(&chan->dma_chan),
-                 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "MEMCPY " : "",
+                 "%s: CAPABILITY ( %s%s%s)\n", dma_chan_name(&chan->dma_chan),
                  dma_has_cap(DMA_SG, dma_dev->cap_mask) ? "SGCPY " : "",
                  dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "",
                  dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : "");