Merge tag 'dmaengine-5.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma

Pull dmaengine updates from Vinod Koul:

 - Add support in dmaengine core to do device node checks for DT devices
   and update bunch of drivers to use that and remove open coding from
   drivers

 - New driver/driver support for new hardware, namely:
     - MediaTek UART APDMA
     - Freescale i.mx7ulp edma2
     - Synopsys eDMA IP core version 0
     - Allwinner H6 DMA

 - Updates to axi-dma and support for interleaved cyclic transfers

 - Greg's debugfs return value check removals on drivers

 - Updates to stm32-dma, hsu, dw, pl330, tegra drivers

* tag 'dmaengine-5.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (68 commits)
  dmaengine: Revert "dmaengine: fsl-edma: add i.mx7ulp edma2 version support"
  dmaengine: at_xdmac: check for non-empty xfers_list before invoking callback
  Documentation: dmaengine: clean up description of dmatest usage
  dmaengine: tegra210-adma: remove PM_CLK dependency
  dmaengine: fsl-edma: add i.mx7ulp edma2 version support
  dt-bindings: dma: fsl-edma: add new i.mx7ulp-edma
  dmaengine: fsl-edma-common: version check for v2 instead
  dmaengine: fsl-edma-common: move dmamux register to another single function
  dmaengine: fsl-edma: add drvdata for fsl-edma
  dmaengine: Revert "dmaengine: fsl-edma: support little endian for edma driver"
  dmaengine: rcar-dmac: Reject zero-length slave DMA requests
  dmaengine: dw: Enable iDMA 32-bit on Intel Elkhart Lake
  dmaengine: dw-edma: fix semicolon.cocci warnings
  dmaengine: sh: usb-dmac: Use [] to denote a flexible array member
  dmaengine: dmatest: timeout value of -1 should specify infinite wait
  dmaengine: dw: Distinguish ->remove() between DW and iDMA 32-bit
  dmaengine: fsl-edma: support little endian for edma driver
  dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width"
  dmagengine: pl330: add code to get reset property
  dt-bindings: pl330: document the optional resets property
  ...

1 files changed, 112 insertions, 35 deletions

diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index e8fcc69b1de9..ed5b68dcfe50 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
@@ -64,17 +64,20 @@
 #define DMA_CHAN_LLI_ADDR       0x08
 
 #define DMA_CHAN_CUR_CFG        0x0c
-#define DMA_CHAN_MAX_DRQ                0x1f
-#define DMA_CHAN_CFG_SRC_DRQ(x)         ((x) & DMA_CHAN_MAX_DRQ)
-#define DMA_CHAN_CFG_SRC_IO_MODE        BIT(5)
-#define DMA_CHAN_CFG_SRC_LINEAR_MODE    (0 << 5)
+#define DMA_CHAN_MAX_DRQ_A31            0x1f
+#define DMA_CHAN_MAX_DRQ_H6             0x3f
+#define DMA_CHAN_CFG_SRC_DRQ_A31(x)     ((x) & DMA_CHAN_MAX_DRQ_A31)
+#define DMA_CHAN_CFG_SRC_DRQ_H6(x)      ((x) & DMA_CHAN_MAX_DRQ_H6)
+#define DMA_CHAN_CFG_SRC_MODE_A31(x)    (((x) & 0x1) << 5)
+#define DMA_CHAN_CFG_SRC_MODE_H6(x)     (((x) & 0x1) << 8)
 #define DMA_CHAN_CFG_SRC_BURST_A31(x)   (((x) & 0x3) << 7)
 #define DMA_CHAN_CFG_SRC_BURST_H3(x)    (((x) & 0x3) << 6)
 #define DMA_CHAN_CFG_SRC_WIDTH(x)       (((x) & 0x3) << 9)
 
-#define DMA_CHAN_CFG_DST_DRQ(x)         (DMA_CHAN_CFG_SRC_DRQ(x) << 16)
-#define DMA_CHAN_CFG_DST_IO_MODE        (DMA_CHAN_CFG_SRC_IO_MODE << 16)
-#define DMA_CHAN_CFG_DST_LINEAR_MODE    (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16)
+#define DMA_CHAN_CFG_DST_DRQ_A31(x)     (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16)
+#define DMA_CHAN_CFG_DST_DRQ_H6(x)      (DMA_CHAN_CFG_SRC_DRQ_H6(x) << 16)
+#define DMA_CHAN_CFG_DST_MODE_A31(x)    (DMA_CHAN_CFG_SRC_MODE_A31(x) << 16)
+#define DMA_CHAN_CFG_DST_MODE_H6(x)     (DMA_CHAN_CFG_SRC_MODE_H6(x) << 16)
 #define DMA_CHAN_CFG_DST_BURST_A31(x)   (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)
 #define DMA_CHAN_CFG_DST_BURST_H3(x)    (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16)
 #define DMA_CHAN_CFG_DST_WIDTH(x)       (DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
@@ -94,6 +97,8 @@
 #define LLI_LAST_ITEM   0xfffff800
 #define NORMAL_WAIT     8
 #define DRQ_SDRAM       1
+#define LINEAR_MODE     0
+#define IO_MODE         1
 
 /* forward declaration */
 struct sun6i_dma_dev;
@@ -121,10 +126,13 @@ struct sun6i_dma_config {
          */
         void (*clock_autogate_enable)(struct sun6i_dma_dev *);
         void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst);
+        void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq);
+        void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode);
         u32 src_burst_lengths;
         u32 dst_burst_lengths;
         u32 src_addr_widths;
         u32 dst_addr_widths;
+        bool has_mbus_clk;
 };
 
 /*
@@ -178,6 +186,7 @@ struct sun6i_dma_dev {
         struct dma_device       slave;
         void __iomem            *base;
         struct clk              *clk;
+        struct clk              *clk_mbus;
         int                     irq;
         spinlock_t              lock;
         struct reset_control    *rstc;
@@ -305,6 +314,30 @@ static void sun6i_set_burst_length_h3(u32 *p_cfg, s8 src_burst, s8 dst_burst)
                   DMA_CHAN_CFG_DST_BURST_H3(dst_burst);
 }
 
+static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq)
+{
+        *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_A31(src_drq) |
+                  DMA_CHAN_CFG_DST_DRQ_A31(dst_drq);
+}
+
+static void sun6i_set_drq_h6(u32 *p_cfg, s8 src_drq, s8 dst_drq)
+{
+        *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_H6(src_drq) |
+                  DMA_CHAN_CFG_DST_DRQ_H6(dst_drq);
+}
+
+static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode)
+{
+        *p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) |
+                  DMA_CHAN_CFG_DST_MODE_A31(dst_mode);
+}
+
+static void sun6i_set_mode_h6(u32 *p_cfg, s8 src_mode, s8 dst_mode)
+{
+        *p_cfg |= DMA_CHAN_CFG_SRC_MODE_H6(src_mode) |
+                  DMA_CHAN_CFG_DST_MODE_H6(dst_mode);
+}
+
 static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)
 {
         struct sun6i_desc *txd = pchan->desc;
@@ -628,14 +661,12 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
 
         burst = convert_burst(8);
         width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);
-        v_lli->cfg = DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
-                DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
-                DMA_CHAN_CFG_DST_LINEAR_MODE |
-                DMA_CHAN_CFG_SRC_LINEAR_MODE |
-                DMA_CHAN_CFG_SRC_WIDTH(width) |
+        v_lli->cfg = DMA_CHAN_CFG_SRC_WIDTH(width) |
                 DMA_CHAN_CFG_DST_WIDTH(width);
 
         sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst);
+        sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, DRQ_SDRAM);
+        sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, LINEAR_MODE);
 
         sun6i_dma_lli_add(NULL, v_lli, p_lli, txd);
 
@@ -687,11 +718,9 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
                 if (dir == DMA_MEM_TO_DEV) {
                         v_lli->src = sg_dma_address(sg);
                         v_lli->dst = sconfig->dst_addr;
-                        v_lli->cfg = lli_cfg |
-                                DMA_CHAN_CFG_DST_IO_MODE |
-                                DMA_CHAN_CFG_SRC_LINEAR_MODE |
-                                DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
-                                DMA_CHAN_CFG_DST_DRQ(vchan->port);
+                        v_lli->cfg = lli_cfg;
+                        sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
+                        sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE);
 
                         dev_dbg(chan2dev(chan),
                                 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
@@ -702,11 +731,9 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
                 } else {
                         v_lli->src = sconfig->src_addr;
                         v_lli->dst = sg_dma_address(sg);
-                        v_lli->cfg = lli_cfg |
-                                DMA_CHAN_CFG_DST_LINEAR_MODE |
-                                DMA_CHAN_CFG_SRC_IO_MODE |
-                                DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
-                                DMA_CHAN_CFG_SRC_DRQ(vchan->port);
+                        v_lli->cfg = lli_cfg;
+                        sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
+                        sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE);
 
                         dev_dbg(chan2dev(chan),
                                 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
@@ -772,19 +799,15 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic(
                 if (dir == DMA_MEM_TO_DEV) {
                         v_lli->src = buf_addr + period_len * i;
                         v_lli->dst = sconfig->dst_addr;
-                        v_lli->cfg = lli_cfg |
-                                DMA_CHAN_CFG_DST_IO_MODE |
-                                DMA_CHAN_CFG_SRC_LINEAR_MODE |
-                                DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) |
-                                DMA_CHAN_CFG_DST_DRQ(vchan->port);
+                        v_lli->cfg = lli_cfg;
+                        sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
+                        sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE);
                 } else {
                         v_lli->src = sconfig->src_addr;
                         v_lli->dst = buf_addr + period_len * i;
-                        v_lli->cfg = lli_cfg |
-                                DMA_CHAN_CFG_DST_LINEAR_MODE |
-                                DMA_CHAN_CFG_SRC_IO_MODE |
-                                DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |
-                                DMA_CHAN_CFG_SRC_DRQ(vchan->port);
+                        v_lli->cfg = lli_cfg;
+                        sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
+                        sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE);
                 }
 
                 prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
@@ -1049,6 +1072,8 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = {
         .nr_max_requests = 30,
         .nr_max_vchans   = 53,
         .set_burst_length = sun6i_set_burst_length_a31,
+        .set_drq          = sun6i_set_drq_a31,
+        .set_mode         = sun6i_set_mode_a31,
         .src_burst_lengths = BIT(1) | BIT(8),
         .dst_burst_lengths = BIT(1) | BIT(8),
         .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
@@ -1070,6 +1095,8 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = {
         .nr_max_vchans   = 37,
         .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
         .set_burst_length = sun6i_set_burst_length_a31,
+        .set_drq          = sun6i_set_drq_a31,
+        .set_mode         = sun6i_set_mode_a31,
         .src_burst_lengths = BIT(1) | BIT(8),
         .dst_burst_lengths = BIT(1) | BIT(8),
         .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
@@ -1086,6 +1113,8 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = {
         .nr_max_vchans   = 39,
         .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
         .set_burst_length = sun6i_set_burst_length_a31,
+        .set_drq          = sun6i_set_drq_a31,
+        .set_mode         = sun6i_set_mode_a31,
         .src_burst_lengths = BIT(1) | BIT(8),
         .dst_burst_lengths = BIT(1) | BIT(8),
         .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
@@ -1109,6 +1138,8 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
         .nr_max_vchans   = 34,
         .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
         .set_burst_length = sun6i_set_burst_length_h3,
+        .set_drq          = sun6i_set_drq_a31,
+        .set_mode         = sun6i_set_mode_a31,
         .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
         .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
         .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
@@ -1128,6 +1159,8 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
 static struct sun6i_dma_config sun50i_a64_dma_cfg = {
         .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
         .set_burst_length = sun6i_set_burst_length_h3,
+        .set_drq          = sun6i_set_drq_a31,
+        .set_mode         = sun6i_set_mode_a31,
         .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
         .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
         .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
@@ -1141,6 +1174,28 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = {
 };
 
 /*
+ * The H6 binding uses the number of dma channels from the
+ * device tree node.
+ */
+static struct sun6i_dma_config sun50i_h6_dma_cfg = {
+        .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
+        .set_burst_length = sun6i_set_burst_length_h3,
+        .set_drq          = sun6i_set_drq_h6,
+        .set_mode         = sun6i_set_mode_h6,
+        .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
+        .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
+        .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+                             BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
+                             BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
+                             BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
+        .dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+                             BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
+                             BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
+                             BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
+        .has_mbus_clk = true,
+};
+
+/*
  * The V3s have only 8 physical channels, a maximum DRQ port id of 23,
  * and a total of 24 usable source and destination endpoints.
  */
@@ -1151,6 +1206,8 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = {
         .nr_max_vchans   = 24,
         .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
         .set_burst_length = sun6i_set_burst_length_a31,
+        .set_drq          = sun6i_set_drq_a31,
+        .set_mode         = sun6i_set_mode_a31,
         .src_burst_lengths = BIT(1) | BIT(8),
         .dst_burst_lengths = BIT(1) | BIT(8),
         .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
@@ -1168,6 +1225,7 @@ static const struct of_device_id sun6i_dma_match[] = {
         { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
         { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg },
         { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
+        { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg },
         { /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, sun6i_dma_match);
@@ -1204,6 +1262,14 @@ static int sun6i_dma_probe(struct platform_device *pdev)
                 return PTR_ERR(sdc->clk);
         }
 
+        if (sdc->cfg->has_mbus_clk) {
+                sdc->clk_mbus = devm_clk_get(&pdev->dev, "mbus");
+                if (IS_ERR(sdc->clk_mbus)) {
+                        dev_err(&pdev->dev, "No mbus clock specified\n");
+                        return PTR_ERR(sdc->clk_mbus);
+                }
+        }
+
         sdc->rstc = devm_reset_control_get(&pdev->dev, NULL);
         if (IS_ERR(sdc->rstc)) {
                 dev_err(&pdev->dev, "No reset controller specified\n");
@@ -1258,8 +1324,8 @@ static int sun6i_dma_probe(struct platform_device *pdev)
         ret = of_property_read_u32(np, "dma-requests", &sdc->max_request);
         if (ret && !sdc->max_request) {
                 dev_info(&pdev->dev, "Missing dma-requests, using %u.\n",
-                         DMA_CHAN_MAX_DRQ);
-                sdc->max_request = DMA_CHAN_MAX_DRQ;
+                         DMA_CHAN_MAX_DRQ_A31);
+                sdc->max_request = DMA_CHAN_MAX_DRQ_A31;
         }
 
         /*
@@ -1308,11 +1374,19 @@ static int sun6i_dma_probe(struct platform_device *pdev)
                 goto err_reset_assert;
         }
 
+        if (sdc->cfg->has_mbus_clk) {
+                ret = clk_prepare_enable(sdc->clk_mbus);
+                if (ret) {
+                        dev_err(&pdev->dev, "Couldn't enable mbus clock\n");
+                        goto err_clk_disable;
+                }
+        }
+
         ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0,
                                dev_name(&pdev->dev), sdc);
         if (ret) {
                 dev_err(&pdev->dev, "Cannot request IRQ\n");
-                goto err_clk_disable;
+                goto err_mbus_clk_disable;
         }
 
         ret = dma_async_device_register(&sdc->slave);
@@ -1337,6 +1411,8 @@ err_dma_unregister:
         dma_async_device_unregister(&sdc->slave);
 err_irq_disable:
         sun6i_kill_tasklet(sdc);
+err_mbus_clk_disable:
+        clk_disable_unprepare(sdc->clk_mbus);
 err_clk_disable:
         clk_disable_unprepare(sdc->clk);
 err_reset_assert:
@@ -1355,6 +1431,7 @@ static int sun6i_dma_remove(struct platform_device *pdev)
 
         sun6i_kill_tasklet(sdc);
 
+        clk_disable_unprepare(sdc->clk_mbus);
         clk_disable_unprepare(sdc->clk);
         reset_control_assert(sdc->rstc);