summaryrefslogtreecommitdiffstats
path: root/drivers/dma/pl330.c
diff options
context:
space:
mode:
authorLars-Peter Clausen <lars@metafoo.de>2014-07-06 14:32:18 -0400
committerVinod Koul <vinod.koul@intel.com>2014-07-15 12:31:02 -0400
commit585a9d0b43d109ad76c0e43eae0fbe5ec3196246 (patch)
treef6d17796832981acddcbf5ca17be0a80192a6455 /drivers/dma/pl330.c
parent653e67f7e5e008258ff65c2067460cc9e8ee8f94 (diff)
dmaengine: pl330: Use dma_transfer_direction instead of custom pl330_reqtype
The pl330 driver has the custom pl330_reqtype enum which has the same possible settings as the generic dma_transfer_direction enum. Switching over to the generic enum internally makes it possible to directly initialize it from the transfer request direction. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/pl330.c')
-rw-r--r--drivers/dma/pl330.c25
1 files changed, 8 insertions, 17 deletions
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 73fa9b7a10ab..3aff676af853 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -63,13 +63,6 @@ enum pl330_byteswap {
63 SWAP_16, 63 SWAP_16,
64}; 64};
65 65
66enum pl330_reqtype {
67 MEMTOMEM,
68 MEMTODEV,
69 DEVTOMEM,
70 DEVTODEV,
71};
72
73/* Register and Bit field Definitions */ 66/* Register and Bit field Definitions */
74#define DS 0x0 67#define DS 0x0
75#define DS_ST_STOP 0x0 68#define DS_ST_STOP 0x0
@@ -378,7 +371,7 @@ enum pl330_op_err {
378 371
379/* A request defining Scatter-Gather List ending with NULL xfer. */ 372/* A request defining Scatter-Gather List ending with NULL xfer. */
380struct pl330_req { 373struct pl330_req {
381 enum pl330_reqtype rqtype; 374 enum dma_transfer_direction rqtype;
382 /* Index of peripheral for the xfer. */ 375 /* Index of peripheral for the xfer. */
383 unsigned peri:5; 376 unsigned peri:5;
384 /* Unique token for this xfer, set by the client. */ 377 /* Unique token for this xfer, set by the client. */
@@ -1296,13 +1289,13 @@ static int _bursts(unsigned dry_run, u8 buf[],
1296 int off = 0; 1289 int off = 0;
1297 1290
1298 switch (pxs->r->rqtype) { 1291 switch (pxs->r->rqtype) {
1299 case MEMTODEV: 1292 case DMA_MEM_TO_DEV:
1300 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc); 1293 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1301 break; 1294 break;
1302 case DEVTOMEM: 1295 case DMA_DEV_TO_MEM:
1303 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc); 1296 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1304 break; 1297 break;
1305 case MEMTOMEM: 1298 case DMA_MEM_TO_MEM:
1306 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); 1299 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1307 break; 1300 break;
1308 default: 1301 default:
@@ -1543,7 +1536,7 @@ static int pl330_submit_req(void *ch_id, struct pl330_req *r)
1543 } 1536 }
1544 1537
1545 /* If request for non-existing peripheral */ 1538 /* If request for non-existing peripheral */
1546 if (r->rqtype != MEMTOMEM && r->peri >= pi->pcfg.num_peri) { 1539 if (r->rqtype != DMA_MEM_TO_MEM && r->peri >= pi->pcfg.num_peri) {
1547 dev_info(thrd->dmac->pinfo->dev, 1540 dev_info(thrd->dmac->pinfo->dev,
1548 "%s:%d Invalid peripheral(%u)!\n", 1541 "%s:%d Invalid peripheral(%u)!\n",
1549 __func__, __LINE__, r->peri); 1542 __func__, __LINE__, r->peri);
@@ -2698,14 +2691,12 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2698 case DMA_MEM_TO_DEV: 2691 case DMA_MEM_TO_DEV:
2699 desc->rqcfg.src_inc = 1; 2692 desc->rqcfg.src_inc = 1;
2700 desc->rqcfg.dst_inc = 0; 2693 desc->rqcfg.dst_inc = 0;
2701 desc->req.rqtype = MEMTODEV;
2702 src = dma_addr; 2694 src = dma_addr;
2703 dst = pch->fifo_addr; 2695 dst = pch->fifo_addr;
2704 break; 2696 break;
2705 case DMA_DEV_TO_MEM: 2697 case DMA_DEV_TO_MEM:
2706 desc->rqcfg.src_inc = 0; 2698 desc->rqcfg.src_inc = 0;
2707 desc->rqcfg.dst_inc = 1; 2699 desc->rqcfg.dst_inc = 1;
2708 desc->req.rqtype = DEVTOMEM;
2709 src = pch->fifo_addr; 2700 src = pch->fifo_addr;
2710 dst = dma_addr; 2701 dst = dma_addr;
2711 break; 2702 break;
@@ -2713,6 +2704,7 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2713 break; 2704 break;
2714 } 2705 }
2715 2706
2707 desc->req.rqtype = direction;
2716 desc->rqcfg.brst_size = pch->burst_sz; 2708 desc->rqcfg.brst_size = pch->burst_sz;
2717 desc->rqcfg.brst_len = 1; 2709 desc->rqcfg.brst_len = 1;
2718 fill_px(&desc->px, dst, src, period_len); 2710 fill_px(&desc->px, dst, src, period_len);
@@ -2754,7 +2746,7 @@ pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2754 2746
2755 desc->rqcfg.src_inc = 1; 2747 desc->rqcfg.src_inc = 1;
2756 desc->rqcfg.dst_inc = 1; 2748 desc->rqcfg.dst_inc = 1;
2757 desc->req.rqtype = MEMTOMEM; 2749 desc->req.rqtype = DMA_MEM_TO_MEM;
2758 2750
2759 /* Select max possible burst size */ 2751 /* Select max possible burst size */
2760 burst = pi->pcfg.data_bus_width / 8; 2752 burst = pi->pcfg.data_bus_width / 8;
@@ -2838,19 +2830,18 @@ pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2838 if (direction == DMA_MEM_TO_DEV) { 2830 if (direction == DMA_MEM_TO_DEV) {
2839 desc->rqcfg.src_inc = 1; 2831 desc->rqcfg.src_inc = 1;
2840 desc->rqcfg.dst_inc = 0; 2832 desc->rqcfg.dst_inc = 0;
2841 desc->req.rqtype = MEMTODEV;
2842 fill_px(&desc->px, 2833 fill_px(&desc->px,
2843 addr, sg_dma_address(sg), sg_dma_len(sg)); 2834 addr, sg_dma_address(sg), sg_dma_len(sg));
2844 } else { 2835 } else {
2845 desc->rqcfg.src_inc = 0; 2836 desc->rqcfg.src_inc = 0;
2846 desc->rqcfg.dst_inc = 1; 2837 desc->rqcfg.dst_inc = 1;
2847 desc->req.rqtype = DEVTOMEM;
2848 fill_px(&desc->px, 2838 fill_px(&desc->px,
2849 sg_dma_address(sg), addr, sg_dma_len(sg)); 2839 sg_dma_address(sg), addr, sg_dma_len(sg));
2850 } 2840 }
2851 2841
2852 desc->rqcfg.brst_size = pch->burst_sz; 2842 desc->rqcfg.brst_size = pch->burst_sz;
2853 desc->rqcfg.brst_len = 1; 2843 desc->rqcfg.brst_len = 1;
2844 desc->req.rqtype = direction;
2854 } 2845 }
2855 2846
2856 /* Return the last desc in the chain */ 2847 /* Return the last desc in the chain */