summaryrefslogtreecommitdiffstats
path: root/drivers/dma/pl330.c
diff options
context:
space:
mode:
authorJon Medhurst <tixy@linaro.org>2014-11-07 13:05:17 -0500
committerVinod Koul <vinod.koul@intel.com>2014-11-17 02:31:09 -0500
commit137bd11090d89b3a3ef4bdb7a6cf964ffc797517 (patch)
tree1f64fa0aafa630d853c34904bc192e0151261a36 /drivers/dma/pl330.c
parent1f9cd915b64bb95f7b41667b4bf8b22f0a0a557b (diff)
dmaengine: pl330: Align DMA memcpy operations to MFIFO width
The algorithm used for programming the DMA Controller doesn't take into consideration the requirements of transfers that are not aligned to the bus width. This failure may result in DMA transferring one too few MFIFO entries (so too few bytes are copied) or the DMA trying to write one too many MFIFO entries and hanging because this is never provided. See "MFIFO Usage Overview" chapter in the the TRM for "CoreLink DMA Controller DMA-330", Revision r1p1. We work around these shortcomings by making sure we pick a burst size and length which ensures no bursts straddle an MFIFO entry. Signed-off-by: Jon Medhurst <tixy@linaro.org> [squashed linker error "undefined reference to `__aeabi_uldivmod] Reported-by: kbuild test robot <fengguang.wu@intel.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/pl330.c')
-rw-r--r--drivers/dma/pl330.c17
1 files changed, 13 insertions, 4 deletions
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 4839bfa74a10..81505420bde4 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -2459,16 +2459,25 @@ pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2459 /* Select max possible burst size */ 2459 /* Select max possible burst size */
2460 burst = pl330->pcfg.data_bus_width / 8; 2460 burst = pl330->pcfg.data_bus_width / 8;
2461 2461
2462 while (burst > 1) { 2462 /*
2463 if (!(len % burst)) 2463 * Make sure we use a burst size that aligns with all the memcpy
2464 break; 2464 * parameters because our DMA programming algorithm doesn't cope with
2465 * transfers which straddle an entry in the DMA device's MFIFO.
2466 */
2467 while ((src | dst | len) & (burst - 1))
2465 burst /= 2; 2468 burst /= 2;
2466 }
2467 2469
2468 desc->rqcfg.brst_size = 0; 2470 desc->rqcfg.brst_size = 0;
2469 while (burst != (1 << desc->rqcfg.brst_size)) 2471 while (burst != (1 << desc->rqcfg.brst_size))
2470 desc->rqcfg.brst_size++; 2472 desc->rqcfg.brst_size++;
2471 2473
2474 /*
2475 * If burst size is smaller than bus width then make sure we only
2476 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2477 */
2478 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2479 desc->rqcfg.brst_len = 1;
2480
2472 desc->rqcfg.brst_len = get_burst_len(desc, len); 2481 desc->rqcfg.brst_len = get_burst_len(desc, len);
2473 2482
2474 desc->txd.flags = flags; 2483 desc->txd.flags = flags;