Merge tag 'powerpc-4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull powerpc updates from Michael Ellerman:
 "A bit of a small release, I suspect in part due to me travelling for
  KS. But my backlog of patches to review is smaller than usual, so I
  think in part folks just didn't send as much this cycle.

  Non-highlights:

   - Five fixes for the >128T address space handling, both to fix bugs
     in our implementation and to bring the semantics exactly into line
     with x86.

  Highlights:

   - Support for a new OPAL call on bare metal machines which gives us a
     true NMI (ie. is not masked by MSR[EE]=0) for debugging etc.

   - Support for Power9 DD2 in the CXL driver.

   - Improvements to machine check handling so that uncorrectable errors
     can be reported into the generic memory_failure() machinery.

   - Some fixes and improvements for VPHN, which is used under PowerVM
     to notify the Linux partition of topology changes.

   - Plumbing to enable TM (transactional memory) without suspend on
     some Power9 processors (PPC_FEATURE2_HTM_NO_SUSPEND).

   - Support for emulating vector loads form cache-inhibited memory, on
     some Power9 revisions.

   - Disable the fast-endian switch "syscall" by default (behind a
     CONFIG), we believe it has never had any users.

   - A major rework of the API drivers use when initiating and waiting
     for long running operations performed by OPAL firmware, and changes
     to the powernv_flash driver to use the new API.

   - Several fixes for the handling of FP/VMX/VSX while processes are
     using transactional memory.

   - Optimisations of TLB range flushes when using the radix MMU on
     Power9.

   - Improvements to the VAS facility used to access coprocessors on
     Power9, and related improvements to the way the NX crypto driver
     handles requests.

   - Implementation of PMEM_API and UACCESS_FLUSHCACHE for 64-bit.

  Thanks to: Alexey Kardashevskiy, Alistair Popple, Allen Pais, Andrew
  Donnellan, Aneesh Kumar K.V, Arnd Bergmann, Balbir Singh, Benjamin
  Herrenschmidt, Breno Leitao, Christophe Leroy, Christophe Lombard,
  Cyril Bur, Frederic Barrat, Gautham R. Shenoy, Geert Uytterhoeven,
  Guilherme G. Piccoli, Gustavo Romero, Haren Myneni, Joel Stanley,
  Kamalesh Babulal, Kautuk Consul, Markus Elfring, Masami Hiramatsu,
  Michael Bringmann, Michael Neuling, Michal Suchanek, Naveen N. Rao,
  Nicholas Piggin, Oliver O'Halloran, Paul Mackerras, Pedro Miraglia
  Franco de Carvalho, Philippe Bergheaud, Sandipan Das, Seth Forshee,
  Shriya, Stephen Rothwell, Stewart Smith, Sukadev Bhattiprolu, Tyrel
  Datwyler, Vaibhav Jain, Vaidyanathan Srinivasan, and William A.
  Kennington III"

* tag 'powerpc-4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (151 commits)
  powerpc/64s: Fix Power9 DD2.0 workarounds by adding DD2.1 feature
  powerpc/64s: Fix masking of SRR1 bits on instruction fault
  powerpc/64s: mm_context.addr_limit is only used on hash
  powerpc/64s/radix: Fix 128TB-512TB virtual address boundary case allocation
  powerpc/64s/hash: Allow MAP_FIXED allocations to cross 128TB boundary
  powerpc/64s/hash: Fix fork() with 512TB process address space
  powerpc/64s/hash: Fix 128TB-512TB virtual address boundary case allocation
  powerpc/64s/hash: Fix 512T hint detection to use >= 128T
  powerpc: Fix DABR match on hash based systems
  powerpc/signal: Properly handle return value from uprobe_deny_signal()
  powerpc/fadump: use kstrtoint to handle sysfs store
  powerpc/lib: Implement UACCESS_FLUSHCACHE API
  powerpc/lib: Implement PMEM API
  powerpc/powernv/npu: Don't explicitly flush nmmu tlb
  powerpc/powernv/npu: Use flush_all_mm() instead of flush_tlb_mm()
  powerpc/powernv/idle: Round up latency and residency values
  powerpc/kprobes: refactor kprobe_lookup_name for safer string operations
  powerpc/kprobes: Blacklist emulate_update_regs() from kprobes
  powerpc/kprobes: Do not disable interrupts for optprobes and kprobes_on_ftrace
  powerpc/kprobes: Disable preemption before invoking probe handler for optprobes
  ...

2 files changed, 72 insertions, 97 deletions

diff --git a/drivers/crypto/nx/nx-842-powernv.c b/drivers/crypto/nx/nx-842-powernv.c
index 0f20f5ec9617..f2246a5abcf6 100644
--- a/drivers/crypto/nx/nx-842-powernv.c
+++ b/drivers/crypto/nx/nx-842-powernv.c
@@ -46,7 +46,6 @@ struct nx842_workmem {
 
         ktime_t start;
 
-        struct vas_window *txwin;       /* Used with VAS function */
         char padding[WORKMEM_ALIGN]; /* unused, to allow alignment */
 } __packed __aligned(WORKMEM_ALIGN);
 
@@ -65,7 +64,7 @@ struct nx842_coproc {
  * Send the request to NX engine on the chip for the corresponding CPU
  * where the process is executing. Use with VAS function.
  */
-static DEFINE_PER_CPU(struct nx842_coproc *, coproc_inst);
+static DEFINE_PER_CPU(struct vas_window *, cpu_txwin);
 
 /* no cpu hotplug on powernv, so this list never changes after init */
 static LIST_HEAD(nx842_coprocs);
@@ -586,16 +585,11 @@ static int nx842_exec_vas(const unsigned char *in, unsigned int inlen,
         ccw = SET_FIELD(CCW_FC_842, ccw, fc);
         crb->ccw = cpu_to_be32(ccw);
 
-        txwin = wmem->txwin;
-        /* shoudn't happen, we don't load without a coproc */
-        if (!txwin) {
-                pr_err_ratelimited("NX-842 coprocessor is not available");
-                return -ENODEV;
-        }
-
         do {
                 wmem->start = ktime_get();
                 preempt_disable();
+                txwin = this_cpu_read(cpu_txwin);
+
                 /*
                  * VAS copy CRB into L2 cache. Refer <asm/vas.h>.
                  * @crb and @offset.
@@ -689,25 +683,6 @@ static inline void nx842_add_coprocs_list(struct nx842_coproc *coproc,
         list_add(&coproc->list, &nx842_coprocs);
 }
 
-/*
- * Identify chip ID for each CPU and save coprocesor adddress for the
- * corresponding NX engine in percpu coproc_inst.
- * coproc_inst is used in crypto_init to open send window on the NX instance
- * for the corresponding CPU / chip where the open request is executed.
- */
-static void nx842_set_per_cpu_coproc(struct nx842_coproc *coproc)
-{
-        unsigned int i, chip_id;
-
-        for_each_possible_cpu(i) {
-                chip_id = cpu_to_chip_id(i);
-
-                if (coproc->chip_id == chip_id)
-                        per_cpu(coproc_inst, i) = coproc;
-        }
-}
-
-
 static struct vas_window *nx842_alloc_txwin(struct nx842_coproc *coproc)
 {
         struct vas_window *txwin = NULL;
@@ -725,15 +700,58 @@ static struct vas_window *nx842_alloc_txwin(struct nx842_coproc *coproc)
          * Open a VAS send window which is used to send request to NX.
          */
         txwin = vas_tx_win_open(coproc->vas.id, coproc->ct, &txattr);
-        if (IS_ERR(txwin)) {
+        if (IS_ERR(txwin))
                 pr_err("ibm,nx-842: Can not open TX window: %ld\n",
                                 PTR_ERR(txwin));
-                return NULL;
-        }
 
         return txwin;
 }
 
+/*
+ * Identify chip ID for each CPU, open send wndow for the corresponding NX
+ * engine and save txwin in percpu cpu_txwin.
+ * cpu_txwin is used in copy/paste operation for each compression /
+ * decompression request.
+ */
+static int nx842_open_percpu_txwins(void)
+{
+        struct nx842_coproc *coproc, *n;
+        unsigned int i, chip_id;
+
+        for_each_possible_cpu(i) {
+                struct vas_window *txwin = NULL;
+
+                chip_id = cpu_to_chip_id(i);
+
+                list_for_each_entry_safe(coproc, n, &nx842_coprocs, list) {
+                        /*
+                         * Kernel requests use only high priority FIFOs. So
+                         * open send windows for these FIFOs.
+                         */
+
+                        if (coproc->ct != VAS_COP_TYPE_842_HIPRI)
+                                continue;
+
+                        if (coproc->chip_id == chip_id) {
+                                txwin = nx842_alloc_txwin(coproc);
+                                if (IS_ERR(txwin))
+                                        return PTR_ERR(txwin);
+
+                                per_cpu(cpu_txwin, i) = txwin;
+                                break;
+                        }
+                }
+
+                if (!per_cpu(cpu_txwin, i)) {
+                        /* shoudn't happen, Each chip will have NX engine */
+                        pr_err("NX engine is not availavle for CPU %d\n", i);
+                        return -EINVAL;
+                }
+        }
+
+        return 0;
+}
+
 static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
                                         int vasid)
 {
@@ -819,14 +837,6 @@ static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
         coproc->vas.id = vasid;
         nx842_add_coprocs_list(coproc, chip_id);
 
-        /*
-         * Kernel requests use only high priority FIFOs. So save coproc
-         * info in percpu coproc_inst which will be used to open send
-         * windows for crypto open requests later.
-         */
-        if (coproc->ct == VAS_COP_TYPE_842_HIPRI)
-                nx842_set_per_cpu_coproc(coproc);
-
         return 0;
 
 err_out:
@@ -847,24 +857,12 @@ static int __init nx842_powernv_probe_vas(struct device_node *pn)
                 return -EINVAL;
         }
 
-        for_each_compatible_node(dn, NULL, "ibm,power9-vas-x") {
-                if (of_get_ibm_chip_id(dn) == chip_id)
-                        break;
-        }
-
-        if (!dn) {
-                pr_err("Missing VAS device node\n");
+        vasid = chip_to_vas_id(chip_id);
+        if (vasid < 0) {
+                pr_err("Unable to map chip_id %d to vasid\n", chip_id);
                 return -EINVAL;
         }
 
-        if (of_property_read_u32(dn, "ibm,vas-id", &vasid)) {
-                pr_err("Missing ibm,vas-id device property\n");
-                of_node_put(dn);
-                return -EINVAL;
-        }
-
-        of_node_put(dn);
-
         for_each_child_of_node(pn, dn) {
                 if (of_device_is_compatible(dn, "ibm,p9-nx-842")) {
                         ret = vas_cfg_coproc_info(dn, chip_id, vasid);
@@ -928,6 +926,19 @@ static int __init nx842_powernv_probe(struct device_node *dn)
 static void nx842_delete_coprocs(void)
 {
         struct nx842_coproc *coproc, *n;
+        struct vas_window *txwin;
+        int i;
+
+        /*
+         * close percpu txwins that are opened for the corresponding coproc.
+         */
+        for_each_possible_cpu(i) {
+                txwin = per_cpu(cpu_txwin, i);
+                if (txwin)
+                        vas_win_close(txwin);
+
+                per_cpu(cpu_txwin, i) = 0;
+        }
 
         list_for_each_entry_safe(coproc, n, &nx842_coprocs, list) {
                 if (coproc->vas.rxwin)
@@ -954,46 +965,6 @@ static struct nx842_driver nx842_powernv_driver = {
         .decompress =   nx842_powernv_decompress,
 };
 
-static int nx842_powernv_crypto_init_vas(struct crypto_tfm *tfm)
-{
-        struct nx842_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-        struct nx842_workmem *wmem;
-        struct nx842_coproc *coproc;
-        int ret;
-
-        ret = nx842_crypto_init(tfm, &nx842_powernv_driver);
-
-        if (ret)
-                return ret;
-
-        wmem = PTR_ALIGN((struct nx842_workmem *)ctx->wmem, WORKMEM_ALIGN);
-        coproc = per_cpu(coproc_inst, smp_processor_id());
-
-        ret = -EINVAL;
-        if (coproc && coproc->vas.rxwin) {
-                wmem->txwin = nx842_alloc_txwin(coproc);
-                if (!IS_ERR(wmem->txwin))
-                        return 0;
-
-                ret = PTR_ERR(wmem->txwin);
-        }
-
-        return ret;
-}
-
-void nx842_powernv_crypto_exit_vas(struct crypto_tfm *tfm)
-{
-        struct nx842_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-        struct nx842_workmem *wmem;
-
-        wmem = PTR_ALIGN((struct nx842_workmem *)ctx->wmem, WORKMEM_ALIGN);
-
-        if (wmem && wmem->txwin)
-                vas_win_close(wmem->txwin);
-
-        nx842_crypto_exit(tfm);
-}
-
 static int nx842_powernv_crypto_init(struct crypto_tfm *tfm)
 {
         return nx842_crypto_init(tfm, &nx842_powernv_driver);
@@ -1044,9 +1015,13 @@ static __init int nx842_powernv_init(void)
 
                 nx842_powernv_exec = nx842_exec_icswx;
         } else {
+                ret = nx842_open_percpu_txwins();
+                if (ret) {
+                        nx842_delete_coprocs();
+                        return ret;
+                }
+
                 nx842_powernv_exec = nx842_exec_vas;
-                nx842_powernv_alg.cra_init = nx842_powernv_crypto_init_vas;
-                nx842_powernv_alg.cra_exit = nx842_powernv_crypto_exit_vas;
         }
 
         ret = crypto_register_alg(&nx842_powernv_alg);
diff --git a/drivers/crypto/nx/nx-842.c b/drivers/crypto/nx/nx-842.c
index da3cb8c35ec7..d94e25df503b 100644
--- a/drivers/crypto/nx/nx-842.c
+++ b/drivers/crypto/nx/nx-842.c
@@ -116,7 +116,7 @@ int nx842_crypto_init(struct crypto_tfm *tfm, struct nx842_driver *driver)
 
         spin_lock_init(&ctx->lock);
         ctx->driver = driver;
-        ctx->wmem = kzalloc(driver->workmem_size, GFP_KERNEL);
+        ctx->wmem = kmalloc(driver->workmem_size, GFP_KERNEL);
         ctx->sbounce = (u8 *)__get_free_pages(GFP_KERNEL, BOUNCE_BUFFER_ORDER);
         ctx->dbounce = (u8 *)__get_free_pages(GFP_KERNEL, BOUNCE_BUFFER_ORDER);
         if (!ctx->wmem || !ctx->sbounce || !ctx->dbounce) {