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author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2012-09-03 02:26:33 -0400 |
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committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2012-09-03 02:26:33 -0400 |
commit | c50e86ce7c2961a41f2f7aa6e4fd6c99229ba205 (patch) | |
tree | 4ea36009719bd8fc523239fe1bdccb90f0dce3ae /drivers/crypto/atmel-sha-regs.h | |
parent | 14d33d384693eb6083396199de516fdef320f7af (diff) | |
parent | 4cbe5a555fa58a79b6ecbb6c531b8bab0650778d (diff) |
Merge tag 'v3.6-rc4'
Merge 3.6-rc4 to get latest OMAP and device tree fixes.
Diffstat (limited to 'drivers/crypto/atmel-sha-regs.h')
-rw-r--r-- | drivers/crypto/atmel-sha-regs.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/drivers/crypto/atmel-sha-regs.h b/drivers/crypto/atmel-sha-regs.h new file mode 100644 index 000000000000..dc53a20d7da1 --- /dev/null +++ b/drivers/crypto/atmel-sha-regs.h | |||
@@ -0,0 +1,46 @@ | |||
1 | #ifndef __ATMEL_SHA_REGS_H__ | ||
2 | #define __ATMEL_SHA_REGS_H__ | ||
3 | |||
4 | #define SHA_REG_DIGEST(x) (0x80 + ((x) * 0x04)) | ||
5 | #define SHA_REG_DIN(x) (0x40 + ((x) * 0x04)) | ||
6 | |||
7 | #define SHA_CR 0x00 | ||
8 | #define SHA_CR_START (1 << 0) | ||
9 | #define SHA_CR_FIRST (1 << 4) | ||
10 | #define SHA_CR_SWRST (1 << 8) | ||
11 | |||
12 | #define SHA_MR 0x04 | ||
13 | #define SHA_MR_MODE_MASK (0x3 << 0) | ||
14 | #define SHA_MR_MODE_MANUAL 0x0 | ||
15 | #define SHA_MR_MODE_AUTO 0x1 | ||
16 | #define SHA_MR_MODE_PDC 0x2 | ||
17 | #define SHA_MR_DUALBUFF (1 << 3) | ||
18 | #define SHA_MR_PROCDLY (1 << 4) | ||
19 | #define SHA_MR_ALGO_SHA1 (0 << 8) | ||
20 | #define SHA_MR_ALGO_SHA256 (1 << 8) | ||
21 | |||
22 | #define SHA_IER 0x10 | ||
23 | #define SHA_IDR 0x14 | ||
24 | #define SHA_IMR 0x18 | ||
25 | #define SHA_ISR 0x1C | ||
26 | #define SHA_INT_DATARDY (1 << 0) | ||
27 | #define SHA_INT_ENDTX (1 << 1) | ||
28 | #define SHA_INT_TXBUFE (1 << 2) | ||
29 | #define SHA_INT_URAD (1 << 8) | ||
30 | #define SHA_ISR_URAT_MASK (0x7 << 12) | ||
31 | #define SHA_ISR_URAT_IDR (0x0 << 12) | ||
32 | #define SHA_ISR_URAT_ODR (0x1 << 12) | ||
33 | #define SHA_ISR_URAT_MR (0x2 << 12) | ||
34 | #define SHA_ISR_URAT_WO (0x5 << 12) | ||
35 | |||
36 | #define SHA_TPR 0x108 | ||
37 | #define SHA_TCR 0x10C | ||
38 | #define SHA_TNPR 0x118 | ||
39 | #define SHA_TNCR 0x11C | ||
40 | #define SHA_PTCR 0x120 | ||
41 | #define SHA_PTCR_TXTEN (1 << 8) | ||
42 | #define SHA_PTCR_TXTDIS (1 << 9) | ||
43 | #define SHA_PTSR 0x124 | ||
44 | #define SHA_PTSR_TXTEN (1 << 8) | ||
45 | |||
46 | #endif /* __ATMEL_SHA_REGS_H__ */ | ||