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authorJason Gunthorpe <jgg@mellanox.com>2019-08-21 13:12:29 -0400
committerJason Gunthorpe <jgg@mellanox.com>2019-08-21 19:58:18 -0400
commitdaa138a58c802e7b4c2fb73f9b85bb082616ef43 (patch)
treebe913e8e3745bb367d2ba371598f447649102cfc /drivers/clocksource/timer-riscv.c
parent6869b7b206595ae0e326f59719090351eb8f4f5d (diff)
parentfba0e448a2c5b297a4ddc1ec4e48f4aa6600a1c9 (diff)
Merge branch 'odp_fixes' into hmm.git
From rdma.git Jason Gunthorpe says: ==================== This is a collection of general cleanups for ODP to clarify some of the flows around umem creation and use of the interval tree. ==================== The branch is based on v5.3-rc5 due to dependencies, and is being taken into hmm.git due to dependencies in the next patches. * odp_fixes: RDMA/mlx5: Use odp instead of mr->umem in pagefault_mr RDMA/mlx5: Use ib_umem_start instead of umem.address RDMA/core: Make invalidate_range a device operation RDMA/odp: Use kvcalloc for the dma_list and page_list RDMA/odp: Check for overflow when computing the umem_odp end RDMA/odp: Provide ib_umem_odp_release() to undo the allocs RDMA/odp: Split creating a umem_odp from ib_umem_get RDMA/odp: Make the three ways to create a umem_odp clear RMDA/odp: Consolidate umem_odp initialization RDMA/odp: Make it clearer when a umem is an implicit ODP umem RDMA/odp: Iterate over the whole rbtree directly RDMA/odp: Use the common interval tree library instead of generic RDMA/mlx5: Fix MR npages calculation for IB_ACCESS_HUGETLB Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
Diffstat (limited to 'drivers/clocksource/timer-riscv.c')
-rw-r--r--drivers/clocksource/timer-riscv.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 5e6038fbf115..09e031176bc6 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -55,7 +55,7 @@ static u64 riscv_sched_clock(void)
55 return get_cycles64(); 55 return get_cycles64();
56} 56}
57 57
58static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = { 58static struct clocksource riscv_clocksource = {
59 .name = "riscv_clocksource", 59 .name = "riscv_clocksource",
60 .rating = 300, 60 .rating = 300,
61 .mask = CLOCKSOURCE_MASK(64), 61 .mask = CLOCKSOURCE_MASK(64),
@@ -92,7 +92,6 @@ void riscv_timer_interrupt(void)
92static int __init riscv_timer_init_dt(struct device_node *n) 92static int __init riscv_timer_init_dt(struct device_node *n)
93{ 93{
94 int cpuid, hartid, error; 94 int cpuid, hartid, error;
95 struct clocksource *cs;
96 95
97 hartid = riscv_of_processor_hartid(n); 96 hartid = riscv_of_processor_hartid(n);
98 if (hartid < 0) { 97 if (hartid < 0) {
@@ -112,8 +111,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
112 111
113 pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", 112 pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
114 __func__, cpuid, hartid); 113 __func__, cpuid, hartid);
115 cs = per_cpu_ptr(&riscv_clocksource, cpuid); 114 error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
116 error = clocksource_register_hz(cs, riscv_timebase);
117 if (error) { 115 if (error) {
118 pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", 116 pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
119 error, cpuid); 117 error, cpuid);