Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull timer updates from Thomas Gleixner:
 "A rather large update for timers/timekeeping:

   - compat syscall consolidation (Al Viro)

   - Posix timer consolidation (Christoph Helwig / Thomas Gleixner)

   - Cleanup of the device tree based initialization for clockevents and
     clocksources (Daniel Lezcano)

   - Consolidation of the FTTMR010 clocksource/event driver (Linus
     Walleij)

   - The usual set of small fixes and updates all over the place"

* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (93 commits)
  timers: Make the cpu base lock raw
  clocksource/drivers/mips-gic-timer: Fix an error code in 'gic_clocksource_of_init()'
  clocksource/drivers/fsl_ftm_timer: Unmap region obtained by of_iomap
  clocksource/drivers/tcb_clksrc: Make IO endian agnostic
  clocksource/drivers/sun4i: Switch to the timer-of common init
  clocksource/drivers/timer-of: Fix invalid iomap check
  Revert "ktime: Simplify ktime_compare implementation"
  clocksource/drivers: Fix uninitialized variable use in timer_of_init
  kselftests: timers: Add test for frequency step
  kselftests: timers: Fix inconsistency-check to not ignore first timestamp
  time: Add warning about imminent deprecation of CONFIG_GENERIC_TIME_VSYSCALL_OLD
  time: Clean up CLOCK_MONOTONIC_RAW time handling
  posix-cpu-timers: Make timespec to nsec conversion safe
  itimer: Make timeval to nsec conversion range limited
  timers: Fix parameter description of try_to_del_timer_sync()
  ktime: Simplify ktime_compare implementation
  clocksource/drivers/fttmr010: Factor out clock read code
  clocksource/drivers/fttmr010: Implement delay timer
  clocksource/drivers: Add timer-of common init routine
  clocksource/drivers/tcb_clksrc: Save timer context on suspend/resume
  ...

1 files changed, 289 insertions, 187 deletions

diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c
index b4a6f1e4bc54..66dd909960c6 100644
--- a/drivers/clocksource/timer-fttmr010.c
+++ b/drivers/clocksource/timer-fttmr010.c
@@ -11,12 +11,13 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
-#include <linux/mfd/syscon.h>
-#include <linux/regmap.h>
 #include <linux/clockchips.h>
 #include <linux/clocksource.h>
 #include <linux/sched_clock.h>
 #include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
 
 /*
  * Register definitions for the timers
@@ -37,267 +38,368 @@
 #define TIMER_INTR_STATE        (0x34)
 #define TIMER_INTR_MASK         (0x38)
 
-#define TIMER_1_CR_ENABLE       (1 << 0)
-#define TIMER_1_CR_CLOCK        (1 << 1)
-#define TIMER_1_CR_INT          (1 << 2)
-#define TIMER_2_CR_ENABLE       (1 << 3)
-#define TIMER_2_CR_CLOCK        (1 << 4)
-#define TIMER_2_CR_INT          (1 << 5)
-#define TIMER_3_CR_ENABLE       (1 << 6)
-#define TIMER_3_CR_CLOCK        (1 << 7)
-#define TIMER_3_CR_INT          (1 << 8)
-#define TIMER_1_CR_UPDOWN       (1 << 9)
-#define TIMER_2_CR_UPDOWN       (1 << 10)
-#define TIMER_3_CR_UPDOWN       (1 << 11)
-#define TIMER_DEFAULT_FLAGS     (TIMER_1_CR_UPDOWN | \
-                                 TIMER_3_CR_ENABLE | \
-                                 TIMER_3_CR_UPDOWN)
-
-#define TIMER_1_INT_MATCH1      (1 << 0)
-#define TIMER_1_INT_MATCH2      (1 << 1)
-#define TIMER_1_INT_OVERFLOW    (1 << 2)
-#define TIMER_2_INT_MATCH1      (1 << 3)
-#define TIMER_2_INT_MATCH2      (1 << 4)
-#define TIMER_2_INT_OVERFLOW    (1 << 5)
-#define TIMER_3_INT_MATCH1      (1 << 6)
-#define TIMER_3_INT_MATCH2      (1 << 7)
-#define TIMER_3_INT_OVERFLOW    (1 << 8)
+#define TIMER_1_CR_ENABLE       BIT(0)
+#define TIMER_1_CR_CLOCK        BIT(1)
+#define TIMER_1_CR_INT          BIT(2)
+#define TIMER_2_CR_ENABLE       BIT(3)
+#define TIMER_2_CR_CLOCK        BIT(4)
+#define TIMER_2_CR_INT          BIT(5)
+#define TIMER_3_CR_ENABLE       BIT(6)
+#define TIMER_3_CR_CLOCK        BIT(7)
+#define TIMER_3_CR_INT          BIT(8)
+#define TIMER_1_CR_UPDOWN       BIT(9)
+#define TIMER_2_CR_UPDOWN       BIT(10)
+#define TIMER_3_CR_UPDOWN       BIT(11)
+
+/*
+ * The Aspeed AST2400 moves bits around in the control register
+ * and lacks bits for setting the timer to count upwards.
+ */
+#define TIMER_1_CR_ASPEED_ENABLE        BIT(0)
+#define TIMER_1_CR_ASPEED_CLOCK         BIT(1)
+#define TIMER_1_CR_ASPEED_INT           BIT(2)
+#define TIMER_2_CR_ASPEED_ENABLE        BIT(4)
+#define TIMER_2_CR_ASPEED_CLOCK         BIT(5)
+#define TIMER_2_CR_ASPEED_INT           BIT(6)
+#define TIMER_3_CR_ASPEED_ENABLE        BIT(8)
+#define TIMER_3_CR_ASPEED_CLOCK         BIT(9)
+#define TIMER_3_CR_ASPEED_INT           BIT(10)
+
+#define TIMER_1_INT_MATCH1      BIT(0)
+#define TIMER_1_INT_MATCH2      BIT(1)
+#define TIMER_1_INT_OVERFLOW    BIT(2)
+#define TIMER_2_INT_MATCH1      BIT(3)
+#define TIMER_2_INT_MATCH2      BIT(4)
+#define TIMER_2_INT_OVERFLOW    BIT(5)
+#define TIMER_3_INT_MATCH1      BIT(6)
+#define TIMER_3_INT_MATCH2      BIT(7)
+#define TIMER_3_INT_OVERFLOW    BIT(8)
 #define TIMER_INT_ALL_MASK      0x1ff
 
-static unsigned int tick_rate;
-static void __iomem *base;
+struct fttmr010 {
+        void __iomem *base;
+        unsigned int tick_rate;
+        bool count_down;
+        u32 t1_enable_val;
+        struct clock_event_device clkevt;
+#ifdef CONFIG_ARM
+        struct delay_timer delay_timer;
+#endif
+};
+
+/*
+ * A local singleton used by sched_clock and delay timer reads, which are
+ * fast and stateless
+ */
+static struct fttmr010 *local_fttmr;
+
+static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
+{
+        return container_of(evt, struct fttmr010, clkevt);
+}
+
+static unsigned long fttmr010_read_current_timer_up(void)
+{
+        return readl(local_fttmr->base + TIMER2_COUNT);
+}
+
+static unsigned long fttmr010_read_current_timer_down(void)
+{
+        return ~readl(local_fttmr->base + TIMER2_COUNT);
+}
+
+static u64 notrace fttmr010_read_sched_clock_up(void)
+{
+        return fttmr010_read_current_timer_up();
+}
 
-static u64 notrace fttmr010_read_sched_clock(void)
+static u64 notrace fttmr010_read_sched_clock_down(void)
 {
-        return readl(base + TIMER3_COUNT);
+        return fttmr010_read_current_timer_down();
 }
 
 static int fttmr010_timer_set_next_event(unsigned long cycles,
                                        struct clock_event_device *evt)
 {
+        struct fttmr010 *fttmr010 = to_fttmr010(evt);
         u32 cr;
 
-        /* Setup the match register */
-        cr = readl(base + TIMER1_COUNT);
-        writel(cr + cycles, base + TIMER1_MATCH1);
-        if (readl(base + TIMER1_COUNT) - cr > cycles)
-                return -ETIME;
+        /* Stop */
+        cr = readl(fttmr010->base + TIMER_CR);
+        cr &= ~fttmr010->t1_enable_val;
+        writel(cr, fttmr010->base + TIMER_CR);
+
+        /* Setup the match register forward/backward in time */
+        cr = readl(fttmr010->base + TIMER1_COUNT);
+        if (fttmr010->count_down)
+                cr -= cycles;
+        else
+                cr += cycles;
+        writel(cr, fttmr010->base + TIMER1_MATCH1);
+
+        /* Start */
+        cr = readl(fttmr010->base + TIMER_CR);
+        cr |= fttmr010->t1_enable_val;
+        writel(cr, fttmr010->base + TIMER_CR);
 
         return 0;
 }
 
 static int fttmr010_timer_shutdown(struct clock_event_device *evt)
 {
+        struct fttmr010 *fttmr010 = to_fttmr010(evt);
         u32 cr;
 
-        /*
-         * Disable also for oneshot: the set_next() call will arm the timer
-         * instead.
-         */
-        /* Stop timer and interrupt. */
-        cr = readl(base + TIMER_CR);
-        cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
-        writel(cr, base + TIMER_CR);
+        /* Stop */
+        cr = readl(fttmr010->base + TIMER_CR);
+        cr &= ~fttmr010->t1_enable_val;
+        writel(cr, fttmr010->base + TIMER_CR);
+
+        return 0;
+}
+
+static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
+{
+        struct fttmr010 *fttmr010 = to_fttmr010(evt);
+        u32 cr;
+
+        /* Stop */
+        cr = readl(fttmr010->base + TIMER_CR);
+        cr &= ~fttmr010->t1_enable_val;
+        writel(cr, fttmr010->base + TIMER_CR);
 
-        /* Setup counter start from 0 */
-        writel(0, base + TIMER1_COUNT);
-        writel(0, base + TIMER1_LOAD);
+        /* Setup counter start from 0 or ~0 */
+        writel(0, fttmr010->base + TIMER1_COUNT);
+        if (fttmr010->count_down)
+                writel(~0, fttmr010->base + TIMER1_LOAD);
+        else
+                writel(0, fttmr010->base + TIMER1_LOAD);
 
-        /* enable interrupt */
-        cr = readl(base + TIMER_INTR_MASK);
+        /* Enable interrupt */
+        cr = readl(fttmr010->base + TIMER_INTR_MASK);
         cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
         cr |= TIMER_1_INT_MATCH1;
-        writel(cr, base + TIMER_INTR_MASK);
-
-        /* start the timer */
-        cr = readl(base + TIMER_CR);
-        cr |= TIMER_1_CR_ENABLE;
-        writel(cr, base + TIMER_CR);
+        writel(cr, fttmr010->base + TIMER_INTR_MASK);
 
         return 0;
 }
 
 static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
 {
-        u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ);
+        struct fttmr010 *fttmr010 = to_fttmr010(evt);
+        u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
         u32 cr;
 
-        /* Stop timer and interrupt */
-        cr = readl(base + TIMER_CR);
-        cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
-        writel(cr, base + TIMER_CR);
-
-        /* Setup timer to fire at 1/HT intervals. */
-        cr = 0xffffffff - (period - 1);
-        writel(cr, base + TIMER1_COUNT);
-        writel(cr, base + TIMER1_LOAD);
-
-        /* enable interrupt on overflow */
-        cr = readl(base + TIMER_INTR_MASK);
-        cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
-        cr |= TIMER_1_INT_OVERFLOW;
-        writel(cr, base + TIMER_INTR_MASK);
+        /* Stop */
+        cr = readl(fttmr010->base + TIMER_CR);
+        cr &= ~fttmr010->t1_enable_val;
+        writel(cr, fttmr010->base + TIMER_CR);
+
+        /* Setup timer to fire at 1/HZ intervals. */
+        if (fttmr010->count_down) {
+                writel(period, fttmr010->base + TIMER1_LOAD);
+                writel(0, fttmr010->base + TIMER1_MATCH1);
+        } else {
+                cr = 0xffffffff - (period - 1);
+                writel(cr, fttmr010->base + TIMER1_COUNT);
+                writel(cr, fttmr010->base + TIMER1_LOAD);
+
+                /* Enable interrupt on overflow */
+                cr = readl(fttmr010->base + TIMER_INTR_MASK);
+                cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
+                cr |= TIMER_1_INT_OVERFLOW;
+                writel(cr, fttmr010->base + TIMER_INTR_MASK);
+        }
 
         /* Start the timer */
-        cr = readl(base + TIMER_CR);
-        cr |= TIMER_1_CR_ENABLE;
-        cr |= TIMER_1_CR_INT;
-        writel(cr, base + TIMER_CR);
+        cr = readl(fttmr010->base + TIMER_CR);
+        cr |= fttmr010->t1_enable_val;
+        writel(cr, fttmr010->base + TIMER_CR);
 
         return 0;
 }
 
-/* Use TIMER1 as clock event */
-static struct clock_event_device fttmr010_clockevent = {
-        .name                   = "TIMER1",
-        /* Reasonably fast and accurate clock event */
-        .rating                 = 300,
-        .shift                  = 32,
-        .features               = CLOCK_EVT_FEAT_PERIODIC |
-                                  CLOCK_EVT_FEAT_ONESHOT,
-        .set_next_event         = fttmr010_timer_set_next_event,
-        .set_state_shutdown     = fttmr010_timer_shutdown,
-        .set_state_periodic     = fttmr010_timer_set_periodic,
-        .set_state_oneshot      = fttmr010_timer_shutdown,
-        .tick_resume            = fttmr010_timer_shutdown,
-};
-
 /*
  * IRQ handler for the timer
  */
 static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
 {
-        struct clock_event_device *evt = &fttmr010_clockevent;
+        struct clock_event_device *evt = dev_id;
 
         evt->event_handler(evt);
         return IRQ_HANDLED;
 }
 
-static struct irqaction fttmr010_timer_irq = {
-        .name           = "Faraday FTTMR010 Timer Tick",
-        .flags          = IRQF_TIMER,
-        .handler        = fttmr010_timer_interrupt,
-};
-
-static int __init fttmr010_timer_common_init(struct device_node *np)
+static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed)
 {
+        struct fttmr010 *fttmr010;
         int irq;
+        struct clk *clk;
+        int ret;
+        u32 val;
+
+        /*
+         * These implementations require a clock reference.
+         * FIXME: we currently only support clocking using PCLK
+         * and using EXTCLK is not supported in the driver.
+         */
+        clk = of_clk_get_by_name(np, "PCLK");
+        if (IS_ERR(clk)) {
+                pr_err("could not get PCLK\n");
+                return PTR_ERR(clk);
+        }
+        ret = clk_prepare_enable(clk);
+        if (ret) {
+                pr_err("failed to enable PCLK\n");
+                return ret;
+        }
 
-        base = of_iomap(np, 0);
-        if (!base) {
+        fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
+        if (!fttmr010) {
+                ret = -ENOMEM;
+                goto out_disable_clock;
+        }
+        fttmr010->tick_rate = clk_get_rate(clk);
+
+        fttmr010->base = of_iomap(np, 0);
+        if (!fttmr010->base) {
                 pr_err("Can't remap registers");
-                return -ENXIO;
+                ret = -ENXIO;
+                goto out_free;
         }
         /* IRQ for timer 1 */
         irq = irq_of_parse_and_map(np, 0);
         if (irq <= 0) {
                 pr_err("Can't parse IRQ");
-                return -EINVAL;
+                ret = -EINVAL;
+                goto out_unmap;
+        }
+
+        /*
+         * The Aspeed AST2400 moves bits around in the control register,
+         * otherwise it works the same.
+         */
+        if (is_aspeed) {
+                fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE |
+                        TIMER_1_CR_ASPEED_INT;
+                /* Downward not available */
+                fttmr010->count_down = true;
+        } else {
+                fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT;
         }
 
         /*
          * Reset the interrupt mask and status
          */
-        writel(TIMER_INT_ALL_MASK, base + TIMER_INTR_MASK);
-        writel(0, base + TIMER_INTR_STATE);
-        writel(TIMER_DEFAULT_FLAGS, base + TIMER_CR);
+        writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
+        writel(0, fttmr010->base + TIMER_INTR_STATE);
+
+        /*
+         * Enable timer 1 count up, timer 2 count up, except on Aspeed,
+         * where everything just counts down.
+         */
+        if (is_aspeed)
+                val = TIMER_2_CR_ASPEED_ENABLE;
+        else {
+                val = TIMER_2_CR_ENABLE;
+                if (!fttmr010->count_down)
+                        val |= TIMER_1_CR_UPDOWN | TIMER_2_CR_UPDOWN;
+        }
+        writel(val, fttmr010->base + TIMER_CR);
 
         /*
          * Setup free-running clocksource timer (interrupts
          * disabled.)
          */
-        writel(0, base + TIMER3_COUNT);
-        writel(0, base + TIMER3_LOAD);
-        writel(0, base + TIMER3_MATCH1);
-        writel(0, base + TIMER3_MATCH2);
-        clocksource_mmio_init(base + TIMER3_COUNT,
-                              "fttmr010_clocksource", tick_rate,
-                              300, 32, clocksource_mmio_readl_up);
-        sched_clock_register(fttmr010_read_sched_clock, 32, tick_rate);
+        local_fttmr = fttmr010;
+        writel(0, fttmr010->base + TIMER2_COUNT);
+        writel(0, fttmr010->base + TIMER2_MATCH1);
+        writel(0, fttmr010->base + TIMER2_MATCH2);
+
+        if (fttmr010->count_down) {
+                writel(~0, fttmr010->base + TIMER2_LOAD);
+                clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
+                                      "FTTMR010-TIMER2",
+                                      fttmr010->tick_rate,
+                                      300, 32, clocksource_mmio_readl_down);
+                sched_clock_register(fttmr010_read_sched_clock_down, 32,
+                                     fttmr010->tick_rate);
+        } else {
+                writel(0, fttmr010->base + TIMER2_LOAD);
+                clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
+                                      "FTTMR010-TIMER2",
+                                      fttmr010->tick_rate,
+                                      300, 32, clocksource_mmio_readl_up);
+                sched_clock_register(fttmr010_read_sched_clock_up, 32,
+                                     fttmr010->tick_rate);
+        }
 
         /*
-         * Setup clockevent timer (interrupt-driven.)
+         * Setup clockevent timer (interrupt-driven) on timer 1.
          */
-        writel(0, base + TIMER1_COUNT);
-        writel(0, base + TIMER1_LOAD);
-        writel(0, base + TIMER1_MATCH1);
-        writel(0, base + TIMER1_MATCH2);
-        setup_irq(irq, &fttmr010_timer_irq);
-        fttmr010_clockevent.cpumask = cpumask_of(0);
-        clockevents_config_and_register(&fttmr010_clockevent, tick_rate,
+        writel(0, fttmr010->base + TIMER1_COUNT);
+        writel(0, fttmr010->base + TIMER1_LOAD);
+        writel(0, fttmr010->base + TIMER1_MATCH1);
+        writel(0, fttmr010->base + TIMER1_MATCH2);
+        ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
+                          "FTTMR010-TIMER1", &fttmr010->clkevt);
+        if (ret) {
+                pr_err("FTTMR010-TIMER1 no IRQ\n");
+                goto out_unmap;
+        }
+
+        fttmr010->clkevt.name = "FTTMR010-TIMER1";
+        /* Reasonably fast and accurate clock event */
+        fttmr010->clkevt.rating = 300;
+        fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
+                CLOCK_EVT_FEAT_ONESHOT;
+        fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
+        fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
+        fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
+        fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
+        fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
+        fttmr010->clkevt.cpumask = cpumask_of(0);
+        fttmr010->clkevt.irq = irq;
+        clockevents_config_and_register(&fttmr010->clkevt,
+                                        fttmr010->tick_rate,
                                         1, 0xffffffff);
 
-        return 0;
-}
+#ifdef CONFIG_ARM
+        /* Also use this timer for delays */
+        if (fttmr010->count_down)
+                fttmr010->delay_timer.read_current_timer =
+                        fttmr010_read_current_timer_down;
+        else
+                fttmr010->delay_timer.read_current_timer =
+                        fttmr010_read_current_timer_up;
+        fttmr010->delay_timer.freq = fttmr010->tick_rate;
+        register_current_timer_delay(&fttmr010->delay_timer);
+#endif
 
-static int __init fttmr010_timer_of_init(struct device_node *np)
-{
-        /*
-         * These implementations require a clock reference.
-         * FIXME: we currently only support clocking using PCLK
-         * and using EXTCLK is not supported in the driver.
-         */
-        struct clk *clk;
+        return 0;
 
-        clk = of_clk_get_by_name(np, "PCLK");
-        if (IS_ERR(clk)) {
-                pr_err("could not get PCLK");
-                return PTR_ERR(clk);
-        }
-        tick_rate = clk_get_rate(clk);
+out_unmap:
+        iounmap(fttmr010->base);
+out_free:
+        kfree(fttmr010);
+out_disable_clock:
+        clk_disable_unprepare(clk);
 
-        return fttmr010_timer_common_init(np);
+        return ret;
 }
-CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_of_init);
 
-/*
- * Gemini-specific: relevant registers in the global syscon
- */
-#define GLOBAL_STATUS           0x04
-#define CPU_AHB_RATIO_MASK      (0x3 << 18)
-#define CPU_AHB_1_1             (0x0 << 18)
-#define CPU_AHB_3_2             (0x1 << 18)
-#define CPU_AHB_24_13           (0x2 << 18)
-#define CPU_AHB_2_1             (0x3 << 18)
-#define REG_TO_AHB_SPEED(reg)   ((((reg) >> 15) & 0x7) * 10 + 130)
-
-static int __init gemini_timer_of_init(struct device_node *np)
+static __init int aspeed_timer_init(struct device_node *np)
 {
-        static struct regmap *map;
-        int ret;
-        u32 val;
-
-        map = syscon_regmap_lookup_by_phandle(np, "syscon");
-        if (IS_ERR(map)) {
-                pr_err("Can't get regmap for syscon handle\n");
-                return -ENODEV;
-        }
-        ret = regmap_read(map, GLOBAL_STATUS, &val);
-        if (ret) {
-                pr_err("Can't read syscon status register\n");
-                return -ENXIO;
-        }
-
-        tick_rate = REG_TO_AHB_SPEED(val) * 1000000;
-        pr_info("Bus: %dMHz ", tick_rate / 1000000);
-
-        tick_rate /= 6;         /* APB bus run AHB*(1/6) */
-
-        switch (val & CPU_AHB_RATIO_MASK) {
-        case CPU_AHB_1_1:
-                pr_cont("(1/1)\n");
-                break;
-        case CPU_AHB_3_2:
-                pr_cont("(3/2)\n");
-                break;
-        case CPU_AHB_24_13:
-                pr_cont("(24/13)\n");
-                break;
-        case CPU_AHB_2_1:
-                pr_cont("(2/1)\n");
-                break;
-        }
+        return fttmr010_common_init(np, true);
+}
 
-        return fttmr010_timer_common_init(np);
+static __init int fttmr010_timer_init(struct device_node *np)
+{
+        return fttmr010_common_init(np, false);
 }
-CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", gemini_timer_of_init);
+
+TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
+TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
+TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
+TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
+TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);