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authorDavid Müller <dave.mueller@gmx.ch>2019-04-08 09:33:54 -0400
committerStephen Boyd <sboyd@kernel.org>2019-04-10 18:54:12 -0400
commit7c2e07130090ae001a97a6b65597830d6815e93e (patch)
tree49390d3305bda6d110ad8a71a871d36bc43192b3 /drivers/clk/x86
parent9f842abde84d4232d7a1951952dc148bd83f9ada (diff)
clk: x86: Add system specific quirk to mark clocks as critical
Since commit 648e921888ad ("clk: x86: Stop marking clocks as CLK_IS_CRITICAL"), the pmc_plt_clocks of the Bay Trail SoC are unconditionally gated off. Unfortunately this will break systems where these clocks are used for external purposes beyond the kernel's knowledge. Fix it by implementing a system specific quirk to mark the necessary pmc_plt_clks as critical. Fixes: 648e921888ad ("clk: x86: Stop marking clocks as CLK_IS_CRITICAL") Signed-off-by: David Müller <dave.mueller@gmx.ch> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/x86')
-rw-r--r--drivers/clk/x86/clk-pmc-atom.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/clk/x86/clk-pmc-atom.c b/drivers/clk/x86/clk-pmc-atom.c
index d977193842df..19174835693b 100644
--- a/drivers/clk/x86/clk-pmc-atom.c
+++ b/drivers/clk/x86/clk-pmc-atom.c
@@ -165,7 +165,7 @@ static const struct clk_ops plt_clk_ops = {
165}; 165};
166 166
167static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id, 167static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id,
168 void __iomem *base, 168 const struct pmc_clk_data *pmc_data,
169 const char **parent_names, 169 const char **parent_names,
170 int num_parents) 170 int num_parents)
171{ 171{
@@ -184,9 +184,17 @@ static struct clk_plt *plt_clk_register(struct platform_device *pdev, int id,
184 init.num_parents = num_parents; 184 init.num_parents = num_parents;
185 185
186 pclk->hw.init = &init; 186 pclk->hw.init = &init;
187 pclk->reg = base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE; 187 pclk->reg = pmc_data->base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE;
188 spin_lock_init(&pclk->lock); 188 spin_lock_init(&pclk->lock);
189 189
190 /*
191 * On some systems, the pmc_plt_clocks already enabled by the
192 * firmware are being marked as critical to avoid them being
193 * gated by the clock framework.
194 */
195 if (pmc_data->critical && plt_clk_is_enabled(&pclk->hw))
196 init.flags |= CLK_IS_CRITICAL;
197
190 ret = devm_clk_hw_register(&pdev->dev, &pclk->hw); 198 ret = devm_clk_hw_register(&pdev->dev, &pclk->hw);
191 if (ret) { 199 if (ret) {
192 pclk = ERR_PTR(ret); 200 pclk = ERR_PTR(ret);
@@ -332,7 +340,7 @@ static int plt_clk_probe(struct platform_device *pdev)
332 return PTR_ERR(parent_names); 340 return PTR_ERR(parent_names);
333 341
334 for (i = 0; i < PMC_CLK_NUM; i++) { 342 for (i = 0; i < PMC_CLK_NUM; i++) {
335 data->clks[i] = plt_clk_register(pdev, i, pmc_data->base, 343 data->clks[i] = plt_clk_register(pdev, i, pmc_data,
336 parent_names, data->nparents); 344 parent_names, data->nparents);
337 if (IS_ERR(data->clks[i])) { 345 if (IS_ERR(data->clks[i])) {
338 err = PTR_ERR(data->clks[i]); 346 err = PTR_ERR(data->clks[i]);