Merge tag 'v3.6-rc4'

Merge 3.6-rc4 to get latest OMAP and device tree fixes.

1 files changed, 155 insertions, 34 deletions

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8ea11b444528..a9204c69148d 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -30,18 +30,89 @@
 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
 #define div_mask(d)     ((1 << (d->width)) - 1)
+#define is_power_of_two(i)      !(i & ~i)
+
+static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
+{
+        unsigned int maxdiv = 0;
+        const struct clk_div_table *clkt;
+
+        for (clkt = table; clkt->div; clkt++)
+                if (clkt->div > maxdiv)
+                        maxdiv = clkt->div;
+        return maxdiv;
+}
+
+static unsigned int _get_maxdiv(struct clk_divider *divider)
+{
+        if (divider->flags & CLK_DIVIDER_ONE_BASED)
+                return div_mask(divider);
+        if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+                return 1 << div_mask(divider);
+        if (divider->table)
+                return _get_table_maxdiv(divider->table);
+        return div_mask(divider) + 1;
+}
+
+static unsigned int _get_table_div(const struct clk_div_table *table,
+                                                        unsigned int val)
+{
+        const struct clk_div_table *clkt;
+
+        for (clkt = table; clkt->div; clkt++)
+                if (clkt->val == val)
+                        return clkt->div;
+        return 0;
+}
+
+static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
+{
+        if (divider->flags & CLK_DIVIDER_ONE_BASED)
+                return val;
+        if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+                return 1 << val;
+        if (divider->table)
+                return _get_table_div(divider->table, val);
+        return val + 1;
+}
+
+static unsigned int _get_table_val(const struct clk_div_table *table,
+                                                        unsigned int div)
+{
+        const struct clk_div_table *clkt;
+
+        for (clkt = table; clkt->div; clkt++)
+                if (clkt->div == div)
+                        return clkt->val;
+        return 0;
+}
+
+static unsigned int _get_val(struct clk_divider *divider, u8 div)
+{
+        if (divider->flags & CLK_DIVIDER_ONE_BASED)
+                return div;
+        if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+                return __ffs(div);
+        if (divider->table)
+                return  _get_table_val(divider->table, div);
+        return div - 1;
+}
 
 static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
                 unsigned long parent_rate)
 {
         struct clk_divider *divider = to_clk_divider(hw);
-        unsigned int div;
+        unsigned int div, val;
 
-        div = readl(divider->reg) >> divider->shift;
-        div &= div_mask(divider);
+        val = readl(divider->reg) >> divider->shift;
+        val &= div_mask(divider);
 
-        if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
-                div++;
+        div = _get_div(divider, val);
+        if (!div) {
+                WARN(1, "%s: Invalid divisor for clock %s\n", __func__,
+                                                __clk_get_name(hw->clk));
+                return parent_rate;
+        }
 
         return parent_rate / div;
 }
@@ -52,6 +123,26 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
  */
 #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
 
+static bool _is_valid_table_div(const struct clk_div_table *table,
+                                                         unsigned int div)
+{
+        const struct clk_div_table *clkt;
+
+        for (clkt = table; clkt->div; clkt++)
+                if (clkt->div == div)
+                        return true;
+        return false;
+}
+
+static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
+{
+        if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
+                return is_power_of_two(div);
+        if (divider->table)
+                return _is_valid_table_div(divider->table, div);
+        return true;
+}
+
 static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
                 unsigned long *best_parent_rate)
 {
@@ -62,10 +153,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
         if (!rate)
                 rate = 1;
 
-        maxdiv = (1 << divider->width);
-
-        if (divider->flags & CLK_DIVIDER_ONE_BASED)
-                maxdiv--;
+        maxdiv = _get_maxdiv(divider);
 
         if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
                 parent_rate = *best_parent_rate;
@@ -82,6 +170,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
         maxdiv = min(ULONG_MAX / rate, maxdiv);
 
         for (i = 1; i <= maxdiv; i++) {
+                if (!_is_valid_div(divider, i))
+                        continue;
                 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
                                 MULT_ROUND_UP(rate, i));
                 now = parent_rate / i;
@@ -93,9 +183,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
         }
 
         if (!bestdiv) {
-                bestdiv = (1 << divider->width);
-                if (divider->flags & CLK_DIVIDER_ONE_BASED)
-                        bestdiv--;
+                bestdiv = _get_maxdiv(divider);
                 *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
         }
 
@@ -115,24 +203,22 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
                                 unsigned long parent_rate)
 {
         struct clk_divider *divider = to_clk_divider(hw);
-        unsigned int div;
+        unsigned int div, value;
         unsigned long flags = 0;
         u32 val;
 
         div = parent_rate / rate;
+        value = _get_val(divider, div);
 
-        if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
-                div--;
-
-        if (div > div_mask(divider))
-                div = div_mask(divider);
+        if (value > div_mask(divider))
+                value = div_mask(divider);
 
         if (divider->lock)
                 spin_lock_irqsave(divider->lock, flags);
 
         val = readl(divider->reg);
         val &= ~(div_mask(divider) << divider->shift);
-        val |= div << divider->shift;
+        val |= value << divider->shift;
         writel(val, divider->reg);
 
         if (divider->lock)
@@ -148,22 +234,11 @@ const struct clk_ops clk_divider_ops = {
 };
 EXPORT_SYMBOL_GPL(clk_divider_ops);
 
-/**
- * clk_register_divider - register a divider clock with the clock framework
- * @dev: device registering this clock
- * @name: name of this clock
- * @parent_name: name of clock's parent
- * @flags: framework-specific flags
- * @reg: register address to adjust divider
- * @shift: number of bits to shift the bitfield
- * @width: width of the bitfield
- * @clk_divider_flags: divider-specific flags for this clock
- * @lock: shared register lock for this clock
- */
-struct clk *clk_register_divider(struct device *dev, const char *name,
+static struct clk *_register_divider(struct device *dev, const char *name,
                 const char *parent_name, unsigned long flags,
                 void __iomem *reg, u8 shift, u8 width,
-                u8 clk_divider_flags, spinlock_t *lock)
+                u8 clk_divider_flags, const struct clk_div_table *table,
+                spinlock_t *lock)
 {
         struct clk_divider *div;
         struct clk *clk;
@@ -178,7 +253,7 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
 
         init.name = name;
         init.ops = &clk_divider_ops;
-        init.flags = flags;
+        init.flags = flags | CLK_IS_BASIC;
         init.parent_names = (parent_name ? &parent_name: NULL);
         init.num_parents = (parent_name ? 1 : 0);
 
@@ -189,6 +264,7 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
         div->flags = clk_divider_flags;
         div->lock = lock;
         div->hw.init = &init;
+        div->table = table;
 
         /* register the clock */
         clk = clk_register(dev, &div->hw);
@@ -198,3 +274,48 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
 
         return clk;
 }
+
+/**
+ * clk_register_divider - register a divider clock with the clock framework
+ * @dev: device registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @flags: framework-specific flags
+ * @reg: register address to adjust divider
+ * @shift: number of bits to shift the bitfield
+ * @width: width of the bitfield
+ * @clk_divider_flags: divider-specific flags for this clock
+ * @lock: shared register lock for this clock
+ */
+struct clk *clk_register_divider(struct device *dev, const char *name,
+                const char *parent_name, unsigned long flags,
+                void __iomem *reg, u8 shift, u8 width,
+                u8 clk_divider_flags, spinlock_t *lock)
+{
+        return _register_divider(dev, name, parent_name, flags, reg, shift,
+                        width, clk_divider_flags, NULL, lock);
+}
+
+/**
+ * clk_register_divider_table - register a table based divider clock with
+ * the clock framework
+ * @dev: device registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @flags: framework-specific flags
+ * @reg: register address to adjust divider
+ * @shift: number of bits to shift the bitfield
+ * @width: width of the bitfield
+ * @clk_divider_flags: divider-specific flags for this clock
+ * @table: array of divider/value pairs ending with a div set to 0
+ * @lock: shared register lock for this clock
+ */
+struct clk *clk_register_divider_table(struct device *dev, const char *name,
+                const char *parent_name, unsigned long flags,
+                void __iomem *reg, u8 shift, u8 width,
+                u8 clk_divider_flags, const struct clk_div_table *table,
+                spinlock_t *lock)
+{
+        return _register_divider(dev, name, parent_name, flags, reg, shift,
+                        width, clk_divider_flags, table, lock);
+}