Merge tag 'pci-v3.14-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI updates from Bjorn Helgaas:
 "PCI changes for the v3.14 merge window:

  Resource management
    - Change pci_bus_region addresses to dma_addr_t (Bjorn Helgaas)
    - Support 64-bit AGP BARs (Bjorn Helgaas, Yinghai Lu)
    - Add pci_bus_address() to get bus address of a BAR (Bjorn Helgaas)
    - Use pci_resource_start() for CPU address of AGP BARs (Bjorn Helgaas)
    - Enforce bus address limits in resource allocation (Yinghai Lu)
    - Allocate 64-bit BARs above 4G when possible (Yinghai Lu)
    - Convert pcibios_resource_to_bus() to take pci_bus, not pci_dev (Yinghai Lu)

  PCI device hotplug
    - Major rescan/remove locking update (Rafael J. Wysocki)
    - Make ioapic builtin only (not modular) (Yinghai Lu)
    - Fix release/free issues (Yinghai Lu)
    - Clean up pciehp (Bjorn Helgaas)
    - Announce pciehp slot info during enumeration (Bjorn Helgaas)

  MSI
    - Add pci_msi_vec_count(), pci_msix_vec_count() (Alexander Gordeev)
    - Add pci_enable_msi_range(), pci_enable_msix_range() (Alexander Gordeev)
    - Deprecate "tri-state" interfaces: fail/success/fail+info (Alexander Gordeev)
    - Export MSI mode using attributes, not kobjects (Greg Kroah-Hartman)
    - Drop "irq" param from *_restore_msi_irqs() (DuanZhenzhong)

  SR-IOV
    - Clear NumVFs when disabling SR-IOV in sriov_init() (ethan.zhao)

  Virtualization
    - Add support for save/restore of extended capabilities (Alex Williamson)
    - Add Virtual Channel to save/restore support (Alex Williamson)
    - Never treat a VF as a multifunction device (Alex Williamson)
    - Add pci_try_reset_function(), et al (Alex Williamson)

  AER
    - Ignore non-PCIe error sources (Betty Dall)
    - Support ACPI HEST error sources for domains other than 0 (Betty Dall)
    - Consolidate HEST error source parsers (Bjorn Helgaas)
    - Add a TLP header print helper (Borislav Petkov)

  Freescale i.MX6
    - Remove unnecessary code (Fabio Estevam)
    - Make reset-gpio optional (Marek Vasut)
    - Report "link up" only after link training completes (Marek Vasut)
    - Start link in Gen1 before negotiating for Gen2 mode (Marek Vasut)
    - Fix PCIe startup code (Richard Zhu)

  Marvell MVEBU
    - Remove duplicate of_clk_get_by_name() call (Andrew Lunn)
    - Drop writes to bridge Secondary Status register (Jason Gunthorpe)
    - Obey bridge PCI_COMMAND_MEM and PCI_COMMAND_IO bits (Jason Gunthorpe)
    - Support a bridge with no IO port window (Jason Gunthorpe)
    - Use max_t() instead of max(resource_size_t,) (Jingoo Han)
    - Remove redundant of_match_ptr (Sachin Kamat)
    - Call pci_ioremap_io() at startup instead of dynamically (Thomas Petazzoni)

  NVIDIA Tegra
    - Disable Gen2 for Tegra20 and Tegra30 (Eric Brower)

  Renesas R-Car
    - Add runtime PM support (Valentine Barshak)
    - Fix rcar_pci_probe() return value check (Wei Yongjun)

  Synopsys DesignWare
    - Fix crash in dw_msi_teardown_irq() (Bjørn Erik Nilsen)
    - Remove redundant call to pci_write_config_word() (Bjørn Erik Nilsen)
    - Fix missing MSI IRQs (Harro Haan)
    - Add dw_pcie prefix before cfg_read/write (Pratyush Anand)
    - Fix I/O transfers by using CPU (not realio) address (Pratyush Anand)
    - Whitespace cleanup (Jingoo Han)

  EISA
    - Call put_device() if device_register() fails (Levente Kurusa)
    - Revert EISA initialization breakage ((Bjorn Helgaas)

  Miscellaneous
    - Remove unused code, including PCIe 3.0 interfaces (Stephen Hemminger)
    - Prevent bus conflicts while checking for bridge apertures (Bjorn Helgaas)
    - Stop clearing bridge Secondary Status when setting up I/O aperture (Bjorn Helgaas)
    - Use dev_is_pci() to identify PCI devices (Yijing Wang)
    - Deprecate DEFINE_PCI_DEVICE_TABLE (Joe Perches)
    - Update documentation 00-INDEX (Erik Ekman)"

* tag 'pci-v3.14-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (119 commits)
  Revert "EISA: Initialize device before its resources"
  Revert "EISA: Log device resources in dmesg"
  vfio-pci: Use pci "try" reset interface
  PCI: Check parent kobject in pci_destroy_dev()
  xen/pcifront: Use global PCI rescan-remove locking
  powerpc/eeh: Use global PCI rescan-remove locking
  PCI: Fix pci_check_and_unmask_intx() comment typos
  PCI: Add pci_try_reset_function(), pci_try_reset_slot(), pci_try_reset_bus()
  MPT / PCI: Use pci_stop_and_remove_bus_device_locked()
  platform / x86: Use global PCI rescan-remove locking
  PCI: hotplug: Use global PCI rescan-remove locking
  pcmcia: Use global PCI rescan-remove locking
  ACPI / hotplug / PCI: Use global PCI rescan-remove locking
  ACPI / PCI: Use global PCI rescan-remove locking in PCI root hotplug
  PCI: Add global pci_lock_rescan_remove()
  PCI: Cleanup pci.h whitespace
  PCI: Reorder so actual code comes before stubs
  PCI/AER: Support ACPI HEST AER error sources for PCI domains other than 0
  ACPICA: Add helper macros to extract bus/segment numbers from HEST table.
  PCI: Make local functions static
  ...

13 files changed, 80 insertions, 104 deletions

diff --git a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h
index 923f99df4f1c..b709749c8639 100644
--- a/drivers/char/agp/agp.h
+++ b/drivers/char/agp/agp.h
@@ -239,6 +239,7 @@ long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
 
 /* Chipset independent registers (from AGP Spec) */
 #define AGP_APBASE      0x10
+#define AGP_APERTURE_BAR        0
 
 #define AGPSTAT         0x4
 #define AGPCMD          0x8
diff --git a/drivers/char/agp/ali-agp.c b/drivers/char/agp/ali-agp.c
index 443cd6751ca2..19db03667650 100644
--- a/drivers/char/agp/ali-agp.c
+++ b/drivers/char/agp/ali-agp.c
@@ -85,8 +85,8 @@ static int ali_configure(void)
         pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010));
 
         /* address to map to */
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                    AGP_APERTURE_BAR);
 
 #if 0
         if (agp_bridge->type == ALI_M1541) {
diff --git a/drivers/char/agp/amd-k7-agp.c b/drivers/char/agp/amd-k7-agp.c
index 779f0ab845a9..3661a51e93e2 100644
--- a/drivers/char/agp/amd-k7-agp.c
+++ b/drivers/char/agp/amd-k7-agp.c
@@ -11,7 +11,7 @@
 #include <linux/slab.h>
 #include "agp.h"
 
-#define AMD_MMBASE      0x14
+#define AMD_MMBASE_BAR  1
 #define AMD_APSIZE      0xac
 #define AMD_MODECNTL    0xb0
 #define AMD_MODECNTL2   0xb2
@@ -126,7 +126,6 @@ static int amd_create_gatt_table(struct agp_bridge_data *bridge)
         unsigned long __iomem *cur_gatt;
         unsigned long addr;
         int retval;
-        u32 temp;
         int i;
 
         value = A_SIZE_LVL2(agp_bridge->current_size);
@@ -149,8 +148,7 @@ static int amd_create_gatt_table(struct agp_bridge_data *bridge)
          * used to program the agp master not the cpu
          */
 
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR);
         agp_bridge->gart_bus_addr = addr;
 
         /* Calculate the agp offset */
@@ -207,6 +205,7 @@ static int amd_irongate_fetch_size(void)
 static int amd_irongate_configure(void)
 {
         struct aper_size_info_lvl2 *current_size;
+        phys_addr_t reg;
         u32 temp;
         u16 enable_reg;
 
@@ -214,9 +213,8 @@ static int amd_irongate_configure(void)
 
         if (!amd_irongate_private.registers) {
                 /* Get the memory mapped registers */
-                pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
-                temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
-                amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
+                reg = pci_resource_start(agp_bridge->dev, AMD_MMBASE_BAR);
+                amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096);
                 if (!amd_irongate_private.registers)
                         return -ENOMEM;
         }
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index 896413b59aae..3b47ed0310e1 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -269,7 +269,6 @@ static int agp_aperture_valid(u64 aper, u32 size)
  */
 static int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, u16 cap)
 {
-        u32 aper_low, aper_hi;
         u64 aper, nb_aper;
         int order = 0;
         u32 nb_order, nb_base;
@@ -295,9 +294,7 @@ static int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, u16 cap)
                 apsize |= 0xf00;
         order = 7 - hweight16(apsize);
 
-        pci_read_config_dword(agp, 0x10, &aper_low);
-        pci_read_config_dword(agp, 0x14, &aper_hi);
-        aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
+        aper = pci_bus_address(agp, AGP_APERTURE_BAR);
 
         /*
          * On some sick chips APSIZE is 0. This means it wants 4G
diff --git a/drivers/char/agp/ati-agp.c b/drivers/char/agp/ati-agp.c
index 03c1dc1ab552..18a7a6baa304 100644
--- a/drivers/char/agp/ati-agp.c
+++ b/drivers/char/agp/ati-agp.c
@@ -12,7 +12,7 @@
 #include <asm/agp.h>
 #include "agp.h"
 
-#define ATI_GART_MMBASE_ADDR    0x14
+#define ATI_GART_MMBASE_BAR     1
 #define ATI_RS100_APSIZE        0xac
 #define ATI_RS100_IG_AGPMODE    0xb0
 #define ATI_RS300_APSIZE        0xf8
@@ -196,12 +196,12 @@ static void ati_cleanup(void)
 
 static int ati_configure(void)
 {
+        phys_addr_t reg;
         u32 temp;
 
         /* Get the memory mapped registers */
-        pci_read_config_dword(agp_bridge->dev, ATI_GART_MMBASE_ADDR, &temp);
-        temp = (temp & 0xfffff000);
-        ati_generic_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
+        reg = pci_resource_start(agp_bridge->dev, ATI_GART_MMBASE_BAR);
+        ati_generic_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096);
 
         if (!ati_generic_private.registers)
                 return -ENOMEM;
@@ -211,18 +211,18 @@ static int ati_configure(void)
         else
                 pci_write_config_dword(agp_bridge->dev, ATI_RS300_IG_AGPMODE, 0x20000);
 
-        /* address to map too */
+        /* address to map to */
         /*
-        pci_read_config_dword(agp_bridge.dev, AGP_APBASE, &temp);
-        agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        agp_bridge.gart_bus_addr = pci_bus_address(agp_bridge.dev,
+                                                   AGP_APERTURE_BAR);
         printk(KERN_INFO PFX "IGP320 gart_bus_addr: %x\n", agp_bridge.gart_bus_addr);
         */
         writel(0x60000, ati_generic_private.registers+ATI_GART_FEATURE_ID);
         readl(ati_generic_private.registers+ATI_GART_FEATURE_ID);       /* PCI Posting.*/
 
         /* SIGNALED_SYSTEM_ERROR @ NB_STATUS */
-        pci_read_config_dword(agp_bridge->dev, 4, &temp);
-        pci_write_config_dword(agp_bridge->dev, 4, temp | (1<<14));
+        pci_read_config_dword(agp_bridge->dev, PCI_COMMAND, &temp);
+        pci_write_config_dword(agp_bridge->dev, PCI_COMMAND, temp | (1<<14));
 
         /* Write out the address of the gatt table */
         writel(agp_bridge->gatt_bus_addr, ati_generic_private.registers+ATI_GART_BASE);
@@ -385,8 +385,7 @@ static int ati_create_gatt_table(struct agp_bridge_data *bridge)
          * This is a bus address even on the alpha, b/c its
          * used to program the agp master not the cpu
          */
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR);
         agp_bridge->gart_bus_addr = addr;
 
         /* Calculate the agp offset */
diff --git a/drivers/char/agp/efficeon-agp.c b/drivers/char/agp/efficeon-agp.c
index 6974d5032053..533cb6d229b8 100644
--- a/drivers/char/agp/efficeon-agp.c
+++ b/drivers/char/agp/efficeon-agp.c
@@ -128,7 +128,6 @@ static void efficeon_cleanup(void)
 
 static int efficeon_configure(void)
 {
-        u32 temp;
         u16 temp2;
         struct aper_size_info_lvl2 *current_size;
 
@@ -141,8 +140,8 @@ static int efficeon_configure(void)
                               current_size->size_value);
 
         /* address to map to */
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                    AGP_APERTURE_BAR);
 
         /* agpctrl */
         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
diff --git a/drivers/char/agp/generic.c b/drivers/char/agp/generic.c
index a0df182f6f7d..f39437addb58 100644
--- a/drivers/char/agp/generic.c
+++ b/drivers/char/agp/generic.c
@@ -1396,8 +1396,8 @@ int agp3_generic_configure(void)
 
         current_size = A_SIZE_16(agp_bridge->current_size);
 
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                    AGP_APERTURE_BAR);
 
         /* set aperture size */
         pci_write_config_word(agp_bridge->dev, agp_bridge->capndx+AGPAPSIZE, current_size->size_value);
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index a426ee1f57a6..a7c276585a9f 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -118,7 +118,6 @@ static void intel_8xx_cleanup(void)
 
 static int intel_configure(void)
 {
-        u32 temp;
         u16 temp2;
         struct aper_size_info_16 *current_size;
 
@@ -128,8 +127,8 @@ static int intel_configure(void)
         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 
         /* address to map to */
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                    AGP_APERTURE_BAR);
 
         /* attbase - aperture base */
         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
@@ -148,7 +147,7 @@ static int intel_configure(void)
 
 static int intel_815_configure(void)
 {
-        u32 temp, addr;
+        u32 addr;
         u8 temp2;
         struct aper_size_info_8 *current_size;
 
@@ -167,8 +166,8 @@ static int intel_815_configure(void)
                         current_size->size_value);
 
         /* address to map to */
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                    AGP_APERTURE_BAR);
 
         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
         addr &= INTEL_815_ATTBASE_MASK;
@@ -208,7 +207,6 @@ static void intel_820_cleanup(void)
 
 static int intel_820_configure(void)
 {
-        u32 temp;
         u8 temp2;
         struct aper_size_info_8 *current_size;
 
@@ -218,8 +216,8 @@ static int intel_820_configure(void)
         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 
         /* address to map to */
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                    AGP_APERTURE_BAR);
 
         /* attbase - aperture base */
         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
@@ -239,7 +237,6 @@ static int intel_820_configure(void)
 
 static int intel_840_configure(void)
 {
-        u32 temp;
         u16 temp2;
         struct aper_size_info_8 *current_size;
 
@@ -249,8 +246,8 @@ static int intel_840_configure(void)
         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 
         /* address to map to */
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                    AGP_APERTURE_BAR);
 
         /* attbase - aperture base */
         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
@@ -268,7 +265,6 @@ static int intel_840_configure(void)
 
 static int intel_845_configure(void)
 {
-        u32 temp;
         u8 temp2;
         struct aper_size_info_8 *current_size;
 
@@ -282,9 +278,9 @@ static int intel_845_configure(void)
                                        agp_bridge->apbase_config);
         } else {
                 /* address to map to */
-                pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-                agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
-                agp_bridge->apbase_config = temp;
+                agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                            AGP_APERTURE_BAR);
+                agp_bridge->apbase_config = agp_bridge->gart_bus_addr;
         }
 
         /* attbase - aperture base */
@@ -303,7 +299,6 @@ static int intel_845_configure(void)
 
 static int intel_850_configure(void)
 {
-        u32 temp;
         u16 temp2;
         struct aper_size_info_8 *current_size;
 
@@ -313,8 +308,8 @@ static int intel_850_configure(void)
         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 
         /* address to map to */
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                    AGP_APERTURE_BAR);
 
         /* attbase - aperture base */
         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
@@ -332,7 +327,6 @@ static int intel_850_configure(void)
 
 static int intel_860_configure(void)
 {
-        u32 temp;
         u16 temp2;
         struct aper_size_info_8 *current_size;
 
@@ -342,8 +336,8 @@ static int intel_860_configure(void)
         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 
         /* address to map to */
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                    AGP_APERTURE_BAR);
 
         /* attbase - aperture base */
         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
@@ -361,7 +355,6 @@ static int intel_860_configure(void)
 
 static int intel_830mp_configure(void)
 {
-        u32 temp;
         u16 temp2;
         struct aper_size_info_8 *current_size;
 
@@ -371,8 +364,8 @@ static int intel_830mp_configure(void)
         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 
         /* address to map to */
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                    AGP_APERTURE_BAR);
 
         /* attbase - aperture base */
         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
@@ -390,7 +383,6 @@ static int intel_830mp_configure(void)
 
 static int intel_7505_configure(void)
 {
-        u32 temp;
         u16 temp2;
         struct aper_size_info_8 *current_size;
 
@@ -400,8 +392,8 @@ static int intel_7505_configure(void)
         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
 
         /* address to map to */
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                    AGP_APERTURE_BAR);
 
         /* attbase - aperture base */
         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 1042c1b90376..fda073dcd967 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -55,8 +55,8 @@
 #define INTEL_I860_ERRSTS       0xc8
 
 /* Intel i810 registers */
-#define I810_GMADDR             0x10
-#define I810_MMADDR             0x14
+#define I810_GMADR_BAR          0
+#define I810_MMADR_BAR          1
 #define I810_PTE_BASE           0x10000
 #define I810_PTE_MAIN_UNCACHED  0x00000000
 #define I810_PTE_LOCAL          0x00000002
@@ -113,9 +113,9 @@
 #define INTEL_I850_ERRSTS       0xc8
 
 /* intel 915G registers */
-#define I915_GMADDR     0x18
-#define I915_MMADDR     0x10
-#define I915_PTEADDR    0x1C
+#define I915_GMADR_BAR  2
+#define I915_MMADR_BAR  0
+#define I915_PTE_BAR    3
 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
 #define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index b8e2014cb9cb..ad5da1ffcbe9 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -64,7 +64,7 @@ static struct _intel_private {
         struct pci_dev *pcidev; /* device one */
         struct pci_dev *bridge_dev;
         u8 __iomem *registers;
-        phys_addr_t gtt_bus_addr;
+        phys_addr_t gtt_phys_addr;
         u32 PGETBL_save;
         u32 __iomem *gtt;               /* I915G */
         bool clear_fake_agp; /* on first access via agp, fill with scratch */
@@ -172,7 +172,7 @@ static void i8xx_destroy_pages(struct page *page)
 #define I810_GTT_ORDER 4
 static int i810_setup(void)
 {
-        u32 reg_addr;
+        phys_addr_t reg_addr;
         char *gtt_table;
 
         /* i81x does not preallocate the gtt. It's always 64kb in size. */
@@ -181,8 +181,7 @@ static int i810_setup(void)
                 return -ENOMEM;
         intel_private.i81x_gtt_table = gtt_table;
 
-        pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
-        reg_addr &= 0xfff80000;
+        reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
 
         intel_private.registers = ioremap(reg_addr, KB(64));
         if (!intel_private.registers)
@@ -191,7 +190,7 @@ static int i810_setup(void)
         writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
                intel_private.registers+I810_PGETBL_CTL);
 
-        intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
+        intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
 
         if ((readl(intel_private.registers+I810_DRAM_CTL)
                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
@@ -608,9 +607,8 @@ static bool intel_gtt_can_wc(void)
 
 static int intel_gtt_init(void)
 {
-        u32 gma_addr;
         u32 gtt_map_size;
-        int ret;
+        int ret, bar;
 
         ret = intel_private.driver->setup();
         if (ret != 0)
@@ -636,10 +634,10 @@ static int intel_gtt_init(void)
 
         intel_private.gtt = NULL;
         if (intel_gtt_can_wc())
-                intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
+                intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr,
                                                gtt_map_size);
         if (intel_private.gtt == NULL)
-                intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
+                intel_private.gtt = ioremap(intel_private.gtt_phys_addr,
                                             gtt_map_size);
         if (intel_private.gtt == NULL) {
                 intel_private.driver->cleanup();
@@ -660,14 +658,11 @@ static int intel_gtt_init(void)
         }
 
         if (INTEL_GTT_GEN <= 2)
-                pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
-                                      &gma_addr);
+                bar = I810_GMADR_BAR;
         else
-                pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
-                                      &gma_addr);
-
-        intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
+                bar = I915_GMADR_BAR;
 
+        intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar);
         return 0;
 }
 
@@ -787,16 +782,15 @@ EXPORT_SYMBOL(intel_enable_gtt);
 
 static int i830_setup(void)
 {
-        u32 reg_addr;
+        phys_addr_t reg_addr;
 
-        pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
-        reg_addr &= 0xfff80000;
+        reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
 
         intel_private.registers = ioremap(reg_addr, KB(64));
         if (!intel_private.registers)
                 return -ENOMEM;
 
-        intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
+        intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
 
         return 0;
 }
@@ -1108,12 +1102,10 @@ static void i965_write_entry(dma_addr_t addr,
 
 static int i9xx_setup(void)
 {
-        u32 reg_addr, gtt_addr;
+        phys_addr_t reg_addr;
         int size = KB(512);
 
-        pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
-
-        reg_addr &= 0xfff80000;
+        reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
 
         intel_private.registers = ioremap(reg_addr, size);
         if (!intel_private.registers)
@@ -1121,15 +1113,14 @@ static int i9xx_setup(void)
 
         switch (INTEL_GTT_GEN) {
         case 3:
-                pci_read_config_dword(intel_private.pcidev,
-                                      I915_PTEADDR, &gtt_addr);
-                intel_private.gtt_bus_addr = gtt_addr;
+                intel_private.gtt_phys_addr =
+                        pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
                 break;
         case 5:
-                intel_private.gtt_bus_addr = reg_addr + MB(2);
+                intel_private.gtt_phys_addr = reg_addr + MB(2);
                 break;
         default:
-                intel_private.gtt_bus_addr = reg_addr + KB(512);
+                intel_private.gtt_phys_addr = reg_addr + KB(512);
                 break;
         }
 
diff --git a/drivers/char/agp/nvidia-agp.c b/drivers/char/agp/nvidia-agp.c
index be42a2312dc9..a1861b75eb31 100644
--- a/drivers/char/agp/nvidia-agp.c
+++ b/drivers/char/agp/nvidia-agp.c
@@ -106,6 +106,7 @@ static int nvidia_configure(void)
 {
         int i, rc, num_dirs;
         u32 apbase, aplimit;
+        phys_addr_t apbase_phys;
         struct aper_size_info_8 *current_size;
         u32 temp;
 
@@ -115,9 +116,8 @@ static int nvidia_configure(void)
         pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
                 current_size->size_value);
 
-    /* address to map to */
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &apbase);
-        apbase &= PCI_BASE_ADDRESS_MEM_MASK;
+        /* address to map to */
+        apbase = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR);
         agp_bridge->gart_bus_addr = apbase;
         aplimit = apbase + (current_size->size * 1024 * 1024) - 1;
         pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APBASE, apbase);
@@ -153,8 +153,9 @@ static int nvidia_configure(void)
         pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp | 0x100);
 
         /* map aperture */
+        apbase_phys = pci_resource_start(agp_bridge->dev, AGP_APERTURE_BAR);
         nvidia_private.aperture =
-                (volatile u32 __iomem *) ioremap(apbase, 33 * PAGE_SIZE);
+                (volatile u32 __iomem *) ioremap(apbase_phys, 33 * PAGE_SIZE);
 
         if (!nvidia_private.aperture)
                 return -ENOMEM;
diff --git a/drivers/char/agp/sis-agp.c b/drivers/char/agp/sis-agp.c
index 79c838c434bc..2c74038da459 100644
--- a/drivers/char/agp/sis-agp.c
+++ b/drivers/char/agp/sis-agp.c
@@ -50,13 +50,12 @@ static void sis_tlbflush(struct agp_memory *mem)
 
 static int sis_configure(void)
 {
-        u32 temp;
         struct aper_size_info_8 *current_size;
 
         current_size = A_SIZE_8(agp_bridge->current_size);
         pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05);
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                    AGP_APERTURE_BAR);
         pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE,
                                agp_bridge->gatt_bus_addr);
         pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
diff --git a/drivers/char/agp/via-agp.c b/drivers/char/agp/via-agp.c
index 74d3aa3773bf..228f20cddc05 100644
--- a/drivers/char/agp/via-agp.c
+++ b/drivers/char/agp/via-agp.c
@@ -43,16 +43,15 @@ static int via_fetch_size(void)
 
 static int via_configure(void)
 {
-        u32 temp;
         struct aper_size_info_8 *current_size;
 
         current_size = A_SIZE_8(agp_bridge->current_size);
         /* aperture size */
         pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
                               current_size->size_value);
-        /* address to map too */
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        /* address to map to */
+        agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                    AGP_APERTURE_BAR);
 
         /* GART control register */
         pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
@@ -132,9 +131,9 @@ static int via_configure_agp3(void)
 
         current_size = A_SIZE_16(agp_bridge->current_size);
 
-        /* address to map too */
-        pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
-        agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+        /* address to map to */
+        agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev,
+                                                    AGP_APERTURE_BAR);
 
         /* attbase - aperture GATT base */
         pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,