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authorLinus Torvalds <torvalds@linux-foundation.org>2013-09-25 17:56:39 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-09-25 17:56:39 -0400
commitb4820416dd92bc3df33f261c60ec21b2c4481bec (patch)
tree94ac18c7604b5d10d13caad6fa8a0488960da4a9 /arch
parent06367d58f487a592de50e6e2327371c5e3b6188f (diff)
parent55c25c2f14496badefd780a9f179442756216b67 (diff)
Merge git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle: - Fix a comment - A small cleanup the main purpose of which is to work around an internal compiler error bug in certain Codesource toolchains. * git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: mm: Move some checks out of 'for' loop in DMA operations MIPS: cpu-features.h: s/MIPS53/MIPS64/
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/include/asm/cpu-features.h2
-rw-r--r--arch/mips/mm/dma-default.c12
2 files changed, 5 insertions, 9 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 51680d15ca8e..d445d060e346 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -187,7 +187,7 @@
187 187
188/* 188/*
189 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 189 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
190 * pre-MIPS32/MIPS53 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 190 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
191 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 191 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
192 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 192 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
193 */ 193 */
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index f25a7e9f8cbc..5f8b95512580 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -308,12 +308,10 @@ static void mips_dma_sync_sg_for_cpu(struct device *dev,
308{ 308{
309 int i; 309 int i;
310 310
311 /* Make sure that gcc doesn't leave the empty loop body. */ 311 if (cpu_needs_post_dma_flush(dev))
312 for (i = 0; i < nelems; i++, sg++) { 312 for (i = 0; i < nelems; i++, sg++)
313 if (cpu_needs_post_dma_flush(dev))
314 __dma_sync(sg_page(sg), sg->offset, sg->length, 313 __dma_sync(sg_page(sg), sg->offset, sg->length,
315 direction); 314 direction);
316 }
317} 315}
318 316
319static void mips_dma_sync_sg_for_device(struct device *dev, 317static void mips_dma_sync_sg_for_device(struct device *dev,
@@ -321,12 +319,10 @@ static void mips_dma_sync_sg_for_device(struct device *dev,
321{ 319{
322 int i; 320 int i;
323 321
324 /* Make sure that gcc doesn't leave the empty loop body. */ 322 if (!plat_device_is_coherent(dev))
325 for (i = 0; i < nelems; i++, sg++) { 323 for (i = 0; i < nelems; i++, sg++)
326 if (!plat_device_is_coherent(dev))
327 __dma_sync(sg_page(sg), sg->offset, sg->length, 324 __dma_sync(sg_page(sg), sg->offset, sg->length,
328 direction); 325 direction);
329 }
330} 326}
331 327
332int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) 328int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)