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authorKukjin Kim <kgene.kim@samsung.com>2014-05-25 16:20:25 -0400
committerKukjin Kim <kgene.kim@samsung.com>2014-05-25 16:20:25 -0400
commit985326c9f65a4c1a3b5ab875e6ce0c97c39449ec (patch)
treead32fb4216bea6dd39d0f05d246f354e1dc00bcc /arch
parentccf5511797cd4b48d20a85fa1778f5608eac9fd7 (diff)
parent6520e968eef4f88c076a84a80e026049d157132e (diff)
Merge branch 'v3.16-next/clk-samsung' into v3.16-next/cpuidle-exynos
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi14
-rw-r--r--arch/arm/boot/dts/s3c2416-smdk2416.dts13
-rw-r--r--arch/arm/boot/dts/s3c2416.dtsi42
-rw-r--r--arch/arm/mach-s3c24xx/Kconfig42
-rw-r--r--arch/arm/mach-s3c24xx/Makefile13
-rw-r--r--arch/arm/mach-s3c24xx/clock-dclk.c195
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2410.c284
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2412.c760
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2416.c171
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2440.c217
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2443.c212
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c244x.c141
-rw-r--r--arch/arm/mach-s3c24xx/common-s3c2443.c675
-rw-r--r--arch/arm/mach-s3c24xx/common.c85
-rw-r--r--arch/arm/mach-s3c24xx/common.h21
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq-utils.c4
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-clock.h18
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-gpio.h3
-rw-r--r--arch/arm/mach-s3c24xx/mach-amlm5900.c9
-rw-r--r--arch/arm/mach-s3c24xx/mach-anubis.c34
-rw-r--r--arch/arm/mach-s3c24xx/mach-at2440evb.c10
-rw-r--r--arch/arm/mach-s3c24xx/mach-bast.c34
-rw-r--r--arch/arm/mach-s3c24xx/mach-gta02.c8
-rw-r--r--arch/arm/mach-s3c24xx/mach-h1940.c10
-rw-r--r--arch/arm/mach-s3c24xx/mach-jive.c9
-rw-r--r--arch/arm/mach-s3c24xx/mach-mini2440.c10
-rw-r--r--arch/arm/mach-s3c24xx/mach-n30.c12
-rw-r--r--arch/arm/mach-s3c24xx/mach-nexcoder.c10
-rw-r--r--arch/arm/mach-s3c24xx/mach-osiris.c34
-rw-r--r--arch/arm/mach-s3c24xx/mach-otom.c10
-rw-r--r--arch/arm/mach-s3c24xx/mach-qt2410.c9
-rw-r--r--arch/arm/mach-s3c24xx/mach-rx1950.c21
-rw-r--r--arch/arm/mach-s3c24xx/mach-rx3715.c10
-rw-r--r--arch/arm/mach-s3c24xx/mach-s3c2416-dt.c38
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2410.c9
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2413.c9
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2416.c9
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2440.c10
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2443.c9
-rw-r--r--arch/arm/mach-s3c24xx/mach-tct_hammer.c9
-rw-r--r--arch/arm/mach-s3c24xx/mach-vr1000.c34
-rw-r--r--arch/arm/mach-s3c24xx/mach-vstms.c9
-rw-r--r--arch/arm/mach-s3c24xx/pm.c17
-rw-r--r--arch/arm/mach-s3c24xx/s3c2410.c56
-rw-r--r--arch/arm/mach-s3c24xx/s3c2412.c43
-rw-r--r--arch/arm/mach-s3c24xx/s3c2442.c111
-rw-r--r--arch/arm/mach-s3c24xx/s3c244x.c59
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu-freq-core.h1
49 files changed, 334 insertions, 3233 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 19ffaaed971e..32b94cb5f331 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -754,7 +754,7 @@ config ARCH_S3C64XX
754 select ATAGS 754 select ATAGS
755 select CLKDEV_LOOKUP 755 select CLKDEV_LOOKUP
756 select CLKSRC_SAMSUNG_PWM 756 select CLKSRC_SAMSUNG_PWM
757 select COMMON_CLK 757 select COMMON_CLK_SAMSUNG
758 select CPU_V6K 758 select CPU_V6K
759 select GENERIC_CLOCKEVENTS 759 select GENERIC_CLOCKEVENTS
760 select GPIO_SAMSUNG 760 select GPIO_SAMSUNG
@@ -835,7 +835,7 @@ config ARCH_EXYNOS
835 select ARCH_REQUIRE_GPIOLIB 835 select ARCH_REQUIRE_GPIOLIB
836 select ARCH_SPARSEMEM_ENABLE 836 select ARCH_SPARSEMEM_ENABLE
837 select ARM_GIC 837 select ARM_GIC
838 select COMMON_CLK 838 select COMMON_CLK_SAMSUNG
839 select CPU_V7 839 select CPU_V7
840 select GENERIC_CLOCKEVENTS 840 select GENERIC_CLOCKEVENTS
841 select HAVE_S3C2410_I2C if I2C 841 select HAVE_S3C2410_I2C if I2C
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 00d541a1a3d4..3c530722e8dc 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -594,7 +594,7 @@
594 #size-cells = <0>; 594 #size-cells = <0>;
595 pinctrl-names = "default"; 595 pinctrl-names = "default";
596 pinctrl-0 = <&i2c4_hs_bus>; 596 pinctrl-0 = <&i2c4_hs_bus>;
597 clocks = <&clock CLK_I2C4>; 597 clocks = <&clock CLK_USI0>;
598 clock-names = "hsi2c"; 598 clock-names = "hsi2c";
599 status = "disabled"; 599 status = "disabled";
600 }; 600 };
@@ -607,7 +607,7 @@
607 #size-cells = <0>; 607 #size-cells = <0>;
608 pinctrl-names = "default"; 608 pinctrl-names = "default";
609 pinctrl-0 = <&i2c5_hs_bus>; 609 pinctrl-0 = <&i2c5_hs_bus>;
610 clocks = <&clock CLK_I2C5>; 610 clocks = <&clock CLK_USI1>;
611 clock-names = "hsi2c"; 611 clock-names = "hsi2c";
612 status = "disabled"; 612 status = "disabled";
613 }; 613 };
@@ -620,7 +620,7 @@
620 #size-cells = <0>; 620 #size-cells = <0>;
621 pinctrl-names = "default"; 621 pinctrl-names = "default";
622 pinctrl-0 = <&i2c6_hs_bus>; 622 pinctrl-0 = <&i2c6_hs_bus>;
623 clocks = <&clock CLK_I2C6>; 623 clocks = <&clock CLK_USI2>;
624 clock-names = "hsi2c"; 624 clock-names = "hsi2c";
625 status = "disabled"; 625 status = "disabled";
626 }; 626 };
@@ -633,7 +633,7 @@
633 #size-cells = <0>; 633 #size-cells = <0>;
634 pinctrl-names = "default"; 634 pinctrl-names = "default";
635 pinctrl-0 = <&i2c7_hs_bus>; 635 pinctrl-0 = <&i2c7_hs_bus>;
636 clocks = <&clock CLK_I2C7>; 636 clocks = <&clock CLK_USI3>;
637 clock-names = "hsi2c"; 637 clock-names = "hsi2c";
638 status = "disabled"; 638 status = "disabled";
639 }; 639 };
@@ -646,7 +646,7 @@
646 #size-cells = <0>; 646 #size-cells = <0>;
647 pinctrl-names = "default"; 647 pinctrl-names = "default";
648 pinctrl-0 = <&i2c8_hs_bus>; 648 pinctrl-0 = <&i2c8_hs_bus>;
649 clocks = <&clock CLK_I2C8>; 649 clocks = <&clock CLK_USI4>;
650 clock-names = "hsi2c"; 650 clock-names = "hsi2c";
651 status = "disabled"; 651 status = "disabled";
652 }; 652 };
@@ -659,7 +659,7 @@
659 #size-cells = <0>; 659 #size-cells = <0>;
660 pinctrl-names = "default"; 660 pinctrl-names = "default";
661 pinctrl-0 = <&i2c9_hs_bus>; 661 pinctrl-0 = <&i2c9_hs_bus>;
662 clocks = <&clock CLK_I2C9>; 662 clocks = <&clock CLK_USI5>;
663 clock-names = "hsi2c"; 663 clock-names = "hsi2c";
664 status = "disabled"; 664 status = "disabled";
665 }; 665 };
@@ -672,7 +672,7 @@
672 #size-cells = <0>; 672 #size-cells = <0>;
673 pinctrl-names = "default"; 673 pinctrl-names = "default";
674 pinctrl-0 = <&i2c10_hs_bus>; 674 pinctrl-0 = <&i2c10_hs_bus>;
675 clocks = <&clock CLK_I2C10>; 675 clocks = <&clock CLK_USI6>;
676 clock-names = "hsi2c"; 676 clock-names = "hsi2c";
677 status = "disabled"; 677 status = "disabled";
678 }; 678 };
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
index 59594cf15998..ea92fd69529a 100644
--- a/arch/arm/boot/dts/s3c2416-smdk2416.dts
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -19,6 +19,19 @@
19 reg = <0x30000000 0x4000000>; 19 reg = <0x30000000 0x4000000>;
20 }; 20 };
21 21
22 clocks {
23 compatible = "simple-bus";
24 #address-cells = <1>;
25 #size-cells = <1>;
26
27 xti: xti {
28 compatible = "fixed-clock";
29 clock-frequency = <12000000>;
30 clock-output-names = "xti";
31 #clock-cells = <0>;
32 };
33 };
34
22 serial@50000000 { 35 serial@50000000 {
23 status = "okay"; 36 status = "okay";
24 pinctrl-names = "default"; 37 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
index e6555bdd81b8..955e4a4f8c31 100644
--- a/arch/arm/boot/dts/s3c2416.dtsi
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -8,6 +8,7 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#include <dt-bindings/clock/s3c2443.h>
11#include "s3c24xx.dtsi" 12#include "s3c24xx.dtsi"
12#include "s3c2416-pinctrl.dtsi" 13#include "s3c2416-pinctrl.dtsi"
13 14
@@ -28,26 +29,53 @@
28 compatible = "samsung,s3c2416-irq"; 29 compatible = "samsung,s3c2416-irq";
29 }; 30 };
30 31
32 clocks: clock-controller@0x4c000000 {
33 compatible = "samsung,s3c2416-clock";
34 reg = <0x4c000000 0x40>;
35 #clock-cells = <1>;
36 };
37
31 pinctrl@56000000 { 38 pinctrl@56000000 {
32 compatible = "samsung,s3c2416-pinctrl"; 39 compatible = "samsung,s3c2416-pinctrl";
33 }; 40 };
34 41
42 timer@51000000 {
43 clocks = <&clocks PCLK_PWM>;
44 clock-names = "timers";
45 };
46
35 serial@50000000 { 47 serial@50000000 {
36 compatible = "samsung,s3c2440-uart"; 48 compatible = "samsung,s3c2440-uart";
49 clock-names = "uart", "clk_uart_baud2",
50 "clk_uart_baud3";
51 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
52 <&clocks SCLK_UART>;
37 }; 53 };
38 54
39 serial@50004000 { 55 serial@50004000 {
40 compatible = "samsung,s3c2440-uart"; 56 compatible = "samsung,s3c2440-uart";
57 clock-names = "uart", "clk_uart_baud2",
58 "clk_uart_baud3";
59 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
60 <&clocks SCLK_UART>;
41 }; 61 };
42 62
43 serial@50008000 { 63 serial@50008000 {
44 compatible = "samsung,s3c2440-uart"; 64 compatible = "samsung,s3c2440-uart";
65 clock-names = "uart", "clk_uart_baud2",
66 "clk_uart_baud3";
67 clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
68 <&clocks SCLK_UART>;
45 }; 69 };
46 70
47 serial@5000C000 { 71 serial@5000C000 {
48 compatible = "samsung,s3c2440-uart"; 72 compatible = "samsung,s3c2440-uart";
49 reg = <0x5000C000 0x4000>; 73 reg = <0x5000C000 0x4000>;
50 interrupts = <1 18 24 4>, <1 18 25 4>; 74 interrupts = <1 18 24 4>, <1 18 25 4>;
75 clock-names = "uart", "clk_uart_baud2",
76 "clk_uart_baud3";
77 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
78 <&clocks SCLK_UART>;
51 status = "disabled"; 79 status = "disabled";
52 }; 80 };
53 81
@@ -55,6 +83,10 @@
55 compatible = "samsung,s3c6410-sdhci"; 83 compatible = "samsung,s3c6410-sdhci";
56 reg = <0x4AC00000 0x100>; 84 reg = <0x4AC00000 0x100>;
57 interrupts = <0 0 21 3>; 85 interrupts = <0 0 21 3>;
86 clock-names = "hsmmc", "mmc_busclk.0",
87 "mmc_busclk.2";
88 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
89 <&clocks MUX_HSMMC0>;
58 status = "disabled"; 90 status = "disabled";
59 }; 91 };
60 92
@@ -62,18 +94,28 @@
62 compatible = "samsung,s3c6410-sdhci"; 94 compatible = "samsung,s3c6410-sdhci";
63 reg = <0x4A800000 0x100>; 95 reg = <0x4A800000 0x100>;
64 interrupts = <0 0 20 3>; 96 interrupts = <0 0 20 3>;
97 clock-names = "hsmmc", "mmc_busclk.0",
98 "mmc_busclk.2";
99 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
100 <&clocks MUX_HSMMC1>;
65 status = "disabled"; 101 status = "disabled";
66 }; 102 };
67 103
68 watchdog@53000000 { 104 watchdog@53000000 {
69 interrupts = <1 9 27 3>; 105 interrupts = <1 9 27 3>;
106 clocks = <&clocks PCLK_WDT>;
107 clock-names = "watchdog";
70 }; 108 };
71 109
72 rtc@57000000 { 110 rtc@57000000 {
73 compatible = "samsung,s3c2416-rtc"; 111 compatible = "samsung,s3c2416-rtc";
112 clocks = <&clocks PCLK_RTC>;
113 clock-names = "rtc";
74 }; 114 };
75 115
76 i2c@54000000 { 116 i2c@54000000 {
77 compatible = "samsung,s3c2440-i2c"; 117 compatible = "samsung,s3c2440-i2c";
118 clocks = <&clocks PCLK_I2C0>;
119 clock-names = "i2c";
78 }; 120 };
79}; 121};
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 40cf50b9940c..1e52b6926374 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -18,6 +18,8 @@ config PLAT_S3C24XX
18 help 18 help
19 Base platform code for any Samsung S3C24XX device 19 Base platform code for any Samsung S3C24XX device
20 20
21
22
21menu "SAMSUNG S3C24XX SoCs Support" 23menu "SAMSUNG S3C24XX SoCs Support"
22 24
23comment "S3C24XX SoCs" 25comment "S3C24XX SoCs"
@@ -27,7 +29,7 @@ config CPU_S3C2410
27 default y 29 default y
28 select CPU_ARM920T 30 select CPU_ARM920T
29 select CPU_LLSERIAL_S3C2410 31 select CPU_LLSERIAL_S3C2410
30 select S3C2410_CLOCK 32 select S3C2410_COMMON_CLK
31 select S3C2410_DMA if S3C24XX_DMA 33 select S3C2410_DMA if S3C24XX_DMA
32 select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ 34 select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
33 select S3C2410_PM if PM 35 select S3C2410_PM if PM
@@ -40,6 +42,7 @@ config CPU_S3C2412
40 bool "SAMSUNG S3C2412" 42 bool "SAMSUNG S3C2412"
41 select CPU_ARM926T 43 select CPU_ARM926T
42 select CPU_LLSERIAL_S3C2440 44 select CPU_LLSERIAL_S3C2440
45 select S3C2412_COMMON_CLK
43 select S3C2412_DMA if S3C24XX_DMA 46 select S3C2412_DMA if S3C24XX_DMA
44 select S3C2412_PM if PM 47 select S3C2412_PM if PM
45 help 48 help
@@ -50,9 +53,8 @@ config CPU_S3C2416
50 select CPU_ARM926T 53 select CPU_ARM926T
51 select CPU_LLSERIAL_S3C2440 54 select CPU_LLSERIAL_S3C2440
52 select S3C2416_PM if PM 55 select S3C2416_PM if PM
53 select S3C2443_COMMON 56 select S3C2443_COMMON_CLK
54 select S3C2443_DMA if S3C24XX_DMA 57 select S3C2443_DMA if S3C24XX_DMA
55 select SAMSUNG_CLKSRC
56 help 58 help
57 Support for the S3C2416 SoC from the S3C24XX line 59 Support for the S3C2416 SoC from the S3C24XX line
58 60
@@ -60,7 +62,7 @@ config CPU_S3C2440
60 bool "SAMSUNG S3C2440" 62 bool "SAMSUNG S3C2440"
61 select CPU_ARM920T 63 select CPU_ARM920T
62 select CPU_LLSERIAL_S3C2440 64 select CPU_LLSERIAL_S3C2440
63 select S3C2410_CLOCK 65 select S3C2410_COMMON_CLK
64 select S3C2410_PM if PM 66 select S3C2410_PM if PM
65 select S3C2440_DMA if S3C24XX_DMA 67 select S3C2440_DMA if S3C24XX_DMA
66 help 68 help
@@ -70,7 +72,7 @@ config CPU_S3C2442
70 bool "SAMSUNG S3C2442" 72 bool "SAMSUNG S3C2442"
71 select CPU_ARM920T 73 select CPU_ARM920T
72 select CPU_LLSERIAL_S3C2440 74 select CPU_LLSERIAL_S3C2440
73 select S3C2410_CLOCK 75 select S3C2410_COMMON_CLK
74 select S3C2410_DMA if S3C24XX_DMA 76 select S3C2410_DMA if S3C24XX_DMA
75 select S3C2410_PM if PM 77 select S3C2410_PM if PM
76 help 78 help
@@ -85,25 +87,13 @@ config CPU_S3C2443
85 bool "SAMSUNG S3C2443" 87 bool "SAMSUNG S3C2443"
86 select CPU_ARM920T 88 select CPU_ARM920T
87 select CPU_LLSERIAL_S3C2440 89 select CPU_LLSERIAL_S3C2440
88 select S3C2443_COMMON 90 select S3C2443_COMMON_CLK
89 select S3C2443_DMA if S3C24XX_DMA 91 select S3C2443_DMA if S3C24XX_DMA
90 select SAMSUNG_CLKSRC
91 help 92 help
92 Support for the S3C2443 SoC from the S3C24XX line 93 Support for the S3C2443 SoC from the S3C24XX line
93 94
94# common code 95# common code
95 96
96config S3C2410_CLOCK
97 bool
98 help
99 Clock code for the S3C2410, and similar processors which
100 is currently includes the S3C2410, S3C2440, S3C2442.
101
102config S3C24XX_DCLK
103 bool
104 help
105 Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
106
107config S3C24XX_SMDK 97config S3C24XX_SMDK
108 bool 98 bool
109 help 99 help
@@ -258,8 +248,8 @@ config ARCH_BAST
258 bool "Simtec Electronics BAST (EB2410ITX)" 248 bool "Simtec Electronics BAST (EB2410ITX)"
259 select ISA 249 select ISA
260 select MACH_BAST_IDE 250 select MACH_BAST_IDE
251 select S3C2410_COMMON_DCLK
261 select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ 252 select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ
262 select S3C24XX_DCLK
263 select S3C24XX_SIMTEC_NOR 253 select S3C24XX_SIMTEC_NOR
264 select S3C24XX_SIMTEC_PM if PM 254 select S3C24XX_SIMTEC_PM if PM
265 select S3C24XX_SIMTEC_USB 255 select S3C24XX_SIMTEC_USB
@@ -340,7 +330,7 @@ config MACH_TCT_HAMMER
340config MACH_VR1000 330config MACH_VR1000
341 bool "Thorcom VR1000" 331 bool "Thorcom VR1000"
342 select MACH_BAST_IDE 332 select MACH_BAST_IDE
343 select S3C24XX_DCLK 333 select S3C2410_COMMON_DCLK
344 select S3C24XX_SIMTEC_NOR 334 select S3C24XX_SIMTEC_NOR
345 select S3C24XX_SIMTEC_PM if PM 335 select S3C24XX_SIMTEC_PM if PM
346 select S3C24XX_SIMTEC_USB 336 select S3C24XX_SIMTEC_USB
@@ -519,8 +509,8 @@ comment "S3C2440 Boards"
519config MACH_ANUBIS 509config MACH_ANUBIS
520 bool "Simtec Electronics ANUBIS" 510 bool "Simtec Electronics ANUBIS"
521 select HAVE_PATA_PLATFORM 511 select HAVE_PATA_PLATFORM
512 select S3C2410_COMMON_DCLK
522 select S3C2440_XTAL_12000000 513 select S3C2440_XTAL_12000000
523 select S3C24XX_DCLK
524 select S3C24XX_SIMTEC_PM if PM 514 select S3C24XX_SIMTEC_PM if PM
525 select S3C_DEV_USB_HOST 515 select S3C_DEV_USB_HOST
526 help 516 help
@@ -558,9 +548,9 @@ config MACH_NEXCODER_2440
558 548
559config MACH_OSIRIS 549config MACH_OSIRIS
560 bool "Simtec IM2440D20 (OSIRIS) module" 550 bool "Simtec IM2440D20 (OSIRIS) module"
551 select S3C2410_COMMON_DCLK
561 select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ 552 select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
562 select S3C2440_XTAL_12000000 553 select S3C2440_XTAL_12000000
563 select S3C24XX_DCLK
564 select S3C24XX_SIMTEC_PM if PM 554 select S3C24XX_SIMTEC_PM if PM
565 select S3C_DEV_NAND 555 select S3C_DEV_NAND
566 select S3C_DEV_USB_HOST 556 select S3C_DEV_USB_HOST
@@ -629,9 +619,9 @@ config MACH_RX1950
629 bool "HP iPAQ rx1950" 619 bool "HP iPAQ rx1950"
630 select I2C 620 select I2C
631 select PM_H1940 if PM 621 select PM_H1940 if PM
622 select S3C2410_COMMON_DCLK
632 select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ 623 select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
633 select S3C2440_XTAL_16934400 624 select S3C2440_XTAL_16934400
634 select S3C24XX_DCLK
635 select S3C24XX_PWM 625 select S3C24XX_PWM
636 select S3C_DEV_NAND 626 select S3C_DEV_NAND
637 help 627 help
@@ -641,12 +631,6 @@ endif # CPU_S3C2442
641 631
642if CPU_S3C2443 || CPU_S3C2416 632if CPU_S3C2443 || CPU_S3C2416
643 633
644config S3C2443_COMMON
645 bool
646 help
647 Common code for the S3C2443 and similar processors, which includes
648 the S3C2416 and S3C2450.
649
650config S3C2443_DMA 634config S3C2443_DMA
651 bool 635 bool
652 help 636 help
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 7f54e5b954ca..2235d0d3b38d 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -21,22 +21,22 @@ obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o
21obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o 21obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o
22obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o 22obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o
23 23
24obj-$(CONFIG_CPU_S3C2412) += s3c2412.o clock-s3c2412.o 24obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
25obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o 25obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o
26obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o 26obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o
27obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o 27obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o
28 28
29obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock-s3c2416.o 29obj-$(CONFIG_CPU_S3C2416) += s3c2416.o
30obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o 30obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o
31 31
32obj-$(CONFIG_CPU_S3C2440) += s3c2440.o clock-s3c2440.o 32obj-$(CONFIG_CPU_S3C2440) += s3c2440.o
33obj-$(CONFIG_CPU_S3C2442) += s3c2442.o 33obj-$(CONFIG_CPU_S3C2442) += s3c2442.o
34obj-$(CONFIG_CPU_S3C244X) += s3c244x.o clock-s3c244x.o 34obj-$(CONFIG_CPU_S3C244X) += s3c244x.o
35obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o 35obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o
36obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o 36obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
37obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o 37obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
38 38
39obj-$(CONFIG_CPU_S3C2443) += s3c2443.o clock-s3c2443.o 39obj-$(CONFIG_CPU_S3C2443) += s3c2443.o
40 40
41# PM 41# PM
42 42
@@ -44,16 +44,13 @@ obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o
44 44
45# common code 45# common code
46 46
47obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
48obj-$(CONFIG_S3C24XX_DMA) += dma.o 47obj-$(CONFIG_S3C24XX_DMA) += dma.o
49 48
50obj-$(CONFIG_S3C2410_CLOCK) += clock-s3c2410.o
51obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o 49obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
52 50
53obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o 51obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o
54obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o 52obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o
55 53
56obj-$(CONFIG_S3C2443_COMMON) += common-s3c2443.o
57obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o 54obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o
58 55
59# 56#
diff --git a/arch/arm/mach-s3c24xx/clock-dclk.c b/arch/arm/mach-s3c24xx/clock-dclk.c
deleted file mode 100644
index 1edd9b2369c5..000000000000
--- a/arch/arm/mach-s3c24xx/clock-dclk.c
+++ /dev/null
@@ -1,195 +0,0 @@
1/*
2 * Copyright (c) 2004-2008 Simtec Electronics
3 * Ben Dooks <ben@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C24XX - definitions for DCLK and CLKOUT registers
11 */
12
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17
18#include <mach/regs-clock.h>
19#include <mach/regs-gpio.h>
20
21#include <plat/clock.h>
22#include <plat/cpu.h>
23
24/* clocks that could be registered by external code */
25
26static int s3c24xx_dclk_enable(struct clk *clk, int enable)
27{
28 unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
29
30 if (enable)
31 dclkcon |= clk->ctrlbit;
32 else
33 dclkcon &= ~clk->ctrlbit;
34
35 __raw_writel(dclkcon, S3C24XX_DCLKCON);
36
37 return 0;
38}
39
40static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
41{
42 unsigned long dclkcon;
43 unsigned int uclk;
44
45 if (parent == &clk_upll)
46 uclk = 1;
47 else if (parent == &clk_p)
48 uclk = 0;
49 else
50 return -EINVAL;
51
52 clk->parent = parent;
53
54 dclkcon = __raw_readl(S3C24XX_DCLKCON);
55
56 if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
57 if (uclk)
58 dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
59 else
60 dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
61 } else {
62 if (uclk)
63 dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
64 else
65 dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
66 }
67
68 __raw_writel(dclkcon, S3C24XX_DCLKCON);
69
70 return 0;
71}
72static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
73{
74 unsigned long div;
75
76 if ((rate == 0) || !clk->parent)
77 return 0;
78
79 div = clk_get_rate(clk->parent) / rate;
80 if (div < 2)
81 div = 2;
82 else if (div > 16)
83 div = 16;
84
85 return div;
86}
87
88static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
89 unsigned long rate)
90{
91 unsigned long div = s3c24xx_calc_div(clk, rate);
92
93 if (div == 0)
94 return 0;
95
96 return clk_get_rate(clk->parent) / div;
97}
98
99static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
100{
101 unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
102
103 if (div == 0)
104 return -EINVAL;
105
106 if (clk == &s3c24xx_dclk0) {
107 mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
108 S3C2410_DCLKCON_DCLK0_CMP_MASK;
109 data = S3C2410_DCLKCON_DCLK0_DIV(div) |
110 S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
111 } else if (clk == &s3c24xx_dclk1) {
112 mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
113 S3C2410_DCLKCON_DCLK1_CMP_MASK;
114 data = S3C2410_DCLKCON_DCLK1_DIV(div) |
115 S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
116 } else
117 return -EINVAL;
118
119 clk->rate = clk_get_rate(clk->parent) / div;
120 __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
121 S3C24XX_DCLKCON);
122 return clk->rate;
123}
124static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
125{
126 unsigned long mask;
127 unsigned long source;
128
129 /* calculate the MISCCR setting for the clock */
130
131 if (parent == &clk_mpll)
132 source = S3C2410_MISCCR_CLK0_MPLL;
133 else if (parent == &clk_upll)
134 source = S3C2410_MISCCR_CLK0_UPLL;
135 else if (parent == &clk_f)
136 source = S3C2410_MISCCR_CLK0_FCLK;
137 else if (parent == &clk_h)
138 source = S3C2410_MISCCR_CLK0_HCLK;
139 else if (parent == &clk_p)
140 source = S3C2410_MISCCR_CLK0_PCLK;
141 else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
142 source = S3C2410_MISCCR_CLK0_DCLK0;
143 else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
144 source = S3C2410_MISCCR_CLK0_DCLK0;
145 else
146 return -EINVAL;
147
148 clk->parent = parent;
149
150 if (clk == &s3c24xx_clkout0)
151 mask = S3C2410_MISCCR_CLK0_MASK;
152 else {
153 source <<= 4;
154 mask = S3C2410_MISCCR_CLK1_MASK;
155 }
156
157 s3c2410_modify_misccr(mask, source);
158 return 0;
159}
160
161/* external clock definitions */
162
163static struct clk_ops dclk_ops = {
164 .set_parent = s3c24xx_dclk_setparent,
165 .set_rate = s3c24xx_set_dclk_rate,
166 .round_rate = s3c24xx_round_dclk_rate,
167};
168
169struct clk s3c24xx_dclk0 = {
170 .name = "dclk0",
171 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
172 .enable = s3c24xx_dclk_enable,
173 .ops = &dclk_ops,
174};
175
176struct clk s3c24xx_dclk1 = {
177 .name = "dclk1",
178 .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
179 .enable = s3c24xx_dclk_enable,
180 .ops = &dclk_ops,
181};
182
183static struct clk_ops clkout_ops = {
184 .set_parent = s3c24xx_clkout_setparent,
185};
186
187struct clk s3c24xx_clkout0 = {
188 .name = "clkout0",
189 .ops = &clkout_ops,
190};
191
192struct clk s3c24xx_clkout1 = {
193 .name = "clkout1",
194 .ops = &clkout_ops,
195};
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
deleted file mode 100644
index d1afcf9252d1..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2410.c
+++ /dev/null
@@ -1,284 +0,0 @@
1/*
2 * Copyright (c) 2006 Simtec Electronics
3 * Ben Dooks <ben@simtec.co.uk>
4 *
5 * S3C2410,S3C2440,S3C2442 Clock control support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/list.h>
26#include <linux/errno.h>
27#include <linux/err.h>
28#include <linux/device.h>
29#include <linux/clk.h>
30#include <linux/mutex.h>
31#include <linux/delay.h>
32#include <linux/serial_core.h>
33#include <linux/serial_s3c.h>
34#include <linux/io.h>
35
36#include <asm/mach/map.h>
37
38#include <mach/hardware.h>
39#include <mach/regs-clock.h>
40#include <mach/regs-gpio.h>
41
42#include <plat/clock.h>
43#include <plat/cpu.h>
44
45int s3c2410_clkcon_enable(struct clk *clk, int enable)
46{
47 unsigned int clocks = clk->ctrlbit;
48 unsigned long clkcon;
49
50 clkcon = __raw_readl(S3C2410_CLKCON);
51
52 if (enable)
53 clkcon |= clocks;
54 else
55 clkcon &= ~clocks;
56
57 /* ensure none of the special function bits set */
58 clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
59
60 __raw_writel(clkcon, S3C2410_CLKCON);
61
62 return 0;
63}
64
65static int s3c2410_upll_enable(struct clk *clk, int enable)
66{
67 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
68 unsigned long orig = clkslow;
69
70 if (enable)
71 clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
72 else
73 clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
74
75 __raw_writel(clkslow, S3C2410_CLKSLOW);
76
77 /* if we started the UPLL, then allow to settle */
78
79 if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
80 udelay(200);
81
82 return 0;
83}
84
85/* standard clock definitions */
86
87static struct clk init_clocks_off[] = {
88 {
89 .name = "nand",
90 .parent = &clk_h,
91 .enable = s3c2410_clkcon_enable,
92 .ctrlbit = S3C2410_CLKCON_NAND,
93 }, {
94 .name = "sdi",
95 .parent = &clk_p,
96 .enable = s3c2410_clkcon_enable,
97 .ctrlbit = S3C2410_CLKCON_SDI,
98 }, {
99 .name = "adc",
100 .parent = &clk_p,
101 .enable = s3c2410_clkcon_enable,
102 .ctrlbit = S3C2410_CLKCON_ADC,
103 }, {
104 .name = "i2c",
105 .parent = &clk_p,
106 .enable = s3c2410_clkcon_enable,
107 .ctrlbit = S3C2410_CLKCON_IIC,
108 }, {
109 .name = "iis",
110 .parent = &clk_p,
111 .enable = s3c2410_clkcon_enable,
112 .ctrlbit = S3C2410_CLKCON_IIS,
113 }, {
114 .name = "spi",
115 .parent = &clk_p,
116 .enable = s3c2410_clkcon_enable,
117 .ctrlbit = S3C2410_CLKCON_SPI,
118 }
119};
120
121static struct clk clk_lcd = {
122 .name = "lcd",
123 .parent = &clk_h,
124 .enable = s3c2410_clkcon_enable,
125 .ctrlbit = S3C2410_CLKCON_LCDC,
126};
127
128static struct clk clk_gpio = {
129 .name = "gpio",
130 .parent = &clk_p,
131 .enable = s3c2410_clkcon_enable,
132 .ctrlbit = S3C2410_CLKCON_GPIO,
133};
134
135static struct clk clk_usb_host = {
136 .name = "usb-host",
137 .parent = &clk_h,
138 .enable = s3c2410_clkcon_enable,
139 .ctrlbit = S3C2410_CLKCON_USBH,
140};
141
142static struct clk clk_usb_device = {
143 .name = "usb-device",
144 .parent = &clk_h,
145 .enable = s3c2410_clkcon_enable,
146 .ctrlbit = S3C2410_CLKCON_USBD,
147};
148
149static struct clk clk_timers = {
150 .name = "timers",
151 .parent = &clk_p,
152 .enable = s3c2410_clkcon_enable,
153 .ctrlbit = S3C2410_CLKCON_PWMT,
154};
155
156struct clk s3c24xx_clk_uart0 = {
157 .name = "uart",
158 .devname = "s3c2410-uart.0",
159 .parent = &clk_p,
160 .enable = s3c2410_clkcon_enable,
161 .ctrlbit = S3C2410_CLKCON_UART0,
162};
163
164struct clk s3c24xx_clk_uart1 = {
165 .name = "uart",
166 .devname = "s3c2410-uart.1",
167 .parent = &clk_p,
168 .enable = s3c2410_clkcon_enable,
169 .ctrlbit = S3C2410_CLKCON_UART1,
170};
171
172struct clk s3c24xx_clk_uart2 = {
173 .name = "uart",
174 .devname = "s3c2410-uart.2",
175 .parent = &clk_p,
176 .enable = s3c2410_clkcon_enable,
177 .ctrlbit = S3C2410_CLKCON_UART2,
178};
179
180static struct clk clk_rtc = {
181 .name = "rtc",
182 .parent = &clk_p,
183 .enable = s3c2410_clkcon_enable,
184 .ctrlbit = S3C2410_CLKCON_RTC,
185};
186
187static struct clk clk_watchdog = {
188 .name = "watchdog",
189 .parent = &clk_p,
190 .ctrlbit = 0,
191};
192
193static struct clk clk_usb_bus_host = {
194 .name = "usb-bus-host",
195 .parent = &clk_usb_bus,
196};
197
198static struct clk clk_usb_bus_gadget = {
199 .name = "usb-bus-gadget",
200 .parent = &clk_usb_bus,
201};
202
203static struct clk *init_clocks[] = {
204 &clk_lcd,
205 &clk_gpio,
206 &clk_usb_host,
207 &clk_usb_device,
208 &clk_timers,
209 &s3c24xx_clk_uart0,
210 &s3c24xx_clk_uart1,
211 &s3c24xx_clk_uart2,
212 &clk_rtc,
213 &clk_watchdog,
214 &clk_usb_bus_host,
215 &clk_usb_bus_gadget,
216};
217
218/* s3c2410_baseclk_add()
219 *
220 * Add all the clocks used by the s3c2410 or compatible CPUs
221 * such as the S3C2440 and S3C2442.
222 *
223 * We cannot use a system device as we are needed before any
224 * of the init-calls that initialise the devices are actually
225 * done.
226*/
227
228int __init s3c2410_baseclk_add(void)
229{
230 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
231 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
232 struct clk *xtal;
233 int ret;
234 int ptr;
235
236 clk_upll.enable = s3c2410_upll_enable;
237
238 if (s3c24xx_register_clock(&clk_usb_bus) < 0)
239 printk(KERN_ERR "failed to register usb bus clock\n");
240
241 /* register clocks from clock array */
242
243 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++) {
244 struct clk *clkp = init_clocks[ptr];
245
246 /* ensure that we note the clock state */
247
248 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
249
250 ret = s3c24xx_register_clock(clkp);
251 if (ret < 0) {
252 printk(KERN_ERR "Failed to register clock %s (%d)\n",
253 clkp->name, ret);
254 }
255 }
256
257 /* We must be careful disabling the clocks we are not intending to
258 * be using at boot time, as subsystems such as the LCD which do
259 * their own DMA requests to the bus can cause the system to lockup
260 * if they where in the middle of requesting bus access.
261 *
262 * Disabling the LCD clock if the LCD is active is very dangerous,
263 * and therefore the bootloader should be careful to not enable
264 * the LCD clock if it is not needed.
265 */
266
267 /* install (and disable) the clocks we do not need immediately */
268
269 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
270 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
271
272 /* show the clock-slow value */
273
274 xtal = clk_get(NULL, "xtal");
275
276 printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
277 print_mhz(clk_get_rate(xtal) /
278 ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
279 (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
280 (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
281 (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
282
283 return 0;
284}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c
deleted file mode 100644
index 192a5b2550b0..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2412.c
+++ /dev/null
@@ -1,760 +0,0 @@
1/* linux/arch/arm/mach-s3c2412/clock.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412,S3C2413 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/list.h>
27#include <linux/errno.h>
28#include <linux/err.h>
29#include <linux/device.h>
30#include <linux/clk.h>
31#include <linux/mutex.h>
32#include <linux/delay.h>
33#include <linux/serial_core.h>
34#include <linux/serial_s3c.h>
35#include <linux/io.h>
36
37#include <asm/mach/map.h>
38
39#include <mach/hardware.h>
40#include <mach/regs-clock.h>
41#include <mach/regs-gpio.h>
42
43#include <plat/clock.h>
44#include <plat/cpu.h>
45
46/* We currently have to assume that the system is running
47 * from the XTPll input, and that all ***REFCLKs are being
48 * fed from it, as we cannot read the state of OM[4] from
49 * software.
50 *
51 * It would be possible for each board initialisation to
52 * set the correct muxing at initialisation
53*/
54
55static int s3c2412_clkcon_enable(struct clk *clk, int enable)
56{
57 unsigned int clocks = clk->ctrlbit;
58 unsigned long clkcon;
59
60 clkcon = __raw_readl(S3C2410_CLKCON);
61
62 if (enable)
63 clkcon |= clocks;
64 else
65 clkcon &= ~clocks;
66
67 __raw_writel(clkcon, S3C2410_CLKCON);
68
69 return 0;
70}
71
72static int s3c2412_upll_enable(struct clk *clk, int enable)
73{
74 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
75 unsigned long orig = upllcon;
76
77 if (!enable)
78 upllcon |= S3C2412_PLLCON_OFF;
79 else
80 upllcon &= ~S3C2412_PLLCON_OFF;
81
82 __raw_writel(upllcon, S3C2410_UPLLCON);
83
84 /* allow ~150uS for the PLL to settle and lock */
85
86 if (enable && (orig & S3C2412_PLLCON_OFF))
87 udelay(150);
88
89 return 0;
90}
91
92/* clock selections */
93
94static struct clk clk_erefclk = {
95 .name = "erefclk",
96};
97
98static struct clk clk_urefclk = {
99 .name = "urefclk",
100};
101
102static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
103{
104 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
105
106 if (parent == &clk_urefclk)
107 clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
108 else if (parent == &clk_upll)
109 clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
110 else
111 return -EINVAL;
112
113 clk->parent = parent;
114
115 __raw_writel(clksrc, S3C2412_CLKSRC);
116 return 0;
117}
118
119static struct clk clk_usysclk = {
120 .name = "usysclk",
121 .parent = &clk_xtal,
122 .ops = &(struct clk_ops) {
123 .set_parent = s3c2412_setparent_usysclk,
124 },
125};
126
127static struct clk clk_mrefclk = {
128 .name = "mrefclk",
129 .parent = &clk_xtal,
130};
131
132static struct clk clk_mdivclk = {
133 .name = "mdivclk",
134 .parent = &clk_xtal,
135};
136
137static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
138{
139 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
140
141 if (parent == &clk_usysclk)
142 clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
143 else if (parent == &clk_h)
144 clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
145 else
146 return -EINVAL;
147
148 clk->parent = parent;
149
150 __raw_writel(clksrc, S3C2412_CLKSRC);
151 return 0;
152}
153
154static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
155 unsigned long rate)
156{
157 unsigned long parent_rate = clk_get_rate(clk->parent);
158 int div;
159
160 if (rate > parent_rate)
161 return parent_rate;
162
163 div = parent_rate / rate;
164 if (div > 2)
165 div = 2;
166
167 return parent_rate / div;
168}
169
170static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
171{
172 unsigned long parent_rate = clk_get_rate(clk->parent);
173 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
174
175 return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
176}
177
178static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
179{
180 unsigned long parent_rate = clk_get_rate(clk->parent);
181 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
182
183 rate = s3c2412_roundrate_usbsrc(clk, rate);
184
185 if ((parent_rate / rate) == 2)
186 clkdivn |= S3C2412_CLKDIVN_USB48DIV;
187 else
188 clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
189
190 __raw_writel(clkdivn, S3C2410_CLKDIVN);
191 return 0;
192}
193
194static struct clk clk_usbsrc = {
195 .name = "usbsrc",
196 .ops = &(struct clk_ops) {
197 .get_rate = s3c2412_getrate_usbsrc,
198 .set_rate = s3c2412_setrate_usbsrc,
199 .round_rate = s3c2412_roundrate_usbsrc,
200 .set_parent = s3c2412_setparent_usbsrc,
201 },
202};
203
204static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
205{
206 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
207
208 if (parent == &clk_mdivclk)
209 clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
210 else if (parent == &clk_mpll)
211 clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
212 else
213 return -EINVAL;
214
215 clk->parent = parent;
216
217 __raw_writel(clksrc, S3C2412_CLKSRC);
218 return 0;
219}
220
221static struct clk clk_msysclk = {
222 .name = "msysclk",
223 .ops = &(struct clk_ops) {
224 .set_parent = s3c2412_setparent_msysclk,
225 },
226};
227
228static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
229{
230 unsigned long flags;
231 unsigned long clkdiv;
232 unsigned long dvs;
233
234 /* Note, we current equate fclk andf msysclk for S3C2412 */
235
236 if (parent == &clk_msysclk || parent == &clk_f)
237 dvs = 0;
238 else if (parent == &clk_h)
239 dvs = S3C2412_CLKDIVN_DVSEN;
240 else
241 return -EINVAL;
242
243 clk->parent = parent;
244
245 /* update this under irq lockdown, clkdivn is not protected
246 * by the clock system. */
247
248 local_irq_save(flags);
249
250 clkdiv = __raw_readl(S3C2410_CLKDIVN);
251 clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
252 clkdiv |= dvs;
253 __raw_writel(clkdiv, S3C2410_CLKDIVN);
254
255 local_irq_restore(flags);
256
257 return 0;
258}
259
260static struct clk clk_armclk = {
261 .name = "armclk",
262 .parent = &clk_msysclk,
263 .ops = &(struct clk_ops) {
264 .set_parent = s3c2412_setparent_armclk,
265 },
266};
267
268/* these next clocks have an divider immediately after them,
269 * so we can register them with their divider and leave out the
270 * intermediate clock stage
271*/
272static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
273 unsigned long rate)
274{
275 unsigned long parent_rate = clk_get_rate(clk->parent);
276 int div;
277
278 if (rate > parent_rate)
279 return parent_rate;
280
281 /* note, we remove the +/- 1 calculations as they cancel out */
282
283 div = (rate / parent_rate);
284
285 if (div < 1)
286 div = 1;
287 else if (div > 16)
288 div = 16;
289
290 return parent_rate / div;
291}
292
293static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
294{
295 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
296
297 if (parent == &clk_erefclk)
298 clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
299 else if (parent == &clk_mpll)
300 clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
301 else
302 return -EINVAL;
303
304 clk->parent = parent;
305
306 __raw_writel(clksrc, S3C2412_CLKSRC);
307 return 0;
308}
309
310static unsigned long s3c2412_getrate_uart(struct clk *clk)
311{
312 unsigned long parent_rate = clk_get_rate(clk->parent);
313 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
314
315 div &= S3C2412_CLKDIVN_UARTDIV_MASK;
316 div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
317
318 return parent_rate / (div + 1);
319}
320
321static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
322{
323 unsigned long parent_rate = clk_get_rate(clk->parent);
324 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
325
326 rate = s3c2412_roundrate_clksrc(clk, rate);
327
328 clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
329 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
330
331 __raw_writel(clkdivn, S3C2410_CLKDIVN);
332 return 0;
333}
334
335static struct clk clk_uart = {
336 .name = "uartclk",
337 .ops = &(struct clk_ops) {
338 .get_rate = s3c2412_getrate_uart,
339 .set_rate = s3c2412_setrate_uart,
340 .set_parent = s3c2412_setparent_uart,
341 .round_rate = s3c2412_roundrate_clksrc,
342 },
343};
344
345static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
346{
347 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
348
349 if (parent == &clk_erefclk)
350 clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
351 else if (parent == &clk_mpll)
352 clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
353 else
354 return -EINVAL;
355
356 clk->parent = parent;
357
358 __raw_writel(clksrc, S3C2412_CLKSRC);
359 return 0;
360}
361
362static unsigned long s3c2412_getrate_i2s(struct clk *clk)
363{
364 unsigned long parent_rate = clk_get_rate(clk->parent);
365 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
366
367 div &= S3C2412_CLKDIVN_I2SDIV_MASK;
368 div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
369
370 return parent_rate / (div + 1);
371}
372
373static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
374{
375 unsigned long parent_rate = clk_get_rate(clk->parent);
376 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
377
378 rate = s3c2412_roundrate_clksrc(clk, rate);
379
380 clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
381 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
382
383 __raw_writel(clkdivn, S3C2410_CLKDIVN);
384 return 0;
385}
386
387static struct clk clk_i2s = {
388 .name = "i2sclk",
389 .ops = &(struct clk_ops) {
390 .get_rate = s3c2412_getrate_i2s,
391 .set_rate = s3c2412_setrate_i2s,
392 .set_parent = s3c2412_setparent_i2s,
393 .round_rate = s3c2412_roundrate_clksrc,
394 },
395};
396
397static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
398{
399 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
400
401 if (parent == &clk_usysclk)
402 clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
403 else if (parent == &clk_h)
404 clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
405 else
406 return -EINVAL;
407
408 clk->parent = parent;
409
410 __raw_writel(clksrc, S3C2412_CLKSRC);
411 return 0;
412}
413static unsigned long s3c2412_getrate_cam(struct clk *clk)
414{
415 unsigned long parent_rate = clk_get_rate(clk->parent);
416 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
417
418 div &= S3C2412_CLKDIVN_CAMDIV_MASK;
419 div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
420
421 return parent_rate / (div + 1);
422}
423
424static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
425{
426 unsigned long parent_rate = clk_get_rate(clk->parent);
427 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
428
429 rate = s3c2412_roundrate_clksrc(clk, rate);
430
431 clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
432 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
433
434 __raw_writel(clkdivn, S3C2410_CLKDIVN);
435 return 0;
436}
437
438static struct clk clk_cam = {
439 .name = "camif-upll", /* same as 2440 name */
440 .ops = &(struct clk_ops) {
441 .get_rate = s3c2412_getrate_cam,
442 .set_rate = s3c2412_setrate_cam,
443 .set_parent = s3c2412_setparent_cam,
444 .round_rate = s3c2412_roundrate_clksrc,
445 },
446};
447
448/* standard clock definitions */
449
450static struct clk init_clocks_disable[] = {
451 {
452 .name = "nand",
453 .parent = &clk_h,
454 .enable = s3c2412_clkcon_enable,
455 .ctrlbit = S3C2412_CLKCON_NAND,
456 }, {
457 .name = "sdi",
458 .parent = &clk_p,
459 .enable = s3c2412_clkcon_enable,
460 .ctrlbit = S3C2412_CLKCON_SDI,
461 }, {
462 .name = "adc",
463 .parent = &clk_p,
464 .enable = s3c2412_clkcon_enable,
465 .ctrlbit = S3C2412_CLKCON_ADC,
466 }, {
467 .name = "i2c",
468 .parent = &clk_p,
469 .enable = s3c2412_clkcon_enable,
470 .ctrlbit = S3C2412_CLKCON_IIC,
471 }, {
472 .name = "iis",
473 .parent = &clk_p,
474 .enable = s3c2412_clkcon_enable,
475 .ctrlbit = S3C2412_CLKCON_IIS,
476 }, {
477 .name = "spi",
478 .parent = &clk_p,
479 .enable = s3c2412_clkcon_enable,
480 .ctrlbit = S3C2412_CLKCON_SPI,
481 }
482};
483
484static struct clk init_clocks[] = {
485 {
486 .name = "dma.0",
487 .parent = &clk_h,
488 .enable = s3c2412_clkcon_enable,
489 .ctrlbit = S3C2412_CLKCON_DMA0,
490 }, {
491 .name = "dma.1",
492 .parent = &clk_h,
493 .enable = s3c2412_clkcon_enable,
494 .ctrlbit = S3C2412_CLKCON_DMA1,
495 }, {
496 .name = "dma.2",
497 .parent = &clk_h,
498 .enable = s3c2412_clkcon_enable,
499 .ctrlbit = S3C2412_CLKCON_DMA2,
500 }, {
501 .name = "dma.3",
502 .parent = &clk_h,
503 .enable = s3c2412_clkcon_enable,
504 .ctrlbit = S3C2412_CLKCON_DMA3,
505 }, {
506 .name = "lcd",
507 .parent = &clk_h,
508 .enable = s3c2412_clkcon_enable,
509 .ctrlbit = S3C2412_CLKCON_LCDC,
510 }, {
511 .name = "gpio",
512 .parent = &clk_p,
513 .enable = s3c2412_clkcon_enable,
514 .ctrlbit = S3C2412_CLKCON_GPIO,
515 }, {
516 .name = "usb-host",
517 .parent = &clk_h,
518 .enable = s3c2412_clkcon_enable,
519 .ctrlbit = S3C2412_CLKCON_USBH,
520 }, {
521 .name = "usb-device",
522 .parent = &clk_h,
523 .enable = s3c2412_clkcon_enable,
524 .ctrlbit = S3C2412_CLKCON_USBD,
525 }, {
526 .name = "timers",
527 .parent = &clk_p,
528 .enable = s3c2412_clkcon_enable,
529 .ctrlbit = S3C2412_CLKCON_PWMT,
530 }, {
531 .name = "uart",
532 .devname = "s3c2412-uart.0",
533 .parent = &clk_p,
534 .enable = s3c2412_clkcon_enable,
535 .ctrlbit = S3C2412_CLKCON_UART0,
536 }, {
537 .name = "uart",
538 .devname = "s3c2412-uart.1",
539 .parent = &clk_p,
540 .enable = s3c2412_clkcon_enable,
541 .ctrlbit = S3C2412_CLKCON_UART1,
542 }, {
543 .name = "uart",
544 .devname = "s3c2412-uart.2",
545 .parent = &clk_p,
546 .enable = s3c2412_clkcon_enable,
547 .ctrlbit = S3C2412_CLKCON_UART2,
548 }, {
549 .name = "rtc",
550 .parent = &clk_p,
551 .enable = s3c2412_clkcon_enable,
552 .ctrlbit = S3C2412_CLKCON_RTC,
553 }, {
554 .name = "watchdog",
555 .parent = &clk_p,
556 .ctrlbit = 0,
557 }, {
558 .name = "usb-bus-gadget",
559 .parent = &clk_usb_bus,
560 .enable = s3c2412_clkcon_enable,
561 .ctrlbit = S3C2412_CLKCON_USB_DEV48,
562 }, {
563 .name = "usb-bus-host",
564 .parent = &clk_usb_bus,
565 .enable = s3c2412_clkcon_enable,
566 .ctrlbit = S3C2412_CLKCON_USB_HOST48,
567 }
568};
569
570/* clocks to add where we need to check their parentage */
571
572struct clk_init {
573 struct clk *clk;
574 unsigned int bit;
575 struct clk *src_0;
576 struct clk *src_1;
577};
578
579static struct clk_init clks_src[] __initdata = {
580 {
581 .clk = &clk_usysclk,
582 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
583 .src_0 = &clk_urefclk,
584 .src_1 = &clk_upll,
585 }, {
586 .clk = &clk_i2s,
587 .bit = S3C2412_CLKSRC_I2SCLK_MPLL,
588 .src_0 = &clk_erefclk,
589 .src_1 = &clk_mpll,
590 }, {
591 .clk = &clk_cam,
592 .bit = S3C2412_CLKSRC_CAMCLK_HCLK,
593 .src_0 = &clk_usysclk,
594 .src_1 = &clk_h,
595 }, {
596 .clk = &clk_msysclk,
597 .bit = S3C2412_CLKSRC_MSYSCLK_MPLL,
598 .src_0 = &clk_mdivclk,
599 .src_1 = &clk_mpll,
600 }, {
601 .clk = &clk_uart,
602 .bit = S3C2412_CLKSRC_UARTCLK_MPLL,
603 .src_0 = &clk_erefclk,
604 .src_1 = &clk_mpll,
605 }, {
606 .clk = &clk_usbsrc,
607 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
608 .src_0 = &clk_usysclk,
609 .src_1 = &clk_h,
610 /* here we assume OM[4] select xtal */
611 }, {
612 .clk = &clk_erefclk,
613 .bit = S3C2412_CLKSRC_EREFCLK_EXTCLK,
614 .src_0 = &clk_xtal,
615 .src_1 = &clk_ext,
616 }, {
617 .clk = &clk_urefclk,
618 .bit = S3C2412_CLKSRC_UREFCLK_EXTCLK,
619 .src_0 = &clk_xtal,
620 .src_1 = &clk_ext,
621 },
622};
623
624/* s3c2412_clk_initparents
625 *
626 * Initialise the parents for the clocks that we get at start-time
627*/
628
629static void __init s3c2412_clk_initparents(void)
630{
631 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
632 struct clk_init *cip = clks_src;
633 struct clk *src;
634 int ptr;
635 int ret;
636
637 for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
638 ret = s3c24xx_register_clock(cip->clk);
639 if (ret < 0) {
640 printk(KERN_ERR "Failed to register clock %s (%d)\n",
641 cip->clk->name, ret);
642 }
643
644 src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
645
646 printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
647 clk_set_parent(cip->clk, src);
648 }
649}
650
651/* clocks to add straight away */
652
653static struct clk *clks[] __initdata = {
654 &clk_ext,
655 &clk_usb_bus,
656 &clk_mrefclk,
657 &clk_armclk,
658};
659
660static struct clk_lookup s3c2412_clk_lookup[] = {
661 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
662 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
663 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
664};
665
666int __init s3c2412_baseclk_add(void)
667{
668 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
669 unsigned int dvs;
670 struct clk *clkp;
671 int ret;
672 int ptr;
673
674 clk_upll.enable = s3c2412_upll_enable;
675 clk_usb_bus.parent = &clk_usbsrc;
676 clk_usb_bus.rate = 0x0;
677
678 clk_f.parent = &clk_msysclk;
679
680 s3c2412_clk_initparents();
681
682 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
683 clkp = clks[ptr];
684
685 ret = s3c24xx_register_clock(clkp);
686 if (ret < 0) {
687 printk(KERN_ERR "Failed to register clock %s (%d)\n",
688 clkp->name, ret);
689 }
690 }
691
692 /* set the dvs state according to what we got at boot time */
693
694 dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
695
696 if (dvs)
697 clk_armclk.parent = &clk_h;
698
699 printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
700
701 /* ensure usb bus clock is within correct rate of 48MHz */
702
703 if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
704 printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
705
706 /* for the moment, let's use the UPLL, and see if we can
707 * get 48MHz */
708
709 clk_set_parent(&clk_usysclk, &clk_upll);
710 clk_set_parent(&clk_usbsrc, &clk_usysclk);
711 clk_set_rate(&clk_usbsrc, 48*1000*1000);
712 }
713
714 printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
715 (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
716 print_mhz(clk_get_rate(&clk_upll)),
717 print_mhz(clk_get_rate(&clk_usb_bus)));
718
719 /* register clocks from clock array */
720
721 clkp = init_clocks;
722 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
723 /* ensure that we note the clock state */
724
725 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
726
727 ret = s3c24xx_register_clock(clkp);
728 if (ret < 0) {
729 printk(KERN_ERR "Failed to register clock %s (%d)\n",
730 clkp->name, ret);
731 }
732 }
733
734 /* We must be careful disabling the clocks we are not intending to
735 * be using at boot time, as subsystems such as the LCD which do
736 * their own DMA requests to the bus can cause the system to lockup
737 * if they where in the middle of requesting bus access.
738 *
739 * Disabling the LCD clock if the LCD is active is very dangerous,
740 * and therefore the bootloader should be careful to not enable
741 * the LCD clock if it is not needed.
742 */
743
744 /* install (and disable) the clocks we do not need immediately */
745
746 clkp = init_clocks_disable;
747 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
748
749 ret = s3c24xx_register_clock(clkp);
750 if (ret < 0) {
751 printk(KERN_ERR "Failed to register clock %s (%d)\n",
752 clkp->name, ret);
753 }
754
755 s3c2412_clkcon_enable(clkp, 0);
756 }
757
758 clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
759 return 0;
760}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
deleted file mode 100644
index d421a72920a5..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ /dev/null
@@ -1,171 +0,0 @@
1/* linux/arch/arm/mach-s3c2416/clock.c
2 *
3 * Copyright (c) 2010 Simtec Electronics
4 * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
5 *
6 * S3C2416 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/init.h>
15#include <linux/clk.h>
16
17#include <plat/clock.h>
18#include <plat/clock-clksrc.h>
19#include <plat/cpu.h>
20
21#include <plat/cpu-freq.h>
22#include <plat/pll.h>
23
24#include <asm/mach/map.h>
25
26#include <mach/regs-clock.h>
27#include <mach/regs-s3c2443-clock.h>
28
29/* armdiv
30 *
31 * this clock is sourced from msysclk and can have a number of
32 * divider values applied to it to then be fed into armclk.
33 * The real clock definition is done in s3c2443-clock.c,
34 * only the armdiv divisor table must be defined here.
35*/
36
37static unsigned int armdiv[8] = {
38 [0] = 1,
39 [1] = 2,
40 [2] = 3,
41 [3] = 4,
42 [5] = 6,
43 [7] = 8,
44};
45
46static struct clksrc_clk hsspi_eplldiv = {
47 .clk = {
48 .name = "hsspi-eplldiv",
49 .parent = &clk_esysclk.clk,
50 .ctrlbit = (1 << 14),
51 .enable = s3c2443_clkcon_enable_s,
52 },
53 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
54};
55
56static struct clk *hsspi_sources[] = {
57 [0] = &hsspi_eplldiv.clk,
58 [1] = NULL, /* to fix */
59};
60
61static struct clksrc_clk hsspi_mux = {
62 .clk = {
63 .name = "hsspi-if",
64 },
65 .sources = &(struct clksrc_sources) {
66 .sources = hsspi_sources,
67 .nr_sources = ARRAY_SIZE(hsspi_sources),
68 },
69 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
70};
71
72static struct clksrc_clk hsmmc_div[] = {
73 [0] = {
74 .clk = {
75 .name = "hsmmc-div",
76 .devname = "s3c-sdhci.0",
77 .parent = &clk_esysclk.clk,
78 },
79 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
80 },
81 [1] = {
82 .clk = {
83 .name = "hsmmc-div",
84 .devname = "s3c-sdhci.1",
85 .parent = &clk_esysclk.clk,
86 },
87 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
88 },
89};
90
91static struct clksrc_clk hsmmc_mux0 = {
92 .clk = {
93 .name = "hsmmc-if",
94 .devname = "s3c-sdhci.0",
95 .ctrlbit = (1 << 6),
96 .enable = s3c2443_clkcon_enable_s,
97 },
98 .sources = &(struct clksrc_sources) {
99 .nr_sources = 2,
100 .sources = (struct clk * []) {
101 [0] = &hsmmc_div[0].clk,
102 [1] = NULL, /* to fix */
103 },
104 },
105 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
106};
107
108static struct clksrc_clk hsmmc_mux1 = {
109 .clk = {
110 .name = "hsmmc-if",
111 .devname = "s3c-sdhci.1",
112 .ctrlbit = (1 << 12),
113 .enable = s3c2443_clkcon_enable_s,
114 },
115 .sources = &(struct clksrc_sources) {
116 .nr_sources = 2,
117 .sources = (struct clk * []) {
118 [0] = &hsmmc_div[1].clk,
119 [1] = NULL, /* to fix */
120 },
121 },
122 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
123};
124
125static struct clk hsmmc0_clk = {
126 .name = "hsmmc",
127 .devname = "s3c-sdhci.0",
128 .parent = &clk_h,
129 .enable = s3c2443_clkcon_enable_h,
130 .ctrlbit = S3C2416_HCLKCON_HSMMC0,
131};
132
133static struct clksrc_clk *clksrcs[] __initdata = {
134 &hsspi_eplldiv,
135 &hsspi_mux,
136 &hsmmc_div[0],
137 &hsmmc_div[1],
138 &hsmmc_mux0,
139 &hsmmc_mux1,
140};
141
142static struct clk_lookup s3c2416_clk_lookup[] = {
143 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
144 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
145 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
146 /* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */
147 CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk),
148};
149
150void __init s3c2416_init_clocks(int xtal)
151{
152 u32 epllcon = __raw_readl(S3C2443_EPLLCON);
153 u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
154 int ptr;
155
156 /* s3c2416 EPLL compatible with s3c64xx */
157 clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
158
159 clk_epll.parent = &clk_epllref.clk;
160
161 s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
162 armdiv, ARRAY_SIZE(armdiv),
163 S3C2416_CLKDIV0_ARMDIV_MASK);
164
165 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
166 s3c_register_clksrc(clksrcs[ptr], 1);
167
168 s3c24xx_register_clock(&hsmmc0_clk);
169 clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
170
171}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
deleted file mode 100644
index 5527226fd61f..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ /dev/null
@@ -1,217 +0,0 @@
1/* linux/arch/arm/mach-s3c2440/clock.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2440 Clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/interrupt.h>
32#include <linux/ioport.h>
33#include <linux/mutex.h>
34#include <linux/clk.h>
35#include <linux/io.h>
36#include <linux/serial_core.h>
37#include <linux/serial_s3c.h>
38
39#include <mach/hardware.h>
40#include <linux/atomic.h>
41#include <asm/irq.h>
42
43#include <mach/regs-clock.h>
44
45#include <plat/clock.h>
46#include <plat/cpu.h>
47
48/* S3C2440 extended clock support */
49
50static unsigned long s3c2440_camif_upll_round(struct clk *clk,
51 unsigned long rate)
52{
53 unsigned long parent_rate = clk_get_rate(clk->parent);
54 int div;
55
56 if (rate > parent_rate)
57 return parent_rate;
58
59 /* note, we remove the +/- 1 calculations for the divisor */
60
61 div = (parent_rate / rate) / 2;
62
63 if (div < 1)
64 div = 1;
65 else if (div > 16)
66 div = 16;
67
68 return parent_rate / (div * 2);
69}
70
71static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
72{
73 unsigned long parent_rate = clk_get_rate(clk->parent);
74 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
75
76 rate = s3c2440_camif_upll_round(clk, rate);
77
78 camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
79
80 if (rate != parent_rate) {
81 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
82 camdivn |= (((parent_rate / rate) / 2) - 1);
83 }
84
85 __raw_writel(camdivn, S3C2440_CAMDIVN);
86
87 return 0;
88}
89
90static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
91{
92 unsigned long parent_rate = clk_get_rate(clk->parent);
93 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
94
95 if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL))
96 return parent_rate;
97
98 camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK;
99
100 return parent_rate / (camdivn + 1) / 2;
101}
102
103/* Extra S3C2440 clocks */
104
105static struct clk s3c2440_clk_cam = {
106 .name = "camif",
107 .enable = s3c2410_clkcon_enable,
108 .ctrlbit = S3C2440_CLKCON_CAMERA,
109};
110
111static struct clk s3c2440_clk_cam_upll = {
112 .name = "camif-upll",
113 .ops = &(struct clk_ops) {
114 .set_rate = s3c2440_camif_upll_setrate,
115 .get_rate = s3c2440_camif_upll_getrate,
116 .round_rate = s3c2440_camif_upll_round,
117 },
118};
119
120static struct clk s3c2440_clk_ac97 = {
121 .name = "ac97",
122 .enable = s3c2410_clkcon_enable,
123 .ctrlbit = S3C2440_CLKCON_AC97,
124};
125
126#define S3C24XX_VA_UART0 (S3C_VA_UART)
127#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
128#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
129#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
130
131static unsigned long s3c2440_fclk_n_getrate(struct clk *clk)
132{
133 unsigned long ucon0, ucon1, ucon2, divisor;
134
135 /* the fun of calculating the uart divisors on the s3c2440 */
136 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
137 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
138 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
139
140 ucon0 &= S3C2440_UCON0_DIVMASK;
141 ucon1 &= S3C2440_UCON1_DIVMASK;
142 ucon2 &= S3C2440_UCON2_DIVMASK;
143
144 if (ucon0 != 0)
145 divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
146 else if (ucon1 != 0)
147 divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
148 else if (ucon2 != 0)
149 divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
150 else
151 /* manual calims 44, seems to be 9 */
152 divisor = 9;
153
154 return clk_get_rate(clk->parent) / divisor;
155}
156
157static struct clk s3c2440_clk_fclk_n = {
158 .name = "fclk_n",
159 .parent = &clk_f,
160 .ops = &(struct clk_ops) {
161 .get_rate = s3c2440_fclk_n_getrate,
162 },
163};
164
165static struct clk_lookup s3c2440_clk_lookup[] = {
166 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
167 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
168 CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
169 CLKDEV_INIT("s3c2440-uart.0", "uart", &s3c24xx_clk_uart0),
170 CLKDEV_INIT("s3c2440-uart.1", "uart", &s3c24xx_clk_uart1),
171 CLKDEV_INIT("s3c2440-uart.2", "uart", &s3c24xx_clk_uart2),
172 CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll),
173};
174
175static int __init_refok s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
176{
177 struct clk *clock_upll;
178 struct clk *clock_h;
179 struct clk *clock_p;
180
181 clock_p = clk_get(NULL, "pclk");
182 clock_h = clk_get(NULL, "hclk");
183 clock_upll = clk_get(NULL, "upll");
184
185 if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
186 printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
187 return -EINVAL;
188 }
189
190 s3c2440_clk_cam.parent = clock_h;
191 s3c2440_clk_ac97.parent = clock_p;
192 s3c2440_clk_cam_upll.parent = clock_upll;
193 s3c24xx_register_clock(&s3c2440_clk_fclk_n);
194
195 s3c24xx_register_clock(&s3c2440_clk_ac97);
196 s3c24xx_register_clock(&s3c2440_clk_cam);
197 s3c24xx_register_clock(&s3c2440_clk_cam_upll);
198 clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));
199
200 clk_disable(&s3c2440_clk_ac97);
201 clk_disable(&s3c2440_clk_cam);
202
203 return 0;
204}
205
206static struct subsys_interface s3c2440_clk_interface = {
207 .name = "s3c2440_clk",
208 .subsys = &s3c2440_subsys,
209 .add_dev = s3c2440_clk_add,
210};
211
212static __init int s3c24xx_clk_init(void)
213{
214 return subsys_interface_register(&s3c2440_clk_interface);
215}
216
217arch_initcall(s3c24xx_clk_init);
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
deleted file mode 100644
index 76cd31f7804e..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ /dev/null
@@ -1,212 +0,0 @@
1/* linux/arch/arm/mach-s3c2443/clock.c
2 *
3 * Copyright (c) 2007, 2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2443 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/init.h>
24
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/clk.h>
32#include <linux/mutex.h>
33#include <linux/serial_core.h>
34#include <linux/io.h>
35
36#include <asm/mach/map.h>
37
38#include <mach/hardware.h>
39
40#include <mach/regs-s3c2443-clock.h>
41
42#include <plat/cpu-freq.h>
43
44#include <plat/clock.h>
45#include <plat/clock-clksrc.h>
46#include <plat/cpu.h>
47
48/* We currently have to assume that the system is running
49 * from the XTPll input, and that all ***REFCLKs are being
50 * fed from it, as we cannot read the state of OM[4] from
51 * software.
52 *
53 * It would be possible for each board initialisation to
54 * set the correct muxing at initialisation
55*/
56
57/* clock selections */
58
59/* armdiv
60 *
61 * this clock is sourced from msysclk and can have a number of
62 * divider values applied to it to then be fed into armclk.
63 * The real clock definition is done in s3c2443-clock.c,
64 * only the armdiv divisor table must be defined here.
65*/
66
67static unsigned int armdiv[16] = {
68 [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1,
69 [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2,
70 [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3,
71 [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4,
72 [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6,
73 [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8,
74 [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12,
75 [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
76};
77
78/* hsspi
79 *
80 * high-speed spi clock, sourced from esysclk
81*/
82
83static struct clksrc_clk clk_hsspi = {
84 .clk = {
85 .name = "hsspi-if",
86 .parent = &clk_esysclk.clk,
87 .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
88 .enable = s3c2443_clkcon_enable_s,
89 },
90 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
91};
92
93
94/* clk_hsmcc_div
95 *
96 * this clock is sourced from epll, and is fed through a divider,
97 * to a mux controlled by sclkcon where either it or a extclk can
98 * be fed to the hsmmc block
99*/
100
101static struct clksrc_clk clk_hsmmc_div = {
102 .clk = {
103 .name = "hsmmc-div",
104 .devname = "s3c-sdhci.1",
105 .parent = &clk_esysclk.clk,
106 },
107 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
108};
109
110static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
111{
112 unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
113
114 clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
115 S3C2443_SCLKCON_HSMMCCLK_EPLL);
116
117 if (parent == &clk_epll)
118 clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
119 else if (parent == &clk_ext)
120 clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
121 else
122 return -EINVAL;
123
124 if (clk->usage > 0) {
125 __raw_writel(clksrc, S3C2443_SCLKCON);
126 }
127
128 clk->parent = parent;
129 return 0;
130}
131
132static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
133{
134 return s3c2443_setparent_hsmmc(clk, clk->parent);
135}
136
137static struct clk clk_hsmmc = {
138 .name = "hsmmc-if",
139 .devname = "s3c-sdhci.1",
140 .parent = &clk_hsmmc_div.clk,
141 .enable = s3c2443_enable_hsmmc,
142 .ops = &(struct clk_ops) {
143 .set_parent = s3c2443_setparent_hsmmc,
144 },
145};
146
147/* standard clock definitions */
148
149static struct clk init_clocks_off[] = {
150 {
151 .name = "sdi",
152 .parent = &clk_p,
153 .enable = s3c2443_clkcon_enable_p,
154 .ctrlbit = S3C2443_PCLKCON_SDI,
155 }, {
156 .name = "spi",
157 .devname = "s3c2410-spi.0",
158 .parent = &clk_p,
159 .enable = s3c2443_clkcon_enable_p,
160 .ctrlbit = S3C2443_PCLKCON_SPI1,
161 }
162};
163
164/* clocks to add straight away */
165
166static struct clksrc_clk *clksrcs[] __initdata = {
167 &clk_hsspi,
168 &clk_hsmmc_div,
169};
170
171static struct clk *clks[] __initdata = {
172 &clk_hsmmc,
173};
174
175static struct clk_lookup s3c2443_clk_lookup[] = {
176 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
177 CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk),
178};
179
180void __init s3c2443_init_clocks(int xtal)
181{
182 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
183 int ptr;
184
185 clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
186 clk_epll.parent = &clk_epllref.clk;
187
188 s3c2443_common_init_clocks(xtal, s3c2443_get_mpll,
189 armdiv, ARRAY_SIZE(armdiv),
190 S3C2443_CLKDIV0_ARMDIV_MASK);
191
192 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
193
194 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
195 s3c_register_clksrc(clksrcs[ptr], 1);
196
197 /* We must be careful disabling the clocks we are not intending to
198 * be using at boot time, as subsystems such as the LCD which do
199 * their own DMA requests to the bus can cause the system to lockup
200 * if they where in the middle of requesting bus access.
201 *
202 * Disabling the LCD clock if the LCD is active is very dangerous,
203 * and therefore the bootloader should be careful to not enable
204 * the LCD clock if it is not needed.
205 */
206
207 /* install (and disable) the clocks we do not need immediately */
208
209 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
210 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
211 clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
212}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c244x.c b/arch/arm/mach-s3c24xx/clock-s3c244x.c
deleted file mode 100644
index 6d9b688c442b..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c244x.c
+++ /dev/null
@@ -1,141 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c
2 *
3 * Copyright (c) 2004-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2440/S3C2442 Common clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/interrupt.h>
32#include <linux/ioport.h>
33#include <linux/clk.h>
34#include <linux/io.h>
35
36#include <mach/hardware.h>
37#include <linux/atomic.h>
38#include <asm/irq.h>
39
40#include <mach/regs-clock.h>
41
42#include <plat/clock.h>
43#include <plat/cpu.h>
44
45static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent)
46{
47 unsigned long camdivn;
48 unsigned long dvs;
49
50 if (parent == &clk_f)
51 dvs = 0;
52 else if (parent == &clk_h)
53 dvs = S3C2440_CAMDIVN_DVSEN;
54 else
55 return -EINVAL;
56
57 clk->parent = parent;
58
59 camdivn = __raw_readl(S3C2440_CAMDIVN);
60 camdivn &= ~S3C2440_CAMDIVN_DVSEN;
61 camdivn |= dvs;
62 __raw_writel(camdivn, S3C2440_CAMDIVN);
63
64 return 0;
65}
66
67static struct clk clk_arm = {
68 .name = "armclk",
69 .id = -1,
70 .ops = &(struct clk_ops) {
71 .set_parent = s3c2440_setparent_armclk,
72 },
73};
74
75static int s3c244x_clk_add(struct device *dev, struct subsys_interface *sif)
76{
77 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
78 unsigned long clkdivn;
79 struct clk *clock_upll;
80 int ret;
81
82 printk("S3C244X: Clock Support, DVS %s\n",
83 (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
84
85 clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f;
86
87 ret = s3c24xx_register_clock(&clk_arm);
88 if (ret < 0) {
89 printk(KERN_ERR "S3C24XX: Failed to add armclk (%d)\n", ret);
90 return ret;
91 }
92
93 clock_upll = clk_get(NULL, "upll");
94 if (IS_ERR(clock_upll)) {
95 printk(KERN_ERR "S3C244X: Failed to get upll clock\n");
96 return -ENOENT;
97 }
98
99 /* check rate of UPLL, and if it is near 96MHz, then change
100 * to using half the UPLL rate for the system */
101
102 if (clk_get_rate(clock_upll) > (94 * MHZ)) {
103 clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
104
105 spin_lock(&clocks_lock);
106
107 clkdivn = __raw_readl(S3C2410_CLKDIVN);
108 clkdivn |= S3C2440_CLKDIVN_UCLK;
109 __raw_writel(clkdivn, S3C2410_CLKDIVN);
110
111 spin_unlock(&clocks_lock);
112 }
113
114 return 0;
115}
116
117static struct subsys_interface s3c2440_clk_interface = {
118 .name = "s3c2440_clk",
119 .subsys = &s3c2440_subsys,
120 .add_dev = s3c244x_clk_add,
121};
122
123static int s3c2440_clk_init(void)
124{
125 return subsys_interface_register(&s3c2440_clk_interface);
126}
127
128arch_initcall(s3c2440_clk_init);
129
130static struct subsys_interface s3c2442_clk_interface = {
131 .name = "s3c2442_clk",
132 .subsys = &s3c2442_subsys,
133 .add_dev = s3c244x_clk_add,
134};
135
136static int s3c2442_clk_init(void)
137{
138 return subsys_interface_register(&s3c2442_clk_interface);
139}
140
141arch_initcall(s3c2442_clk_init);
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
deleted file mode 100644
index 65d3eef73090..000000000000
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ /dev/null
@@ -1,675 +0,0 @@
1/*
2 * Common code for SoCs starting with the S3C2443
3 *
4 * Copyright (c) 2007, 2010 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21
22#include <mach/regs-s3c2443-clock.h>
23
24#include <plat/clock.h>
25#include <plat/clock-clksrc.h>
26#include <plat/cpu.h>
27
28#include <plat/cpu-freq.h>
29
30
31static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
32{
33 u32 ctrlbit = clk->ctrlbit;
34 u32 con = __raw_readl(reg);
35
36 if (enable)
37 con |= ctrlbit;
38 else
39 con &= ~ctrlbit;
40
41 __raw_writel(con, reg);
42 return 0;
43}
44
45int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
46{
47 return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
48}
49
50int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
51{
52 return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
53}
54
55int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
56{
57 return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
58}
59
60/* mpllref is a direct descendant of clk_xtal by default, but it is not
61 * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
62 * such directly equating the two source clocks is impossible.
63 */
64static struct clk clk_mpllref = {
65 .name = "mpllref",
66 .parent = &clk_xtal,
67};
68
69static struct clk *clk_epllref_sources[] = {
70 [0] = &clk_mpllref,
71 [1] = &clk_mpllref,
72 [2] = &clk_xtal,
73 [3] = &clk_ext,
74};
75
76struct clksrc_clk clk_epllref = {
77 .clk = {
78 .name = "epllref",
79 },
80 .sources = &(struct clksrc_sources) {
81 .sources = clk_epllref_sources,
82 .nr_sources = ARRAY_SIZE(clk_epllref_sources),
83 },
84 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
85};
86
87/* esysclk
88 *
89 * this is sourced from either the EPLL or the EPLLref clock
90*/
91
92static struct clk *clk_sysclk_sources[] = {
93 [0] = &clk_epllref.clk,
94 [1] = &clk_epll,
95};
96
97struct clksrc_clk clk_esysclk = {
98 .clk = {
99 .name = "esysclk",
100 .parent = &clk_epll,
101 },
102 .sources = &(struct clksrc_sources) {
103 .sources = clk_sysclk_sources,
104 .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
105 },
106 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
107};
108
109static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
110{
111 unsigned long parent_rate = clk_get_rate(clk->parent);
112 unsigned long div = __raw_readl(S3C2443_CLKDIV0);
113
114 div &= S3C2443_CLKDIV0_EXTDIV_MASK;
115 div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
116
117 return parent_rate / (div + 1);
118}
119
120static struct clk clk_mdivclk = {
121 .name = "mdivclk",
122 .parent = &clk_mpllref,
123 .ops = &(struct clk_ops) {
124 .get_rate = s3c2443_getrate_mdivclk,
125 },
126};
127
128static struct clk *clk_msysclk_sources[] = {
129 [0] = &clk_mpllref,
130 [1] = &clk_mpll,
131 [2] = &clk_mdivclk,
132 [3] = &clk_mpllref,
133};
134
135static struct clksrc_clk clk_msysclk = {
136 .clk = {
137 .name = "msysclk",
138 .parent = &clk_xtal,
139 },
140 .sources = &(struct clksrc_sources) {
141 .sources = clk_msysclk_sources,
142 .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
143 },
144 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
145};
146
147/* prediv
148 *
149 * this divides the msysclk down to pass to h/p/etc.
150 */
151
152static unsigned long s3c2443_prediv_getrate(struct clk *clk)
153{
154 unsigned long rate = clk_get_rate(clk->parent);
155 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
156
157 clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
158 clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
159
160 return rate / (clkdiv0 + 1);
161}
162
163static struct clk clk_prediv = {
164 .name = "prediv",
165 .parent = &clk_msysclk.clk,
166 .ops = &(struct clk_ops) {
167 .get_rate = s3c2443_prediv_getrate,
168 },
169};
170
171/* hclk divider
172 *
173 * divides the prediv and provides the hclk.
174 */
175
176static unsigned long s3c2443_hclkdiv_getrate(struct clk *clk)
177{
178 unsigned long rate = clk_get_rate(clk->parent);
179 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
180
181 clkdiv0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
182
183 return rate / (clkdiv0 + 1);
184}
185
186static struct clk_ops clk_h_ops = {
187 .get_rate = s3c2443_hclkdiv_getrate,
188};
189
190/* pclk divider
191 *
192 * divides the hclk and provides the pclk.
193 */
194
195static unsigned long s3c2443_pclkdiv_getrate(struct clk *clk)
196{
197 unsigned long rate = clk_get_rate(clk->parent);
198 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
199
200 clkdiv0 = ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 1 : 0);
201
202 return rate / (clkdiv0 + 1);
203}
204
205static struct clk_ops clk_p_ops = {
206 .get_rate = s3c2443_pclkdiv_getrate,
207};
208
209/* armdiv
210 *
211 * this clock is sourced from msysclk and can have a number of
212 * divider values applied to it to then be fed into armclk.
213*/
214
215static unsigned int *armdiv;
216static int nr_armdiv;
217static int armdivmask;
218
219static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
220 unsigned long rate)
221{
222 unsigned long parent = clk_get_rate(clk->parent);
223 unsigned long calc;
224 unsigned best = 256; /* bigger than any value */
225 unsigned div;
226 int ptr;
227
228 if (!nr_armdiv)
229 return -EINVAL;
230
231 for (ptr = 0; ptr < nr_armdiv; ptr++) {
232 div = armdiv[ptr];
233 if (div) {
234 /* cpufreq provides 266mhz as 266666000 not 266666666 */
235 calc = (parent / div / 1000) * 1000;
236 if (calc <= rate && div < best)
237 best = div;
238 }
239 }
240
241 return parent / best;
242}
243
244static unsigned long s3c2443_armclk_getrate(struct clk *clk)
245{
246 unsigned long rate = clk_get_rate(clk->parent);
247 unsigned long clkcon0;
248 int val;
249
250 if (!nr_armdiv || !armdivmask)
251 return -EINVAL;
252
253 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
254 clkcon0 &= armdivmask;
255 val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT;
256
257 return rate / armdiv[val];
258}
259
260static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
261{
262 unsigned long parent = clk_get_rate(clk->parent);
263 unsigned long calc;
264 unsigned div;
265 unsigned best = 256; /* bigger than any value */
266 int ptr;
267 int val = -1;
268
269 if (!nr_armdiv || !armdivmask)
270 return -EINVAL;
271
272 for (ptr = 0; ptr < nr_armdiv; ptr++) {
273 div = armdiv[ptr];
274 if (div) {
275 /* cpufreq provides 266mhz as 266666000 not 266666666 */
276 calc = (parent / div / 1000) * 1000;
277 if (calc <= rate && div < best) {
278 best = div;
279 val = ptr;
280 }
281 }
282 }
283
284 if (val >= 0) {
285 unsigned long clkcon0;
286
287 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
288 clkcon0 &= ~armdivmask;
289 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
290 __raw_writel(clkcon0, S3C2443_CLKDIV0);
291 }
292
293 return (val == -1) ? -EINVAL : 0;
294}
295
296static struct clk clk_armdiv = {
297 .name = "armdiv",
298 .parent = &clk_msysclk.clk,
299 .ops = &(struct clk_ops) {
300 .round_rate = s3c2443_armclk_roundrate,
301 .get_rate = s3c2443_armclk_getrate,
302 .set_rate = s3c2443_armclk_setrate,
303 },
304};
305
306/* armclk
307 *
308 * this is the clock fed into the ARM core itself, from armdiv or from hclk.
309 */
310
311static struct clk *clk_arm_sources[] = {
312 [0] = &clk_armdiv,
313 [1] = &clk_h,
314};
315
316static struct clksrc_clk clk_arm = {
317 .clk = {
318 .name = "armclk",
319 },
320 .sources = &(struct clksrc_sources) {
321 .sources = clk_arm_sources,
322 .nr_sources = ARRAY_SIZE(clk_arm_sources),
323 },
324 .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
325};
326
327/* usbhost
328 *
329 * usb host bus-clock, usually 48MHz to provide USB bus clock timing
330*/
331
332static struct clksrc_clk clk_usb_bus_host = {
333 .clk = {
334 .name = "usb-bus-host-parent",
335 .parent = &clk_esysclk.clk,
336 .ctrlbit = S3C2443_SCLKCON_USBHOST,
337 .enable = s3c2443_clkcon_enable_s,
338 },
339 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
340};
341
342/* common clksrc clocks */
343
344static struct clksrc_clk clksrc_clks[] = {
345 {
346 /* camera interface bus-clock, divided down from esysclk */
347 .clk = {
348 .name = "camif-upll", /* same as 2440 name */
349 .parent = &clk_esysclk.clk,
350 .ctrlbit = S3C2443_SCLKCON_CAMCLK,
351 .enable = s3c2443_clkcon_enable_s,
352 },
353 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
354 }, {
355 .clk = {
356 .name = "display-if",
357 .parent = &clk_esysclk.clk,
358 .ctrlbit = S3C2443_SCLKCON_DISPCLK,
359 .enable = s3c2443_clkcon_enable_s,
360 },
361 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
362 },
363};
364
365static struct clksrc_clk clk_esys_uart = {
366 /* ART baud-rate clock sourced from esysclk via a divisor */
367 .clk = {
368 .name = "uartclk",
369 .parent = &clk_esysclk.clk,
370 },
371 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
372};
373
374static struct clk clk_i2s_ext = {
375 .name = "i2s-ext",
376};
377
378/* i2s_eplldiv
379 *
380 * This clock is the output from the I2S divisor of ESYSCLK, and is separate
381 * from the mux that comes after it (cannot merge into one single clock)
382*/
383
384static struct clksrc_clk clk_i2s_eplldiv = {
385 .clk = {
386 .name = "i2s-eplldiv",
387 .parent = &clk_esysclk.clk,
388 },
389 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
390};
391
392/* i2s-ref
393 *
394 * i2s bus reference clock, selectable from external, esysclk or epllref
395 *
396 * Note, this used to be two clocks, but was compressed into one.
397*/
398
399static struct clk *clk_i2s_srclist[] = {
400 [0] = &clk_i2s_eplldiv.clk,
401 [1] = &clk_i2s_ext,
402 [2] = &clk_epllref.clk,
403 [3] = &clk_epllref.clk,
404};
405
406static struct clksrc_clk clk_i2s = {
407 .clk = {
408 .name = "i2s-if",
409 .ctrlbit = S3C2443_SCLKCON_I2SCLK,
410 .enable = s3c2443_clkcon_enable_s,
411
412 },
413 .sources = &(struct clksrc_sources) {
414 .sources = clk_i2s_srclist,
415 .nr_sources = ARRAY_SIZE(clk_i2s_srclist),
416 },
417 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
418};
419
420static struct clk init_clocks_off[] = {
421 {
422 .name = "iis",
423 .parent = &clk_p,
424 .enable = s3c2443_clkcon_enable_p,
425 .ctrlbit = S3C2443_PCLKCON_IIS,
426 }, {
427 .name = "adc",
428 .parent = &clk_p,
429 .enable = s3c2443_clkcon_enable_p,
430 .ctrlbit = S3C2443_PCLKCON_ADC,
431 }, {
432 .name = "i2c",
433 .parent = &clk_p,
434 .enable = s3c2443_clkcon_enable_p,
435 .ctrlbit = S3C2443_PCLKCON_IIC,
436 }
437};
438
439static struct clk init_clocks[] = {
440 {
441 .name = "dma.0",
442 .parent = &clk_h,
443 .enable = s3c2443_clkcon_enable_h,
444 .ctrlbit = S3C2443_HCLKCON_DMA0,
445 }, {
446 .name = "dma.1",
447 .parent = &clk_h,
448 .enable = s3c2443_clkcon_enable_h,
449 .ctrlbit = S3C2443_HCLKCON_DMA1,
450 }, {
451 .name = "dma.2",
452 .parent = &clk_h,
453 .enable = s3c2443_clkcon_enable_h,
454 .ctrlbit = S3C2443_HCLKCON_DMA2,
455 }, {
456 .name = "dma.3",
457 .parent = &clk_h,
458 .enable = s3c2443_clkcon_enable_h,
459 .ctrlbit = S3C2443_HCLKCON_DMA3,
460 }, {
461 .name = "dma.4",
462 .parent = &clk_h,
463 .enable = s3c2443_clkcon_enable_h,
464 .ctrlbit = S3C2443_HCLKCON_DMA4,
465 }, {
466 .name = "dma.5",
467 .parent = &clk_h,
468 .enable = s3c2443_clkcon_enable_h,
469 .ctrlbit = S3C2443_HCLKCON_DMA5,
470 }, {
471 .name = "gpio",
472 .parent = &clk_p,
473 .enable = s3c2443_clkcon_enable_p,
474 .ctrlbit = S3C2443_PCLKCON_GPIO,
475 }, {
476 .name = "usb-host",
477 .parent = &clk_h,
478 .enable = s3c2443_clkcon_enable_h,
479 .ctrlbit = S3C2443_HCLKCON_USBH,
480 }, {
481 .name = "usb-device",
482 .parent = &clk_h,
483 .enable = s3c2443_clkcon_enable_h,
484 .ctrlbit = S3C2443_HCLKCON_USBD,
485 }, {
486 .name = "lcd",
487 .parent = &clk_h,
488 .enable = s3c2443_clkcon_enable_h,
489 .ctrlbit = S3C2443_HCLKCON_LCDC,
490
491 }, {
492 .name = "timers",
493 .parent = &clk_p,
494 .enable = s3c2443_clkcon_enable_p,
495 .ctrlbit = S3C2443_PCLKCON_PWMT,
496 }, {
497 .name = "cfc",
498 .parent = &clk_h,
499 .enable = s3c2443_clkcon_enable_h,
500 .ctrlbit = S3C2443_HCLKCON_CFC,
501 }, {
502 .name = "ssmc",
503 .parent = &clk_h,
504 .enable = s3c2443_clkcon_enable_h,
505 .ctrlbit = S3C2443_HCLKCON_SSMC,
506 }, {
507 .name = "uart",
508 .devname = "s3c2440-uart.0",
509 .parent = &clk_p,
510 .enable = s3c2443_clkcon_enable_p,
511 .ctrlbit = S3C2443_PCLKCON_UART0,
512 }, {
513 .name = "uart",
514 .devname = "s3c2440-uart.1",
515 .parent = &clk_p,
516 .enable = s3c2443_clkcon_enable_p,
517 .ctrlbit = S3C2443_PCLKCON_UART1,
518 }, {
519 .name = "uart",
520 .devname = "s3c2440-uart.2",
521 .parent = &clk_p,
522 .enable = s3c2443_clkcon_enable_p,
523 .ctrlbit = S3C2443_PCLKCON_UART2,
524 }, {
525 .name = "uart",
526 .devname = "s3c2440-uart.3",
527 .parent = &clk_p,
528 .enable = s3c2443_clkcon_enable_p,
529 .ctrlbit = S3C2443_PCLKCON_UART3,
530 }, {
531 .name = "rtc",
532 .parent = &clk_p,
533 .enable = s3c2443_clkcon_enable_p,
534 .ctrlbit = S3C2443_PCLKCON_RTC,
535 }, {
536 .name = "watchdog",
537 .parent = &clk_p,
538 .ctrlbit = S3C2443_PCLKCON_WDT,
539 }, {
540 .name = "ac97",
541 .parent = &clk_p,
542 .ctrlbit = S3C2443_PCLKCON_AC97,
543 }, {
544 .name = "nand",
545 .parent = &clk_h,
546 }, {
547 .name = "usb-bus-host",
548 .parent = &clk_usb_bus_host.clk,
549 }
550};
551
552static struct clk hsmmc1_clk = {
553 .name = "hsmmc",
554 .devname = "s3c-sdhci.1",
555 .parent = &clk_h,
556 .enable = s3c2443_clkcon_enable_h,
557 .ctrlbit = S3C2443_HCLKCON_HSMMC,
558};
559
560static struct clk hsspi_clk = {
561 .name = "spi",
562 .devname = "s3c2443-spi.0",
563 .parent = &clk_p,
564 .enable = s3c2443_clkcon_enable_p,
565 .ctrlbit = S3C2443_PCLKCON_HSSPI,
566};
567
568/* EPLLCON compatible enough to get on/off information */
569
570void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
571{
572 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
573 unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
574 struct clk *xtal_clk;
575 unsigned long xtal;
576 unsigned long pll;
577 int ptr;
578
579 xtal_clk = clk_get(NULL, "xtal");
580 xtal = clk_get_rate(xtal_clk);
581 clk_put(xtal_clk);
582
583 pll = get_mpll(mpllcon, xtal);
584 clk_msysclk.clk.rate = pll;
585 clk_mpll.rate = pll;
586
587 printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
588 (mpllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
589 print_mhz(pll), print_mhz(clk_get_rate(&clk_armdiv)),
590 print_mhz(clk_get_rate(&clk_h)),
591 print_mhz(clk_get_rate(&clk_p)));
592
593 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
594 s3c_set_clksrc(&clksrc_clks[ptr], true);
595
596 /* ensure usb bus clock is within correct rate of 48MHz */
597
598 if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
599 printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
600 clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
601 }
602
603 printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
604 (epllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
605 print_mhz(clk_get_rate(&clk_epll)),
606 print_mhz(clk_get_rate(&clk_usb_bus)));
607}
608
609static struct clk *clks[] __initdata = {
610 &clk_prediv,
611 &clk_mpllref,
612 &clk_mdivclk,
613 &clk_ext,
614 &clk_epll,
615 &clk_usb_bus,
616 &clk_armdiv,
617 &hsmmc1_clk,
618 &hsspi_clk,
619};
620
621static struct clksrc_clk *clksrcs[] __initdata = {
622 &clk_i2s_eplldiv,
623 &clk_i2s,
624 &clk_usb_bus_host,
625 &clk_epllref,
626 &clk_esysclk,
627 &clk_msysclk,
628 &clk_arm,
629};
630
631static struct clk_lookup s3c2443_clk_lookup[] = {
632 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
633 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
634 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
635 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
636 CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk),
637};
638
639void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
640 unsigned int *divs, int nr_divs,
641 int divmask)
642{
643 int ptr;
644
645 armdiv = divs;
646 nr_armdiv = nr_divs;
647 armdivmask = divmask;
648
649 /* s3c2443 parents h clock from prediv */
650 clk_h.parent = &clk_prediv;
651 clk_h.ops = &clk_h_ops;
652
653 /* and p clock from h clock */
654 clk_p.parent = &clk_h;
655 clk_p.ops = &clk_p_ops;
656
657 clk_usb_bus.parent = &clk_usb_bus_host.clk;
658 clk_epll.parent = &clk_epllref.clk;
659
660 s3c24xx_register_baseclocks(xtal);
661 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
662
663 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
664 s3c_register_clksrc(clksrcs[ptr], 1);
665
666 s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
667 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
668
669 /* See s3c2443/etc notes on disabling clocks at init time */
670 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
671 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
672 clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
673
674 s3c2443_common_setup_clocks(get_mpll);
675}
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 1bc8e73c94f9..c0763b837745 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -53,6 +53,7 @@
53#include <plat/cpu-freq.h> 53#include <plat/cpu-freq.h>
54#include <plat/pll.h> 54#include <plat/pll.h>
55#include <plat/pwm-core.h> 55#include <plat/pwm-core.h>
56#include <plat/watchdog-reset.h>
56 57
57#include "common.h" 58#include "common.h"
58 59
@@ -73,7 +74,6 @@ static struct cpu_table cpu_ids[] __initdata = {
73 .idcode = 0x32410000, 74 .idcode = 0x32410000,
74 .idmask = 0xffffffff, 75 .idmask = 0xffffffff,
75 .map_io = s3c2410_map_io, 76 .map_io = s3c2410_map_io,
76 .init_clocks = s3c2410_init_clocks,
77 .init_uarts = s3c2410_init_uarts, 77 .init_uarts = s3c2410_init_uarts,
78 .init = s3c2410_init, 78 .init = s3c2410_init,
79 .name = name_s3c2410 79 .name = name_s3c2410
@@ -82,7 +82,6 @@ static struct cpu_table cpu_ids[] __initdata = {
82 .idcode = 0x32410002, 82 .idcode = 0x32410002,
83 .idmask = 0xffffffff, 83 .idmask = 0xffffffff,
84 .map_io = s3c2410_map_io, 84 .map_io = s3c2410_map_io,
85 .init_clocks = s3c2410_init_clocks,
86 .init_uarts = s3c2410_init_uarts, 85 .init_uarts = s3c2410_init_uarts,
87 .init = s3c2410a_init, 86 .init = s3c2410a_init,
88 .name = name_s3c2410a 87 .name = name_s3c2410a
@@ -91,7 +90,6 @@ static struct cpu_table cpu_ids[] __initdata = {
91 .idcode = 0x32440000, 90 .idcode = 0x32440000,
92 .idmask = 0xffffffff, 91 .idmask = 0xffffffff,
93 .map_io = s3c2440_map_io, 92 .map_io = s3c2440_map_io,
94 .init_clocks = s3c244x_init_clocks,
95 .init_uarts = s3c244x_init_uarts, 93 .init_uarts = s3c244x_init_uarts,
96 .init = s3c2440_init, 94 .init = s3c2440_init,
97 .name = name_s3c2440 95 .name = name_s3c2440
@@ -100,7 +98,6 @@ static struct cpu_table cpu_ids[] __initdata = {
100 .idcode = 0x32440001, 98 .idcode = 0x32440001,
101 .idmask = 0xffffffff, 99 .idmask = 0xffffffff,
102 .map_io = s3c2440_map_io, 100 .map_io = s3c2440_map_io,
103 .init_clocks = s3c244x_init_clocks,
104 .init_uarts = s3c244x_init_uarts, 101 .init_uarts = s3c244x_init_uarts,
105 .init = s3c2440_init, 102 .init = s3c2440_init,
106 .name = name_s3c2440a 103 .name = name_s3c2440a
@@ -109,7 +106,6 @@ static struct cpu_table cpu_ids[] __initdata = {
109 .idcode = 0x32440aaa, 106 .idcode = 0x32440aaa,
110 .idmask = 0xffffffff, 107 .idmask = 0xffffffff,
111 .map_io = s3c2442_map_io, 108 .map_io = s3c2442_map_io,
112 .init_clocks = s3c244x_init_clocks,
113 .init_uarts = s3c244x_init_uarts, 109 .init_uarts = s3c244x_init_uarts,
114 .init = s3c2442_init, 110 .init = s3c2442_init,
115 .name = name_s3c2442 111 .name = name_s3c2442
@@ -118,7 +114,6 @@ static struct cpu_table cpu_ids[] __initdata = {
118 .idcode = 0x32440aab, 114 .idcode = 0x32440aab,
119 .idmask = 0xffffffff, 115 .idmask = 0xffffffff,
120 .map_io = s3c2442_map_io, 116 .map_io = s3c2442_map_io,
121 .init_clocks = s3c244x_init_clocks,
122 .init_uarts = s3c244x_init_uarts, 117 .init_uarts = s3c244x_init_uarts,
123 .init = s3c2442_init, 118 .init = s3c2442_init,
124 .name = name_s3c2442b 119 .name = name_s3c2442b
@@ -127,7 +122,6 @@ static struct cpu_table cpu_ids[] __initdata = {
127 .idcode = 0x32412001, 122 .idcode = 0x32412001,
128 .idmask = 0xffffffff, 123 .idmask = 0xffffffff,
129 .map_io = s3c2412_map_io, 124 .map_io = s3c2412_map_io,
130 .init_clocks = s3c2412_init_clocks,
131 .init_uarts = s3c2412_init_uarts, 125 .init_uarts = s3c2412_init_uarts,
132 .init = s3c2412_init, 126 .init = s3c2412_init,
133 .name = name_s3c2412, 127 .name = name_s3c2412,
@@ -136,7 +130,6 @@ static struct cpu_table cpu_ids[] __initdata = {
136 .idcode = 0x32412003, 130 .idcode = 0x32412003,
137 .idmask = 0xffffffff, 131 .idmask = 0xffffffff,
138 .map_io = s3c2412_map_io, 132 .map_io = s3c2412_map_io,
139 .init_clocks = s3c2412_init_clocks,
140 .init_uarts = s3c2412_init_uarts, 133 .init_uarts = s3c2412_init_uarts,
141 .init = s3c2412_init, 134 .init = s3c2412_init,
142 .name = name_s3c2412, 135 .name = name_s3c2412,
@@ -145,7 +138,6 @@ static struct cpu_table cpu_ids[] __initdata = {
145 .idcode = 0x32450003, 138 .idcode = 0x32450003,
146 .idmask = 0xffffffff, 139 .idmask = 0xffffffff,
147 .map_io = s3c2416_map_io, 140 .map_io = s3c2416_map_io,
148 .init_clocks = s3c2416_init_clocks,
149 .init_uarts = s3c2416_init_uarts, 141 .init_uarts = s3c2416_init_uarts,
150 .init = s3c2416_init, 142 .init = s3c2416_init,
151 .name = name_s3c2416, 143 .name = name_s3c2416,
@@ -154,7 +146,6 @@ static struct cpu_table cpu_ids[] __initdata = {
154 .idcode = 0x32443001, 146 .idcode = 0x32443001,
155 .idmask = 0xffffffff, 147 .idmask = 0xffffffff,
156 .map_io = s3c2443_map_io, 148 .map_io = s3c2443_map_io,
157 .init_clocks = s3c2443_init_clocks,
158 .init_uarts = s3c2443_init_uarts, 149 .init_uarts = s3c2443_init_uarts,
159 .init = s3c2443_init, 150 .init = s3c2443_init,
160 .name = name_s3c2443, 151 .name = name_s3c2443,
@@ -316,21 +307,6 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
316 }, 307 },
317}; 308};
318 309
319/* initialise all the clocks */
320
321void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
322 unsigned long hclk,
323 unsigned long pclk)
324{
325 clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
326 clk_xtal.rate);
327
328 clk_mpll.rate = fclk;
329 clk_h.rate = hclk;
330 clk_p.rate = pclk;
331 clk_f.rate = fclk;
332}
333
334#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ 310#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
335 defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) 311 defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
336static struct resource s3c2410_dma_resource[] = { 312static struct resource s3c2410_dma_resource[] = {
@@ -534,3 +510,62 @@ struct platform_device s3c2443_device_dma = {
534 }, 510 },
535}; 511};
536#endif 512#endif
513
514#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410)
515void __init s3c2410_init_clocks(int xtal)
516{
517 s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
518 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
519}
520#endif
521
522#ifdef CONFIG_CPU_S3C2412
523void __init s3c2412_init_clocks(int xtal)
524{
525 s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
526}
527#endif
528
529#ifdef CONFIG_CPU_S3C2416
530void __init s3c2416_init_clocks(int xtal)
531{
532 s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
533}
534#endif
535
536#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440)
537void __init s3c2440_init_clocks(int xtal)
538{
539 s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
540 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
541}
542#endif
543
544#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442)
545void __init s3c2442_init_clocks(int xtal)
546{
547 s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
548 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
549}
550#endif
551
552#ifdef CONFIG_CPU_S3C2443
553void __init s3c2443_init_clocks(int xtal)
554{
555 s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
556}
557#endif
558
559#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
560 defined(CONFIG_CPU_S3C2442)
561static struct resource s3c2410_dclk_resource[] = {
562 [0] = DEFINE_RES_MEM(0x56000084, 0x4),
563};
564
565struct platform_device s3c2410_device_dclk = {
566 .name = "s3c2410-dclk",
567 .id = 0,
568 .num_resources = ARRAY_SIZE(s3c2410_dclk_resource),
569 .resource = s3c2410_dclk_resource,
570};
571#endif
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index e46c10417216..ac3ff12a0601 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -67,16 +67,15 @@ extern struct syscore_ops s3c2416_irq_syscore_ops;
67#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) 67#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
68extern void s3c244x_map_io(void); 68extern void s3c244x_map_io(void);
69extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); 69extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
70extern void s3c244x_init_clocks(int xtal);
71extern void s3c244x_restart(enum reboot_mode mode, const char *cmd); 70extern void s3c244x_restart(enum reboot_mode mode, const char *cmd);
72#else 71#else
73#define s3c244x_init_clocks NULL
74#define s3c244x_init_uarts NULL 72#define s3c244x_init_uarts NULL
75#endif 73#endif
76 74
77#ifdef CONFIG_CPU_S3C2440 75#ifdef CONFIG_CPU_S3C2440
78extern int s3c2440_init(void); 76extern int s3c2440_init(void);
79extern void s3c2440_map_io(void); 77extern void s3c2440_map_io(void);
78extern void s3c2440_init_clocks(int xtal);
80extern void s3c2440_init_irq(void); 79extern void s3c2440_init_irq(void);
81#else 80#else
82#define s3c2440_init NULL 81#define s3c2440_init NULL
@@ -86,6 +85,7 @@ extern void s3c2440_init_irq(void);
86#ifdef CONFIG_CPU_S3C2442 85#ifdef CONFIG_CPU_S3C2442
87extern int s3c2442_init(void); 86extern int s3c2442_init(void);
88extern void s3c2442_map_io(void); 87extern void s3c2442_map_io(void);
88extern void s3c2442_init_clocks(int xtal);
89extern void s3c2442_init_irq(void); 89extern void s3c2442_init_irq(void);
90#else 90#else
91#define s3c2442_init NULL 91#define s3c2442_init NULL
@@ -114,4 +114,21 @@ extern struct platform_device s3c2412_device_dma;
114extern struct platform_device s3c2440_device_dma; 114extern struct platform_device s3c2440_device_dma;
115extern struct platform_device s3c2443_device_dma; 115extern struct platform_device s3c2443_device_dma;
116 116
117extern struct platform_device s3c2410_device_dclk;
118
119#ifdef CONFIG_S3C2410_COMMON_CLK
120void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
121 int current_soc,
122 void __iomem *reg_base);
123#endif
124#ifdef CONFIG_S3C2412_COMMON_CLK
125void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
126 unsigned long ext_f, void __iomem *reg_base);
127#endif
128#ifdef CONFIG_S3C2443_COMMON_CLK
129void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
130 int current_soc,
131 void __iomem *reg_base);
132#endif
133
117#endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */ 134#endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */
diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index 2a0aa5684e72..d4d9514335f4 100644
--- a/arch/arm/mach-s3c24xx/cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -14,6 +14,7 @@
14#include <linux/errno.h> 14#include <linux/errno.h>
15#include <linux/cpufreq.h> 15#include <linux/cpufreq.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/clk.h>
17 18
18#include <mach/map.h> 19#include <mach/map.h>
19#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
@@ -60,5 +61,6 @@ void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
60 */ 61 */
61void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg) 62void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
62{ 63{
63 __raw_writel(cfg->pll.driver_data, S3C2410_MPLLCON); 64 if (!IS_ERR(cfg->mpll))
65 clk_set_rate(cfg->mpll, cfg->pll.frequency);
64} 66}
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
index 3415b60082d7..3db6c10de023 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
@@ -42,24 +42,6 @@
42#define S3C2410_CLKCON_IIS (1<<17) 42#define S3C2410_CLKCON_IIS (1<<17)
43#define S3C2410_CLKCON_SPI (1<<18) 43#define S3C2410_CLKCON_SPI (1<<18)
44 44
45/* DCLKCON register addresses in gpio.h */
46
47#define S3C2410_DCLKCON_DCLK0EN (1<<0)
48#define S3C2410_DCLKCON_DCLK0_PCLK (0<<1)
49#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
50#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
51#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
52#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
53#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
54
55#define S3C2410_DCLKCON_DCLK1EN (1<<16)
56#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
57#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
58#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
59#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
60#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
61#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
62
63#define S3C2410_CLKDIVN_PDIVN (1<<0) 45#define S3C2410_CLKDIVN_PDIVN (1<<0)
64#define S3C2410_CLKDIVN_HDIVN (1<<1) 46#define S3C2410_CLKDIVN_HDIVN (1<<1)
65 47
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
index c2ef016032ab..c6583cfa5835 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
@@ -457,9 +457,6 @@
457 457
458/* miscellaneous control */ 458/* miscellaneous control */
459#define S3C2410_MISCCR S3C2410_GPIOREG(0x80) 459#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
460#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
461
462#define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84)
463 460
464/* see clock.h for dclk definitions */ 461/* see clock.h for dclk definitions */
465 462
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 8ac9554aa996..5157e250dd13 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -161,11 +161,16 @@ static struct platform_device *amlm5900_devices[] __initdata = {
161static void __init amlm5900_map_io(void) 161static void __init amlm5900_map_io(void)
162{ 162{
163 s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc)); 163 s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
164 s3c24xx_init_clocks(0);
165 s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs)); 164 s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
166 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 165 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
167} 166}
168 167
168static void __init amlm5900_init_time(void)
169{
170 s3c2410_init_clocks(12000000);
171 samsung_timer_init();
172}
173
169#ifdef CONFIG_FB_S3C2410 174#ifdef CONFIG_FB_S3C2410
170static struct s3c2410fb_display __initdata amlm5900_lcd_info = { 175static struct s3c2410fb_display __initdata amlm5900_lcd_info = {
171 .width = 160, 176 .width = 160,
@@ -241,6 +246,6 @@ MACHINE_START(AML_M5900, "AML_M5900")
241 .map_io = amlm5900_map_io, 246 .map_io = amlm5900_map_io,
242 .init_irq = s3c2410_init_irq, 247 .init_irq = s3c2410_init_irq,
243 .init_machine = amlm5900_init, 248 .init_machine = amlm5900_init,
244 .init_time = samsung_timer_init, 249 .init_time = amlm5900_init_time,
245 .restart = s3c2410_restart, 250 .restart = s3c2410_restart,
246MACHINE_END 251MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 81a270af2336..e053581cab0b 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -46,7 +46,6 @@
46 46
47#include <net/ax88796.h> 47#include <net/ax88796.h>
48 48
49#include <plat/clock.h>
50#include <plat/devs.h> 49#include <plat/devs.h>
51#include <plat/cpu.h> 50#include <plat/cpu.h>
52#include <linux/platform_data/asoc-s3c24xx_simtec.h> 51#include <linux/platform_data/asoc-s3c24xx_simtec.h>
@@ -352,6 +351,7 @@ static struct platform_device anubis_device_sm501 = {
352/* Standard Anubis devices */ 351/* Standard Anubis devices */
353 352
354static struct platform_device *anubis_devices[] __initdata = { 353static struct platform_device *anubis_devices[] __initdata = {
354 &s3c2410_device_dclk,
355 &s3c_device_ohci, 355 &s3c_device_ohci,
356 &s3c_device_wdt, 356 &s3c_device_wdt,
357 &s3c_device_adc, 357 &s3c_device_adc,
@@ -364,14 +364,6 @@ static struct platform_device *anubis_devices[] __initdata = {
364 &anubis_device_sm501, 364 &anubis_device_sm501,
365}; 365};
366 366
367static struct clk *anubis_clocks[] __initdata = {
368 &s3c24xx_dclk0,
369 &s3c24xx_dclk1,
370 &s3c24xx_clkout0,
371 &s3c24xx_clkout1,
372 &s3c24xx_uclk,
373};
374
375/* I2C devices. */ 367/* I2C devices. */
376 368
377static struct i2c_board_info anubis_i2c_devs[] __initdata = { 369static struct i2c_board_info anubis_i2c_devs[] __initdata = {
@@ -394,23 +386,7 @@ static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
394 386
395static void __init anubis_map_io(void) 387static void __init anubis_map_io(void)
396{ 388{
397 /* initialise the clocks */
398
399 s3c24xx_dclk0.parent = &clk_upll;
400 s3c24xx_dclk0.rate = 12*1000*1000;
401
402 s3c24xx_dclk1.parent = &clk_upll;
403 s3c24xx_dclk1.rate = 24*1000*1000;
404
405 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
406 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
407
408 s3c24xx_uclk.parent = &s3c24xx_clkout1;
409
410 s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
411
412 s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); 389 s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
413 s3c24xx_init_clocks(0);
414 s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); 390 s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
415 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 391 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
416 392
@@ -428,6 +404,12 @@ static void __init anubis_map_io(void)
428 } 404 }
429} 405}
430 406
407static void __init anubis_init_time(void)
408{
409 s3c2440_init_clocks(12000000);
410 samsung_timer_init();
411}
412
431static void __init anubis_init(void) 413static void __init anubis_init(void)
432{ 414{
433 s3c_i2c0_set_platdata(NULL); 415 s3c_i2c0_set_platdata(NULL);
@@ -447,6 +429,6 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
447 .map_io = anubis_map_io, 429 .map_io = anubis_map_io,
448 .init_machine = anubis_init, 430 .init_machine = anubis_init,
449 .init_irq = s3c2440_init_irq, 431 .init_irq = s3c2440_init_irq,
450 .init_time = samsung_timer_init, 432 .init_time = anubis_init_time,
451 .restart = s3c244x_restart, 433 .restart = s3c244x_restart,
452MACHINE_END 434MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index d8f6bb1096cb..9db768f448a5 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -45,7 +45,6 @@
45#include <linux/mtd/nand_ecc.h> 45#include <linux/mtd/nand_ecc.h>
46#include <linux/mtd/partitions.h> 46#include <linux/mtd/partitions.h>
47 47
48#include <plat/clock.h>
49#include <plat/devs.h> 48#include <plat/devs.h>
50#include <plat/cpu.h> 49#include <plat/cpu.h>
51#include <linux/platform_data/mmc-s3cmci.h> 50#include <linux/platform_data/mmc-s3cmci.h>
@@ -192,11 +191,16 @@ static struct platform_device *at2440evb_devices[] __initdata = {
192static void __init at2440evb_map_io(void) 191static void __init at2440evb_map_io(void)
193{ 192{
194 s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); 193 s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
195 s3c24xx_init_clocks(16934400);
196 s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs)); 194 s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
197 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 195 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
198} 196}
199 197
198static void __init at2440evb_init_time(void)
199{
200 s3c2440_init_clocks(16934400);
201 samsung_timer_init();
202}
203
200static void __init at2440evb_init(void) 204static void __init at2440evb_init(void)
201{ 205{
202 s3c24xx_fb_set_platdata(&at2440evb_fb_info); 206 s3c24xx_fb_set_platdata(&at2440evb_fb_info);
@@ -213,6 +217,6 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
213 .map_io = at2440evb_map_io, 217 .map_io = at2440evb_map_io,
214 .init_machine = at2440evb_init, 218 .init_machine = at2440evb_init,
215 .init_irq = s3c2440_init_irq, 219 .init_irq = s3c2440_init_irq,
216 .init_time = samsung_timer_init, 220 .init_time = at2440evb_init_time,
217 .restart = s3c244x_restart, 221 .restart = s3c244x_restart,
218MACHINE_END 222MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index e371ff53a408..f9112b801a33 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -51,7 +51,6 @@
51#include <mach/regs-lcd.h> 51#include <mach/regs-lcd.h>
52#include <mach/gpio-samsung.h> 52#include <mach/gpio-samsung.h>
53 53
54#include <plat/clock.h>
55#include <plat/cpu.h> 54#include <plat/cpu.h>
56#include <plat/cpu-freq.h> 55#include <plat/cpu-freq.h>
57#include <plat/devs.h> 56#include <plat/devs.h>
@@ -523,6 +522,7 @@ static struct s3c_hwmon_pdata bast_hwmon_info = {
523// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0 522// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
524 523
525static struct platform_device *bast_devices[] __initdata = { 524static struct platform_device *bast_devices[] __initdata = {
525 &s3c2410_device_dclk,
526 &s3c_device_ohci, 526 &s3c_device_ohci,
527 &s3c_device_lcd, 527 &s3c_device_lcd,
528 &s3c_device_wdt, 528 &s3c_device_wdt,
@@ -537,14 +537,6 @@ static struct platform_device *bast_devices[] __initdata = {
537 &bast_sio, 537 &bast_sio,
538}; 538};
539 539
540static struct clk *bast_clocks[] __initdata = {
541 &s3c24xx_dclk0,
542 &s3c24xx_dclk1,
543 &s3c24xx_clkout0,
544 &s3c24xx_clkout1,
545 &s3c24xx_uclk,
546};
547
548static struct s3c_cpufreq_board __initdata bast_cpufreq = { 540static struct s3c_cpufreq_board __initdata bast_cpufreq = {
549 .refresh = 7800, /* 7.8usec */ 541 .refresh = 7800, /* 7.8usec */
550 .auto_io = 1, 542 .auto_io = 1,
@@ -558,29 +550,19 @@ static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
558 550
559static void __init bast_map_io(void) 551static void __init bast_map_io(void)
560{ 552{
561 /* initialise the clocks */
562
563 s3c24xx_dclk0.parent = &clk_upll;
564 s3c24xx_dclk0.rate = 12*1000*1000;
565
566 s3c24xx_dclk1.parent = &clk_upll;
567 s3c24xx_dclk1.rate = 24*1000*1000;
568
569 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
570 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
571
572 s3c24xx_uclk.parent = &s3c24xx_clkout1;
573
574 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
575
576 s3c_hwmon_set_platdata(&bast_hwmon_info); 553 s3c_hwmon_set_platdata(&bast_hwmon_info);
577 554
578 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); 555 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
579 s3c24xx_init_clocks(0);
580 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); 556 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
581 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 557 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
582} 558}
583 559
560static void __init bast_init_time(void)
561{
562 s3c2410_init_clocks(12000000);
563 samsung_timer_init();
564}
565
584static void __init bast_init(void) 566static void __init bast_init(void)
585{ 567{
586 register_syscore_ops(&bast_pm_syscore_ops); 568 register_syscore_ops(&bast_pm_syscore_ops);
@@ -608,6 +590,6 @@ MACHINE_START(BAST, "Simtec-BAST")
608 .map_io = bast_map_io, 590 .map_io = bast_map_io,
609 .init_irq = s3c2410_init_irq, 591 .init_irq = s3c2410_init_irq,
610 .init_machine = bast_init, 592 .init_machine = bast_init,
611 .init_time = samsung_timer_init, 593 .init_time = bast_init_time,
612 .restart = s3c2410_restart, 594 .restart = s3c2410_restart,
613MACHINE_END 595MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index dc4db849f0fd..fc3a08d0cb3f 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -501,7 +501,6 @@ static struct platform_device gta02_buttons_device = {
501static void __init gta02_map_io(void) 501static void __init gta02_map_io(void)
502{ 502{
503 s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc)); 503 s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
504 s3c24xx_init_clocks(12000000);
505 s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs)); 504 s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
506 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 505 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
507} 506}
@@ -585,6 +584,11 @@ static void __init gta02_machine_init(void)
585 regulator_has_full_constraints(); 584 regulator_has_full_constraints();
586} 585}
587 586
587static void __init gta02_init_time(void)
588{
589 s3c2442_init_clocks(12000000);
590 samsung_timer_init();
591}
588 592
589MACHINE_START(NEO1973_GTA02, "GTA02") 593MACHINE_START(NEO1973_GTA02, "GTA02")
590 /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */ 594 /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
@@ -592,6 +596,6 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
592 .map_io = gta02_map_io, 596 .map_io = gta02_map_io,
593 .init_irq = s3c2442_init_irq, 597 .init_irq = s3c2442_init_irq,
594 .init_machine = gta02_machine_init, 598 .init_machine = gta02_machine_init,
595 .init_time = samsung_timer_init, 599 .init_time = gta02_init_time,
596 .restart = s3c244x_restart, 600 .restart = s3c244x_restart,
597MACHINE_END 601MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index e453acd92cbf..fbf5487ae5d1 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -57,7 +57,6 @@
57#include <mach/regs-lcd.h> 57#include <mach/regs-lcd.h>
58#include <mach/gpio-samsung.h> 58#include <mach/gpio-samsung.h>
59 59
60#include <plat/clock.h>
61#include <plat/cpu.h> 60#include <plat/cpu.h>
62#include <plat/devs.h> 61#include <plat/devs.h>
63#include <plat/gpio-cfg.h> 62#include <plat/gpio-cfg.h>
@@ -646,7 +645,6 @@ static struct platform_device *h1940_devices[] __initdata = {
646static void __init h1940_map_io(void) 645static void __init h1940_map_io(void)
647{ 646{
648 s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc)); 647 s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc));
649 s3c24xx_init_clocks(0);
650 s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs)); 648 s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
651 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 649 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
652 650
@@ -662,6 +660,12 @@ static void __init h1940_map_io(void)
662 WARN_ON(gpiochip_add(&h1940_latch_gpiochip)); 660 WARN_ON(gpiochip_add(&h1940_latch_gpiochip));
663} 661}
664 662
663static void __init h1940_init_time(void)
664{
665 s3c2410_init_clocks(12000000);
666 samsung_timer_init();
667}
668
665/* H1940 and RX3715 need to reserve this for suspend */ 669/* H1940 and RX3715 need to reserve this for suspend */
666static void __init h1940_reserve(void) 670static void __init h1940_reserve(void)
667{ 671{
@@ -739,6 +743,6 @@ MACHINE_START(H1940, "IPAQ-H1940")
739 .reserve = h1940_reserve, 743 .reserve = h1940_reserve,
740 .init_irq = s3c2410_init_irq, 744 .init_irq = s3c2410_init_irq,
741 .init_machine = h1940_init, 745 .init_machine = h1940_init,
742 .init_time = samsung_timer_init, 746 .init_time = h1940_init_time,
743 .restart = s3c2410_restart, 747 .restart = s3c2410_restart,
744MACHINE_END 748MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 5faa7239e7d6..e81ea82c55f9 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -507,11 +507,16 @@ static struct syscore_ops jive_pm_syscore_ops = {
507static void __init jive_map_io(void) 507static void __init jive_map_io(void)
508{ 508{
509 s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc)); 509 s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
510 s3c24xx_init_clocks(12000000);
511 s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs)); 510 s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
512 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 511 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
513} 512}
514 513
514static void __init jive_init_time(void)
515{
516 s3c2412_init_clocks(12000000);
517 samsung_timer_init();
518}
519
515static void jive_power_off(void) 520static void jive_power_off(void)
516{ 521{
517 printk(KERN_INFO "powering system down...\n"); 522 printk(KERN_INFO "powering system down...\n");
@@ -665,6 +670,6 @@ MACHINE_START(JIVE, "JIVE")
665 .init_irq = s3c2412_init_irq, 670 .init_irq = s3c2412_init_irq,
666 .map_io = jive_map_io, 671 .map_io = jive_map_io,
667 .init_machine = jive_machine_init, 672 .init_machine = jive_machine_init,
668 .init_time = samsung_timer_init, 673 .init_time = jive_init_time,
669 .restart = s3c2412_restart, 674 .restart = s3c2412_restart,
670MACHINE_END 675MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 9e57fd9f4f3b..5cc40ec1d254 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -54,7 +54,6 @@
54#include <linux/mtd/partitions.h> 54#include <linux/mtd/partitions.h>
55 55
56#include <plat/gpio-cfg.h> 56#include <plat/gpio-cfg.h>
57#include <plat/clock.h>
58#include <plat/devs.h> 57#include <plat/devs.h>
59#include <plat/cpu.h> 58#include <plat/cpu.h>
60#include <plat/samsung-time.h> 59#include <plat/samsung-time.h>
@@ -525,11 +524,16 @@ static struct platform_device *mini2440_devices[] __initdata = {
525static void __init mini2440_map_io(void) 524static void __init mini2440_map_io(void)
526{ 525{
527 s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc)); 526 s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc));
528 s3c24xx_init_clocks(12000000);
529 s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); 527 s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
530 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 528 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
531} 529}
532 530
531static void __init mini2440_init_time(void)
532{
533 s3c2440_init_clocks(12000000);
534 samsung_timer_init();
535}
536
533/* 537/*
534 * mini2440_features string 538 * mini2440_features string
535 * 539 *
@@ -690,6 +694,6 @@ MACHINE_START(MINI2440, "MINI2440")
690 .map_io = mini2440_map_io, 694 .map_io = mini2440_map_io,
691 .init_machine = mini2440_init, 695 .init_machine = mini2440_init,
692 .init_irq = s3c2440_init_irq, 696 .init_irq = s3c2440_init_irq,
693 .init_time = samsung_timer_init, 697 .init_time = mini2440_init_time,
694 .restart = s3c244x_restart, 698 .restart = s3c244x_restart,
695MACHINE_END 699MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 4cccaad34847..3ac2a54348d6 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -45,7 +45,6 @@
45 45
46#include <linux/platform_data/i2c-s3c2410.h> 46#include <linux/platform_data/i2c-s3c2410.h>
47 47
48#include <plat/clock.h>
49#include <plat/cpu.h> 48#include <plat/cpu.h>
50#include <plat/devs.h> 49#include <plat/devs.h>
51#include <linux/platform_data/mmc-s3cmci.h> 50#include <linux/platform_data/mmc-s3cmci.h>
@@ -535,11 +534,16 @@ static void __init n30_map_io(void)
535{ 534{
536 s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc)); 535 s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc));
537 n30_hwinit(); 536 n30_hwinit();
538 s3c24xx_init_clocks(0);
539 s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs)); 537 s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
540 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 538 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
541} 539}
542 540
541static void __init n30_init_time(void)
542{
543 s3c2410_init_clocks(12000000);
544 samsung_timer_init();
545}
546
543/* GPB3 is the line that controls the pull-up for the USB D+ line */ 547/* GPB3 is the line that controls the pull-up for the USB D+ line */
544 548
545static void __init n30_init(void) 549static void __init n30_init(void)
@@ -591,7 +595,7 @@ MACHINE_START(N30, "Acer-N30")
591 Ben Dooks <ben-linux@fluff.org> 595 Ben Dooks <ben-linux@fluff.org>
592 */ 596 */
593 .atag_offset = 0x100, 597 .atag_offset = 0x100,
594 .init_time = samsung_timer_init, 598 .init_time = n30_init_time,
595 .init_machine = n30_init, 599 .init_machine = n30_init,
596 .init_irq = s3c2410_init_irq, 600 .init_irq = s3c2410_init_irq,
597 .map_io = n30_map_io, 601 .map_io = n30_map_io,
@@ -602,7 +606,7 @@ MACHINE_START(N35, "Acer-N35")
602 /* Maintainer: Christer Weinigel <christer@weinigel.se> 606 /* Maintainer: Christer Weinigel <christer@weinigel.se>
603 */ 607 */
604 .atag_offset = 0x100, 608 .atag_offset = 0x100,
605 .init_time = samsung_timer_init, 609 .init_time = n30_init_time,
606 .init_machine = n30_init, 610 .init_machine = n30_init,
607 .init_irq = s3c2410_init_irq, 611 .init_irq = s3c2410_init_irq,
608 .map_io = n30_map_io, 612 .map_io = n30_map_io,
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 3066851f584d..c82c281ce351 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -42,7 +42,6 @@
42#include <linux/platform_data/i2c-s3c2410.h> 42#include <linux/platform_data/i2c-s3c2410.h>
43 43
44#include <plat/gpio-cfg.h> 44#include <plat/gpio-cfg.h>
45#include <plat/clock.h>
46#include <plat/devs.h> 45#include <plat/devs.h>
47#include <plat/cpu.h> 46#include <plat/cpu.h>
48#include <plat/samsung-time.h> 47#include <plat/samsung-time.h>
@@ -135,13 +134,18 @@ static void __init nexcoder_sensorboard_init(void)
135static void __init nexcoder_map_io(void) 134static void __init nexcoder_map_io(void)
136{ 135{
137 s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc)); 136 s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
138 s3c24xx_init_clocks(0);
139 s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs)); 137 s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
140 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 138 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
141 139
142 nexcoder_sensorboard_init(); 140 nexcoder_sensorboard_init();
143} 141}
144 142
143static void __init nexcoder_init_time(void)
144{
145 s3c2440_init_clocks(12000000);
146 samsung_timer_init();
147}
148
145static void __init nexcoder_init(void) 149static void __init nexcoder_init(void)
146{ 150{
147 s3c_i2c0_set_platdata(NULL); 151 s3c_i2c0_set_platdata(NULL);
@@ -154,6 +158,6 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
154 .map_io = nexcoder_map_io, 158 .map_io = nexcoder_map_io,
155 .init_machine = nexcoder_init, 159 .init_machine = nexcoder_init,
156 .init_irq = s3c2440_init_irq, 160 .init_irq = s3c2440_init_irq,
157 .init_time = samsung_timer_init, 161 .init_time = nexcoder_init_time,
158 .restart = s3c244x_restart, 162 .restart = s3c244x_restart,
159MACHINE_END 163MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index a4ae4bb3666d..189147b80eca 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -40,7 +40,6 @@
40#include <linux/mtd/nand_ecc.h> 40#include <linux/mtd/nand_ecc.h>
41#include <linux/mtd/partitions.h> 41#include <linux/mtd/partitions.h>
42 42
43#include <plat/clock.h>
44#include <plat/cpu.h> 43#include <plat/cpu.h>
45#include <plat/cpu-freq.h> 44#include <plat/cpu-freq.h>
46#include <plat/devs.h> 45#include <plat/devs.h>
@@ -344,20 +343,13 @@ static struct i2c_board_info osiris_i2c_devs[] __initdata = {
344/* Standard Osiris devices */ 343/* Standard Osiris devices */
345 344
346static struct platform_device *osiris_devices[] __initdata = { 345static struct platform_device *osiris_devices[] __initdata = {
346 &s3c2410_device_dclk,
347 &s3c_device_i2c0, 347 &s3c_device_i2c0,
348 &s3c_device_wdt, 348 &s3c_device_wdt,
349 &s3c_device_nand, 349 &s3c_device_nand,
350 &osiris_pcmcia, 350 &osiris_pcmcia,
351}; 351};
352 352
353static struct clk *osiris_clocks[] __initdata = {
354 &s3c24xx_dclk0,
355 &s3c24xx_dclk1,
356 &s3c24xx_clkout0,
357 &s3c24xx_clkout1,
358 &s3c24xx_uclk,
359};
360
361static struct s3c_cpufreq_board __initdata osiris_cpufreq = { 353static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
362 .refresh = 7800, /* refresh period is 7.8usec */ 354 .refresh = 7800, /* refresh period is 7.8usec */
363 .auto_io = 1, 355 .auto_io = 1,
@@ -368,23 +360,7 @@ static void __init osiris_map_io(void)
368{ 360{
369 unsigned long flags; 361 unsigned long flags;
370 362
371 /* initialise the clocks */
372
373 s3c24xx_dclk0.parent = &clk_upll;
374 s3c24xx_dclk0.rate = 12*1000*1000;
375
376 s3c24xx_dclk1.parent = &clk_upll;
377 s3c24xx_dclk1.rate = 24*1000*1000;
378
379 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
380 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
381
382 s3c24xx_uclk.parent = &s3c24xx_clkout1;
383
384 s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
385
386 s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc)); 363 s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
387 s3c24xx_init_clocks(0);
388 s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs)); 364 s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
389 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 365 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
390 366
@@ -408,6 +384,12 @@ static void __init osiris_map_io(void)
408 local_irq_restore(flags); 384 local_irq_restore(flags);
409} 385}
410 386
387static void __init osiris_init_time(void)
388{
389 s3c2440_init_clocks(12000000);
390 samsung_timer_init();
391}
392
411static void __init osiris_init(void) 393static void __init osiris_init(void)
412{ 394{
413 register_syscore_ops(&osiris_pm_syscore_ops); 395 register_syscore_ops(&osiris_pm_syscore_ops);
@@ -429,6 +411,6 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
429 .map_io = osiris_map_io, 411 .map_io = osiris_map_io,
430 .init_irq = s3c2440_init_irq, 412 .init_irq = s3c2440_init_irq,
431 .init_machine = osiris_init, 413 .init_machine = osiris_init,
432 .init_time = samsung_timer_init, 414 .init_time = osiris_init_time,
433 .restart = s3c244x_restart, 415 .restart = s3c244x_restart,
434MACHINE_END 416MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index bdb3faac2d9b..45833001186d 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -30,7 +30,6 @@
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31#include <mach/regs-gpio.h> 31#include <mach/regs-gpio.h>
32 32
33#include <plat/clock.h>
34#include <plat/cpu.h> 33#include <plat/cpu.h>
35#include <plat/devs.h> 34#include <plat/devs.h>
36#include <plat/samsung-time.h> 35#include <plat/samsung-time.h>
@@ -100,11 +99,16 @@ static struct platform_device *otom11_devices[] __initdata = {
100static void __init otom11_map_io(void) 99static void __init otom11_map_io(void)
101{ 100{
102 s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc)); 101 s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
103 s3c24xx_init_clocks(0);
104 s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs)); 102 s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
105 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 103 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
106} 104}
107 105
106static void __init otom11_init_time(void)
107{
108 s3c2410_init_clocks(12000000);
109 samsung_timer_init();
110}
111
108static void __init otom11_init(void) 112static void __init otom11_init(void)
109{ 113{
110 s3c_i2c0_set_platdata(NULL); 114 s3c_i2c0_set_platdata(NULL);
@@ -117,6 +121,6 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
117 .map_io = otom11_map_io, 121 .map_io = otom11_map_io,
118 .init_machine = otom11_init, 122 .init_machine = otom11_init,
119 .init_irq = s3c2410_init_irq, 123 .init_irq = s3c2410_init_irq,
120 .init_time = samsung_timer_init, 124 .init_time = otom11_init_time,
121 .restart = s3c2410_restart, 125 .restart = s3c2410_restart,
122MACHINE_END 126MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 8c12787a8fd3..228c9094519d 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -304,11 +304,16 @@ __setup("tft=", qt2410_tft_setup);
304static void __init qt2410_map_io(void) 304static void __init qt2410_map_io(void)
305{ 305{
306 s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc)); 306 s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
307 s3c24xx_init_clocks(12*1000*1000);
308 s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); 307 s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
309 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 308 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
310} 309}
311 310
311static void __init qt2410_init_time(void)
312{
313 s3c2410_init_clocks(12000000);
314 samsung_timer_init();
315}
316
312static void __init qt2410_machine_init(void) 317static void __init qt2410_machine_init(void)
313{ 318{
314 s3c_nand_set_platdata(&qt2410_nand_info); 319 s3c_nand_set_platdata(&qt2410_nand_info);
@@ -346,6 +351,6 @@ MACHINE_START(QT2410, "QT2410")
346 .map_io = qt2410_map_io, 351 .map_io = qt2410_map_io,
347 .init_irq = s3c2410_init_irq, 352 .init_irq = s3c2410_init_irq,
348 .init_machine = qt2410_machine_init, 353 .init_machine = qt2410_machine_init,
349 .init_time = samsung_timer_init, 354 .init_time = qt2410_init_time,
350 .restart = s3c2410_restart, 355 .restart = s3c2410_restart,
351MACHINE_END 356MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index afb784e934c8..e2c6541909c1 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -54,7 +54,6 @@
54#include <mach/regs-lcd.h> 54#include <mach/regs-lcd.h>
55#include <mach/gpio-samsung.h> 55#include <mach/gpio-samsung.h>
56 56
57#include <plat/clock.h>
58#include <plat/cpu.h> 57#include <plat/cpu.h>
59#include <plat/devs.h> 58#include <plat/devs.h>
60#include <plat/pm.h> 59#include <plat/pm.h>
@@ -710,6 +709,7 @@ static struct i2c_board_info rx1950_i2c_devices[] = {
710}; 709};
711 710
712static struct platform_device *rx1950_devices[] __initdata = { 711static struct platform_device *rx1950_devices[] __initdata = {
712 &s3c2410_device_dclk,
713 &s3c_device_lcd, 713 &s3c_device_lcd,
714 &s3c_device_wdt, 714 &s3c_device_wdt,
715 &s3c_device_i2c0, 715 &s3c_device_i2c0,
@@ -728,20 +728,9 @@ static struct platform_device *rx1950_devices[] __initdata = {
728 &rx1950_leds, 728 &rx1950_leds,
729}; 729};
730 730
731static struct clk *rx1950_clocks[] __initdata = {
732 &s3c24xx_clkout0,
733 &s3c24xx_clkout1,
734};
735
736static void __init rx1950_map_io(void) 731static void __init rx1950_map_io(void)
737{ 732{
738 s3c24xx_clkout0.parent = &clk_h;
739 s3c24xx_clkout1.parent = &clk_f;
740
741 s3c24xx_register_clocks(rx1950_clocks, ARRAY_SIZE(rx1950_clocks));
742
743 s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc)); 733 s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
744 s3c24xx_init_clocks(16934000);
745 s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs)); 734 s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
746 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 735 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
747 736
@@ -754,6 +743,12 @@ static void __init rx1950_map_io(void)
754 s3c_pm_init(); 743 s3c_pm_init();
755} 744}
756 745
746static void __init rx1950_init_time(void)
747{
748 s3c2442_init_clocks(16934000);
749 samsung_timer_init();
750}
751
757static void __init rx1950_init_machine(void) 752static void __init rx1950_init_machine(void)
758{ 753{
759 int i; 754 int i;
@@ -816,6 +811,6 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
816 .reserve = rx1950_reserve, 811 .reserve = rx1950_reserve,
817 .init_irq = s3c2442_init_irq, 812 .init_irq = s3c2442_init_irq,
818 .init_machine = rx1950_init_machine, 813 .init_machine = rx1950_init_machine,
819 .init_time = samsung_timer_init, 814 .init_time = rx1950_init_time,
820 .restart = s3c244x_restart, 815 .restart = s3c244x_restart,
821MACHINE_END 816MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index e6535ce1bc5c..6e749ec3a2ea 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -46,7 +46,6 @@
46#include <mach/regs-lcd.h> 46#include <mach/regs-lcd.h>
47#include <mach/gpio-samsung.h> 47#include <mach/gpio-samsung.h>
48 48
49#include <plat/clock.h>
50#include <plat/cpu.h> 49#include <plat/cpu.h>
51#include <plat/devs.h> 50#include <plat/devs.h>
52#include <plat/pm.h> 51#include <plat/pm.h>
@@ -179,11 +178,16 @@ static struct platform_device *rx3715_devices[] __initdata = {
179static void __init rx3715_map_io(void) 178static void __init rx3715_map_io(void)
180{ 179{
181 s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); 180 s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
182 s3c24xx_init_clocks(16934000);
183 s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); 181 s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
184 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 182 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
185} 183}
186 184
185static void __init rx3715_init_time(void)
186{
187 s3c2440_init_clocks(16934000);
188 samsung_timer_init();
189}
190
187/* H1940 and RX3715 need to reserve this for suspend */ 191/* H1940 and RX3715 need to reserve this for suspend */
188static void __init rx3715_reserve(void) 192static void __init rx3715_reserve(void)
189{ 193{
@@ -210,6 +214,6 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
210 .reserve = rx3715_reserve, 214 .reserve = rx3715_reserve,
211 .init_irq = s3c2440_init_irq, 215 .init_irq = s3c2440_init_irq,
212 .init_machine = rx3715_init_machine, 216 .init_machine = rx3715_init_machine,
213 .init_time = samsung_timer_init, 217 .init_time = rx3715_init_time,
214 .restart = s3c244x_restart, 218 .restart = s3c244x_restart,
215MACHINE_END 219MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
index 70f0900d4bca..e4dcb9aa2ca2 100644
--- a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
+++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
@@ -18,7 +18,6 @@
18#include <linux/clocksource.h> 18#include <linux/clocksource.h>
19#include <linux/irqchip.h> 19#include <linux/irqchip.h>
20#include <linux/of_platform.h> 20#include <linux/of_platform.h>
21#include <linux/serial_core.h>
22#include <linux/serial_s3c.h> 21#include <linux/serial_s3c.h>
23 22
24#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
@@ -29,48 +28,14 @@
29 28
30#include "common.h" 29#include "common.h"
31 30
32/*
33 * The following lookup table is used to override device names when devices
34 * are registered from device tree. This is temporarily added to enable
35 * device tree support addition for the S3C2416 architecture.
36 *
37 * For drivers that require platform data to be provided from the machine
38 * file, a platform data pointer can also be supplied along with the
39 * devices names. Usually, the platform data elements that cannot be parsed
40 * from the device tree by the drivers (example: function pointers) are
41 * supplied. But it should be noted that this is a temporary mechanism and
42 * at some point, the drivers should be capable of parsing all the platform
43 * data from the device tree.
44 */
45static const struct of_dev_auxdata s3c2416_auxdata_lookup[] __initconst = {
46 OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART,
47 "s3c2440-uart.0", NULL),
48 OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x4000,
49 "s3c2440-uart.1", NULL),
50 OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x8000,
51 "s3c2440-uart.2", NULL),
52 OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0xC000,
53 "s3c2440-uart.3", NULL),
54 OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC0,
55 "s3c-sdhci.0", NULL),
56 OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC1,
57 "s3c-sdhci.1", NULL),
58 OF_DEV_AUXDATA("samsung,s3c2440-i2c", S3C_PA_IIC,
59 "s3c2440-i2c.0", NULL),
60 {},
61};
62
63static void __init s3c2416_dt_map_io(void) 31static void __init s3c2416_dt_map_io(void)
64{ 32{
65 s3c24xx_init_io(NULL, 0); 33 s3c24xx_init_io(NULL, 0);
66 s3c24xx_init_clocks(12000000);
67} 34}
68 35
69static void __init s3c2416_dt_machine_init(void) 36static void __init s3c2416_dt_machine_init(void)
70{ 37{
71 of_platform_populate(NULL, of_default_bus_match_table, 38 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
72 s3c2416_auxdata_lookup, NULL);
73
74 s3c_pm_init(); 39 s3c_pm_init();
75} 40}
76 41
@@ -86,6 +51,5 @@ DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)")
86 .map_io = s3c2416_dt_map_io, 51 .map_io = s3c2416_dt_map_io,
87 .init_irq = irqchip_init, 52 .init_irq = irqchip_init,
88 .init_machine = s3c2416_dt_machine_init, 53 .init_machine = s3c2416_dt_machine_init,
89 .init_time = clocksource_of_init,
90 .restart = s3c2416_restart, 54 .restart = s3c2416_restart,
91MACHINE_END 55MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index f32924ee0e9f..419fadd6e446 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -99,11 +99,16 @@ static struct platform_device *smdk2410_devices[] __initdata = {
99static void __init smdk2410_map_io(void) 99static void __init smdk2410_map_io(void)
100{ 100{
101 s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc)); 101 s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
102 s3c24xx_init_clocks(0);
103 s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); 102 s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
104 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 103 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
105} 104}
106 105
106static void __init smdk2410_init_time(void)
107{
108 s3c2410_init_clocks(12000000);
109 samsung_timer_init();
110}
111
107static void __init smdk2410_init(void) 112static void __init smdk2410_init(void)
108{ 113{
109 s3c_i2c0_set_platdata(NULL); 114 s3c_i2c0_set_platdata(NULL);
@@ -118,6 +123,6 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
118 .map_io = smdk2410_map_io, 123 .map_io = smdk2410_map_io,
119 .init_irq = s3c2410_init_irq, 124 .init_irq = s3c2410_init_irq,
120 .init_machine = smdk2410_init, 125 .init_machine = smdk2410_init,
121 .init_time = samsung_timer_init, 126 .init_time = smdk2410_init_time,
122 .restart = s3c2410_restart, 127 .restart = s3c2410_restart,
123MACHINE_END 128MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 233fe52d2015..a38f8a049e22 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -106,11 +106,16 @@ static void __init smdk2413_fixup(struct tag *tags, char **cmdline,
106static void __init smdk2413_map_io(void) 106static void __init smdk2413_map_io(void)
107{ 107{
108 s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc)); 108 s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
109 s3c24xx_init_clocks(12000000);
110 s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs)); 109 s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
111 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 110 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
112} 111}
113 112
113static void __init smdk2413_init_time(void)
114{
115 s3c2412_init_clocks(12000000);
116 samsung_timer_init();
117}
118
114static void __init smdk2413_machine_init(void) 119static void __init smdk2413_machine_init(void)
115{ /* Turn off suspend on both USB ports, and switch the 120{ /* Turn off suspend on both USB ports, and switch the
116 * selectable USB port to USB device mode. */ 121 * selectable USB port to USB device mode. */
@@ -159,6 +164,6 @@ MACHINE_START(SMDK2413, "SMDK2413")
159 .init_irq = s3c2412_init_irq, 164 .init_irq = s3c2412_init_irq,
160 .map_io = smdk2413_map_io, 165 .map_io = smdk2413_map_io,
161 .init_machine = smdk2413_machine_init, 166 .init_machine = smdk2413_machine_init,
162 .init_time = samsung_timer_init, 167 .init_time = smdk2413_init_time,
163 .restart = s3c2412_restart, 168 .restart = s3c2412_restart,
164MACHINE_END 169MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index b3b54d8e1410..fa6f30d23601 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -219,10 +219,15 @@ static struct platform_device *smdk2416_devices[] __initdata = {
219 &s3c2443_device_dma, 219 &s3c2443_device_dma,
220}; 220};
221 221
222static void __init smdk2416_init_time(void)
223{
224 s3c2416_init_clocks(12000000);
225 samsung_timer_init();
226}
227
222static void __init smdk2416_map_io(void) 228static void __init smdk2416_map_io(void)
223{ 229{
224 s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc)); 230 s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
225 s3c24xx_init_clocks(12000000);
226 s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs)); 231 s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
227 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 232 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
228} 233}
@@ -257,6 +262,6 @@ MACHINE_START(SMDK2416, "SMDK2416")
257 .init_irq = s3c2416_init_irq, 262 .init_irq = s3c2416_init_irq,
258 .map_io = smdk2416_map_io, 263 .map_io = smdk2416_map_io,
259 .init_machine = smdk2416_machine_init, 264 .init_machine = smdk2416_machine_init,
260 .init_time = samsung_timer_init, 265 .init_time = smdk2416_init_time,
261 .restart = s3c2416_restart, 266 .restart = s3c2416_restart,
262MACHINE_END 267MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index d071dcfea548..5fb89c0ae17a 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -38,7 +38,6 @@
38#include <mach/fb.h> 38#include <mach/fb.h>
39#include <linux/platform_data/i2c-s3c2410.h> 39#include <linux/platform_data/i2c-s3c2410.h>
40 40
41#include <plat/clock.h>
42#include <plat/devs.h> 41#include <plat/devs.h>
43#include <plat/cpu.h> 42#include <plat/cpu.h>
44#include <plat/samsung-time.h> 43#include <plat/samsung-time.h>
@@ -159,11 +158,16 @@ static struct platform_device *smdk2440_devices[] __initdata = {
159static void __init smdk2440_map_io(void) 158static void __init smdk2440_map_io(void)
160{ 159{
161 s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc)); 160 s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
162 s3c24xx_init_clocks(16934400);
163 s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs)); 161 s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
164 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 162 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
165} 163}
166 164
165static void __init smdk2440_init_time(void)
166{
167 s3c2440_init_clocks(16934400);
168 samsung_timer_init();
169}
170
167static void __init smdk2440_machine_init(void) 171static void __init smdk2440_machine_init(void)
168{ 172{
169 s3c24xx_fb_set_platdata(&smdk2440_fb_info); 173 s3c24xx_fb_set_platdata(&smdk2440_fb_info);
@@ -180,6 +184,6 @@ MACHINE_START(S3C2440, "SMDK2440")
180 .init_irq = s3c2440_init_irq, 184 .init_irq = s3c2440_init_irq,
181 .map_io = smdk2440_map_io, 185 .map_io = smdk2440_map_io,
182 .init_machine = smdk2440_machine_init, 186 .init_machine = smdk2440_machine_init,
183 .init_time = samsung_timer_init, 187 .init_time = smdk2440_init_time,
184 .restart = s3c244x_restart, 188 .restart = s3c244x_restart,
185MACHINE_END 189MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index 06c4d77de3a5..ef5d5ea33182 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -121,11 +121,16 @@ static struct platform_device *smdk2443_devices[] __initdata = {
121static void __init smdk2443_map_io(void) 121static void __init smdk2443_map_io(void)
122{ 122{
123 s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc)); 123 s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
124 s3c24xx_init_clocks(12000000);
125 s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs)); 124 s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
126 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 125 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
127} 126}
128 127
128static void __init smdk2443_init_time(void)
129{
130 s3c2443_init_clocks(12000000);
131 samsung_timer_init();
132}
133
129static void __init smdk2443_machine_init(void) 134static void __init smdk2443_machine_init(void)
130{ 135{
131 s3c_i2c0_set_platdata(NULL); 136 s3c_i2c0_set_platdata(NULL);
@@ -145,6 +150,6 @@ MACHINE_START(SMDK2443, "SMDK2443")
145 .init_irq = s3c2443_init_irq, 150 .init_irq = s3c2443_init_irq,
146 .map_io = smdk2443_map_io, 151 .map_io = smdk2443_map_io,
147 .init_machine = smdk2443_machine_init, 152 .init_machine = smdk2443_machine_init,
148 .init_time = samsung_timer_init, 153 .init_time = smdk2443_init_time,
149 .restart = s3c2443_restart, 154 .restart = s3c2443_restart,
150MACHINE_END 155MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 4108b2f0cede..c616ca2d409e 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -135,11 +135,16 @@ static struct platform_device *tct_hammer_devices[] __initdata = {
135static void __init tct_hammer_map_io(void) 135static void __init tct_hammer_map_io(void)
136{ 136{
137 s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc)); 137 s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc));
138 s3c24xx_init_clocks(0);
139 s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs)); 138 s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs));
140 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 139 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
141} 140}
142 141
142static void __init tct_hammer_init_time(void)
143{
144 s3c2410_init_clocks(12000000);
145 samsung_timer_init();
146}
147
143static void __init tct_hammer_init(void) 148static void __init tct_hammer_init(void)
144{ 149{
145 s3c_i2c0_set_platdata(NULL); 150 s3c_i2c0_set_platdata(NULL);
@@ -151,6 +156,6 @@ MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
151 .map_io = tct_hammer_map_io, 156 .map_io = tct_hammer_map_io,
152 .init_irq = s3c2410_init_irq, 157 .init_irq = s3c2410_init_irq,
153 .init_machine = tct_hammer_init, 158 .init_machine = tct_hammer_init,
154 .init_time = samsung_timer_init, 159 .init_time = tct_hammer_init_time,
155 .restart = s3c2410_restart, 160 .restart = s3c2410_restart,
156MACHINE_END 161MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index 1cc5b1bd51cd..f88c584c3001 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -43,7 +43,6 @@
43#include <mach/regs-gpio.h> 43#include <mach/regs-gpio.h>
44#include <mach/gpio-samsung.h> 44#include <mach/gpio-samsung.h>
45 45
46#include <plat/clock.h>
47#include <plat/cpu.h> 46#include <plat/cpu.h>
48#include <plat/devs.h> 47#include <plat/devs.h>
49#include <plat/samsung-time.h> 48#include <plat/samsung-time.h>
@@ -286,6 +285,7 @@ static struct i2c_board_info vr1000_i2c_devs[] __initdata = {
286/* devices for this board */ 285/* devices for this board */
287 286
288static struct platform_device *vr1000_devices[] __initdata = { 287static struct platform_device *vr1000_devices[] __initdata = {
288 &s3c2410_device_dclk,
289 &s3c_device_ohci, 289 &s3c_device_ohci,
290 &s3c_device_lcd, 290 &s3c_device_lcd,
291 &s3c_device_wdt, 291 &s3c_device_wdt,
@@ -299,14 +299,6 @@ static struct platform_device *vr1000_devices[] __initdata = {
299 &vr1000_led3, 299 &vr1000_led3,
300}; 300};
301 301
302static struct clk *vr1000_clocks[] __initdata = {
303 &s3c24xx_dclk0,
304 &s3c24xx_dclk1,
305 &s3c24xx_clkout0,
306 &s3c24xx_clkout1,
307 &s3c24xx_uclk,
308};
309
310static void vr1000_power_off(void) 302static void vr1000_power_off(void)
311{ 303{
312 gpio_direction_output(S3C2410_GPB(9), 1); 304 gpio_direction_output(S3C2410_GPB(9), 1);
@@ -314,29 +306,19 @@ static void vr1000_power_off(void)
314 306
315static void __init vr1000_map_io(void) 307static void __init vr1000_map_io(void)
316{ 308{
317 /* initialise clock sources */
318
319 s3c24xx_dclk0.parent = &clk_upll;
320 s3c24xx_dclk0.rate = 12*1000*1000;
321
322 s3c24xx_dclk1.parent = NULL;
323 s3c24xx_dclk1.rate = 3692307;
324
325 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
326 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
327
328 s3c24xx_uclk.parent = &s3c24xx_clkout1;
329
330 s3c24xx_register_clocks(vr1000_clocks, ARRAY_SIZE(vr1000_clocks));
331
332 pm_power_off = vr1000_power_off; 309 pm_power_off = vr1000_power_off;
333 310
334 s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc)); 311 s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
335 s3c24xx_init_clocks(0);
336 s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs)); 312 s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
337 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 313 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
338} 314}
339 315
316static void __init vr1000_init_time(void)
317{
318 s3c2410_init_clocks(12000000);
319 samsung_timer_init();
320}
321
340static void __init vr1000_init(void) 322static void __init vr1000_init(void)
341{ 323{
342 s3c_i2c0_set_platdata(NULL); 324 s3c_i2c0_set_platdata(NULL);
@@ -357,6 +339,6 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
357 .map_io = vr1000_map_io, 339 .map_io = vr1000_map_io,
358 .init_machine = vr1000_init, 340 .init_machine = vr1000_init,
359 .init_irq = s3c2410_init_irq, 341 .init_irq = s3c2410_init_irq,
360 .init_time = samsung_timer_init, 342 .init_time = vr1000_init_time,
361 .restart = s3c2410_restart, 343 .restart = s3c2410_restart,
362MACHINE_END 344MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 40868c0e0a68..6b706c915387 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -142,11 +142,16 @@ static void __init vstms_fixup(struct tag *tags, char **cmdline,
142static void __init vstms_map_io(void) 142static void __init vstms_map_io(void)
143{ 143{
144 s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc)); 144 s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
145 s3c24xx_init_clocks(12000000);
146 s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs)); 145 s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
147 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); 146 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
148} 147}
149 148
149static void __init vstms_init_time(void)
150{
151 s3c2412_init_clocks(12000000);
152 samsung_timer_init();
153}
154
150static void __init vstms_init(void) 155static void __init vstms_init(void)
151{ 156{
152 s3c_i2c0_set_platdata(NULL); 157 s3c_i2c0_set_platdata(NULL);
@@ -162,6 +167,6 @@ MACHINE_START(VSTMS, "VSTMS")
162 .init_irq = s3c2412_init_irq, 167 .init_irq = s3c2412_init_irq,
163 .init_machine = vstms_init, 168 .init_machine = vstms_init,
164 .map_io = vstms_map_io, 169 .map_io = vstms_map_io,
165 .init_time = samsung_timer_init, 170 .init_time = vstms_init_time,
166 .restart = s3c2412_restart, 171 .restart = s3c2412_restart,
167MACHINE_END 172MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c
index 68ea5b7e5dc7..b19256ec8d40 100644
--- a/arch/arm/mach-s3c24xx/pm.c
+++ b/arch/arm/mach-s3c24xx/pm.c
@@ -51,9 +51,6 @@
51#define PFX "s3c24xx-pm: " 51#define PFX "s3c24xx-pm: "
52 52
53static struct sleep_save core_save[] = { 53static struct sleep_save core_save[] = {
54 SAVE_ITEM(S3C2410_LOCKTIME),
55 SAVE_ITEM(S3C2410_CLKCON),
56
57 /* we restore the timings here, with the proviso that the board 54 /* we restore the timings here, with the proviso that the board
58 * brings the system up in an slower, or equal frequency setting 55 * brings the system up in an slower, or equal frequency setting
59 * to the original system. 56 * to the original system.
@@ -69,18 +66,6 @@ static struct sleep_save core_save[] = {
69 SAVE_ITEM(S3C2410_BANKCON3), 66 SAVE_ITEM(S3C2410_BANKCON3),
70 SAVE_ITEM(S3C2410_BANKCON4), 67 SAVE_ITEM(S3C2410_BANKCON4),
71 SAVE_ITEM(S3C2410_BANKCON5), 68 SAVE_ITEM(S3C2410_BANKCON5),
72
73#ifndef CONFIG_CPU_FREQ
74 SAVE_ITEM(S3C2410_CLKDIVN),
75 SAVE_ITEM(S3C2410_MPLLCON),
76 SAVE_ITEM(S3C2410_REFRESH),
77#endif
78 SAVE_ITEM(S3C2410_UPLLCON),
79 SAVE_ITEM(S3C2410_CLKSLOW),
80};
81
82static struct sleep_save misc_save[] = {
83 SAVE_ITEM(S3C2410_DCLKCON),
84}; 69};
85 70
86/* s3c_pm_check_resume_pin 71/* s3c_pm_check_resume_pin
@@ -140,12 +125,10 @@ void s3c_pm_configure_extint(void)
140void s3c_pm_restore_core(void) 125void s3c_pm_restore_core(void)
141{ 126{
142 s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); 127 s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
143 s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
144} 128}
145 129
146void s3c_pm_save_core(void) 130void s3c_pm_save_core(void)
147{ 131{
148 s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
149 s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); 132 s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
150} 133}
151 134
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 04b58cb49888..7eab88829883 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -85,62 +85,6 @@ void __init s3c2410_map_io(void)
85 85
86void __init_or_cpufreq s3c2410_setup_clocks(void) 86void __init_or_cpufreq s3c2410_setup_clocks(void)
87{ 87{
88 struct clk *xtal_clk;
89 unsigned long tmp;
90 unsigned long xtal;
91 unsigned long fclk;
92 unsigned long hclk;
93 unsigned long pclk;
94
95 xtal_clk = clk_get(NULL, "xtal");
96 xtal = clk_get_rate(xtal_clk);
97 clk_put(xtal_clk);
98
99 /* now we've got our machine bits initialised, work out what
100 * clocks we've got */
101
102 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
103
104 tmp = __raw_readl(S3C2410_CLKDIVN);
105
106 /* work out clock scalings */
107
108 hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
109 pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
110
111 /* print brieft summary of clocks, etc */
112
113 printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
114 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
115
116 /* initialise the clocks here, to allow other things like the
117 * console to use them
118 */
119
120 s3c24xx_setup_clocks(fclk, hclk, pclk);
121}
122
123/* fake ARMCLK for use with cpufreq, etc. */
124
125static struct clk s3c2410_armclk = {
126 .name = "armclk",
127 .parent = &clk_f,
128 .id = -1,
129};
130
131static struct clk_lookup s3c2410_clk_lookup[] = {
132 CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
133 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
134};
135
136void __init s3c2410_init_clocks(int xtal)
137{
138 s3c24xx_register_baseclocks(xtal);
139 s3c2410_setup_clocks();
140 s3c2410_baseclk_add();
141 s3c24xx_register_clock(&s3c2410_armclk);
142 clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
143 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
144} 88}
145 89
146struct bus_type s3c2410_subsys = { 90struct bus_type s3c2410_subsys = {
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 657cbaca80ac..d49f52fbc842 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -173,49 +173,6 @@ void __init s3c2412_map_io(void)
173 173
174void __init_or_cpufreq s3c2412_setup_clocks(void) 174void __init_or_cpufreq s3c2412_setup_clocks(void)
175{ 175{
176 struct clk *xtal_clk;
177 unsigned long tmp;
178 unsigned long xtal;
179 unsigned long fclk;
180 unsigned long hclk;
181 unsigned long pclk;
182
183 xtal_clk = clk_get(NULL, "xtal");
184 xtal = clk_get_rate(xtal_clk);
185 clk_put(xtal_clk);
186
187 /* now we've got our machine bits initialised, work out what
188 * clocks we've got */
189
190 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
191
192 clk_mpll.rate = fclk;
193
194 tmp = __raw_readl(S3C2410_CLKDIVN);
195
196 /* work out clock scalings */
197
198 hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
199 hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
200 pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
201
202 /* print brieft summary of clocks, etc */
203
204 printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
205 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
206
207 s3c24xx_setup_clocks(fclk, hclk, pclk);
208}
209
210void __init s3c2412_init_clocks(int xtal)
211{
212 /* initialise the clocks here, to allow other things like the
213 * console to use them
214 */
215
216 s3c24xx_register_baseclocks(xtal);
217 s3c2412_setup_clocks();
218 s3c2412_baseclk_add();
219} 176}
220 177
221/* need to register the subsystem before we actually register the device, and 178/* need to register the subsystem before we actually register the device, and
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index 2c8adc028538..fb9da2b603a2 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -53,117 +53,6 @@
53 53
54#include "common.h" 54#include "common.h"
55 55
56/* S3C2442 extended clock support */
57
58static unsigned long s3c2442_camif_upll_round(struct clk *clk,
59 unsigned long rate)
60{
61 unsigned long parent_rate = clk_get_rate(clk->parent);
62 int div;
63
64 if (rate > parent_rate)
65 return parent_rate;
66
67 div = parent_rate / rate;
68
69 if (div == 3)
70 return parent_rate / 3;
71
72 /* note, we remove the +/- 1 calculations for the divisor */
73
74 div /= 2;
75
76 if (div < 1)
77 div = 1;
78 else if (div > 16)
79 div = 16;
80
81 return parent_rate / (div * 2);
82}
83
84static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
85{
86 unsigned long parent_rate = clk_get_rate(clk->parent);
87 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
88
89 rate = s3c2442_camif_upll_round(clk, rate);
90
91 camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
92
93 if (rate == parent_rate) {
94 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
95 } else if ((parent_rate / rate) == 3) {
96 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
97 camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
98 } else {
99 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
100 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
101 camdivn |= (((parent_rate / rate) / 2) - 1);
102 }
103
104 __raw_writel(camdivn, S3C2440_CAMDIVN);
105
106 return 0;
107}
108
109/* Extra S3C2442 clocks */
110
111static struct clk s3c2442_clk_cam = {
112 .name = "camif",
113 .id = -1,
114 .enable = s3c2410_clkcon_enable,
115 .ctrlbit = S3C2440_CLKCON_CAMERA,
116};
117
118static struct clk s3c2442_clk_cam_upll = {
119 .name = "camif-upll",
120 .id = -1,
121 .ops = &(struct clk_ops) {
122 .set_rate = s3c2442_camif_upll_setrate,
123 .round_rate = s3c2442_camif_upll_round,
124 },
125};
126
127static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif)
128{
129 struct clk *clock_upll;
130 struct clk *clock_h;
131 struct clk *clock_p;
132
133 clock_p = clk_get(NULL, "pclk");
134 clock_h = clk_get(NULL, "hclk");
135 clock_upll = clk_get(NULL, "upll");
136
137 if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
138 printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
139 return -EINVAL;
140 }
141
142 s3c2442_clk_cam.parent = clock_h;
143 s3c2442_clk_cam_upll.parent = clock_upll;
144
145 s3c24xx_register_clock(&s3c2442_clk_cam);
146 s3c24xx_register_clock(&s3c2442_clk_cam_upll);
147
148 clk_disable(&s3c2442_clk_cam);
149
150 return 0;
151}
152
153static struct subsys_interface s3c2442_clk_interface = {
154 .name = "s3c2442_clk",
155 .subsys = &s3c2442_subsys,
156 .add_dev = s3c2442_clk_add,
157};
158
159static __init int s3c2442_clk_init(void)
160{
161 return subsys_interface_register(&s3c2442_clk_interface);
162}
163
164arch_initcall(s3c2442_clk_init);
165
166
167static struct device s3c2442_dev = { 56static struct device s3c2442_dev = {
168 .bus = &s3c2442_subsys, 57 .bus = &s3c2442_subsys,
169}; 58};
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index fe30ebb234d2..4a64bcc9eb51 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -46,6 +46,7 @@
46#include <plat/nand-core.h> 46#include <plat/nand-core.h>
47#include <plat/watchdog-reset.h> 47#include <plat/watchdog-reset.h>
48 48
49#include "common.h"
49#include "regs-dsc.h" 50#include "regs-dsc.h"
50 51
51static struct map_desc s3c244x_iodesc[] __initdata = { 52static struct map_desc s3c244x_iodesc[] __initdata = {
@@ -74,67 +75,11 @@ void __init s3c244x_map_io(void)
74 s3c_nand_setname("s3c2440-nand"); 75 s3c_nand_setname("s3c2440-nand");
75 s3c_device_ts.name = "s3c2440-ts"; 76 s3c_device_ts.name = "s3c2440-ts";
76 s3c_device_usbgadget.name = "s3c2440-usbgadget"; 77 s3c_device_usbgadget.name = "s3c2440-usbgadget";
78 s3c2410_device_dclk.name = "s3c2440-dclk";
77} 79}
78 80
79void __init_or_cpufreq s3c244x_setup_clocks(void) 81void __init_or_cpufreq s3c244x_setup_clocks(void)
80{ 82{
81 struct clk *xtal_clk;
82 unsigned long clkdiv;
83 unsigned long camdiv;
84 unsigned long xtal;
85 unsigned long hclk, fclk, pclk;
86 int hdiv = 1;
87
88 xtal_clk = clk_get(NULL, "xtal");
89 xtal = clk_get_rate(xtal_clk);
90 clk_put(xtal_clk);
91
92 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
93
94 clkdiv = __raw_readl(S3C2410_CLKDIVN);
95 camdiv = __raw_readl(S3C2440_CAMDIVN);
96
97 /* work out clock scalings */
98
99 switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
100 case S3C2440_CLKDIVN_HDIVN_1:
101 hdiv = 1;
102 break;
103
104 case S3C2440_CLKDIVN_HDIVN_2:
105 hdiv = 2;
106 break;
107
108 case S3C2440_CLKDIVN_HDIVN_4_8:
109 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
110 break;
111
112 case S3C2440_CLKDIVN_HDIVN_3_6:
113 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
114 break;
115 }
116
117 hclk = fclk / hdiv;
118 pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
119
120 /* print brief summary of clocks, etc */
121
122 printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
123 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
124
125 s3c24xx_setup_clocks(fclk, hclk, pclk);
126}
127
128void __init s3c244x_init_clocks(int xtal)
129{
130 /* initialise the clocks here, to allow other things like the
131 * console to use them, and to add new ones after the initialisation
132 */
133
134 s3c24xx_register_baseclocks(xtal);
135 s3c244x_setup_clocks();
136 s3c2410_baseclk_add();
137 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
138} 83}
139 84
140/* Since the S3C2442 and S3C2440 share items, put both subsystems here */ 85/* Since the S3C2442 and S3C2440 share items, put both subsystems here */
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index 7231c8e4975e..72d4178ad23b 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -119,6 +119,7 @@ struct s3c_plltab {
119struct s3c_cpufreq_config { 119struct s3c_cpufreq_config {
120 struct s3c_freq freq; 120 struct s3c_freq freq;
121 struct s3c_freq max; 121 struct s3c_freq max;
122 struct clk *mpll;
122 struct cpufreq_frequency_table pll; 123 struct cpufreq_frequency_table pll;
123 struct s3c_clkdivs divs; 124 struct s3c_clkdivs divs;
124 struct s3c_cpufreq_info *info; /* for core, not drivers */ 125 struct s3c_cpufreq_info *info; /* for core, not drivers */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 02:30:28 -0500