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authorBjorn Helgaas <bhelgaas@google.com>2017-09-07 14:24:19 -0400
committerBjorn Helgaas <bhelgaas@google.com>2017-09-07 14:24:19 -0400
commit9198407e23ec89f0e1562f439771aeea83345d0d (patch)
treec6a53b71b48c49d7713539eb035e7b2fcec69d2a /arch/tile/kernel
parentd872694bac212f76ca13fd20a85e5c1bdb53a945 (diff)
parentc775697b713b70293507573355aa8c8c177db35b (diff)
Merge branch 'pci/resource' into next
* pci/resource: microblaze/PCI: Remove pcibios_setup_bus_{self/devices} dead code ARC: Remove empty kernel/pcibios.c PCI: Add a generic weak pcibios_align_resource() PCI: Add a generic weak pcibios_fixup_bus()
Diffstat (limited to 'arch/tile/kernel')
-rw-r--r--arch/tile/kernel/pci.c18
-rw-r--r--arch/tile/kernel/pci_gx.c14
2 files changed, 0 insertions, 32 deletions
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index 884826157765..bbf81579b1f8 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -67,16 +67,6 @@ static struct pci_ops tile_cfg_ops;
67 67
68 68
69/* 69/*
70 * We don't need to worry about the alignment of resources.
71 */
72resource_size_t pcibios_align_resource(void *data, const struct resource *res,
73 resource_size_t size, resource_size_t align)
74{
75 return res->start;
76}
77EXPORT_SYMBOL(pcibios_align_resource);
78
79/*
80 * Open a FD to the hypervisor PCI device. 70 * Open a FD to the hypervisor PCI device.
81 * 71 *
82 * controller_id is the controller number, config type is 0 or 1 for 72 * controller_id is the controller number, config type is 0 or 1 for
@@ -380,14 +370,6 @@ int __init pcibios_init(void)
380} 370}
381subsys_initcall(pcibios_init); 371subsys_initcall(pcibios_init);
382 372
383/*
384 * No bus fixups needed.
385 */
386void pcibios_fixup_bus(struct pci_bus *bus)
387{
388 /* Nothing needs to be done. */
389}
390
391void pcibios_set_master(struct pci_dev *dev) 373void pcibios_set_master(struct pci_dev *dev)
392{ 374{
393 /* No special bus mastering setup handling. */ 375 /* No special bus mastering setup handling. */
diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c
index e68317083ac7..9aa238ac7b35 100644
--- a/arch/tile/kernel/pci_gx.c
+++ b/arch/tile/kernel/pci_gx.c
@@ -108,15 +108,6 @@ static struct pci_ops tile_cfg_ops;
108/* Mask of CPUs that should receive PCIe interrupts. */ 108/* Mask of CPUs that should receive PCIe interrupts. */
109static struct cpumask intr_cpus_map; 109static struct cpumask intr_cpus_map;
110 110
111/* We don't need to worry about the alignment of resources. */
112resource_size_t pcibios_align_resource(void *data, const struct resource *res,
113 resource_size_t size,
114 resource_size_t align)
115{
116 return res->start;
117}
118EXPORT_SYMBOL(pcibios_align_resource);
119
120/* 111/*
121 * Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #. 112 * Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #.
122 * For now, we simply send interrupts to non-dataplane CPUs. 113 * For now, we simply send interrupts to non-dataplane CPUs.
@@ -1049,11 +1040,6 @@ alloc_mem_map_failed:
1049} 1040}
1050subsys_initcall(pcibios_init); 1041subsys_initcall(pcibios_init);
1051 1042
1052/* No bus fixups needed. */
1053void pcibios_fixup_bus(struct pci_bus *bus)
1054{
1055}
1056
1057/* Process any "pci=" kernel boot arguments. */ 1043/* Process any "pci=" kernel boot arguments. */
1058char *__init pcibios_setup(char *str) 1044char *__init pcibios_setup(char *str)
1059{ 1045{