diff options
author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2013-12-06 04:59:50 -0500 |
---|---|---|
committer | Simon Horman <horms+renesas@verge.net.au> | 2013-12-24 07:49:43 -0500 |
commit | d5917ef318b850fc72bd10db438580f7d1c406d9 (patch) | |
tree | d9668264e93c430c6ecca5253fdfebb1f7bb720f /arch/sh | |
parent | 64c535e942af6cfe59ceceeb9bc6ba5f437a2fc9 (diff) |
sh: Don't set plat_sci_port scbrr_algo_id field
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/sh')
28 files changed, 0 insertions, 108 deletions
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c index 1a4fe7c0e548..3860b0be56c7 100644 --- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c +++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c | |||
@@ -63,7 +63,6 @@ static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL, | |||
63 | static struct plat_sci_port scif0_platform_data = { | 63 | static struct plat_sci_port scif0_platform_data = { |
64 | .flags = UPF_BOOT_AUTOCONF, | 64 | .flags = UPF_BOOT_AUTOCONF, |
65 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 65 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
66 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
67 | .type = PORT_SCIF, | 66 | .type = PORT_SCIF, |
68 | }; | 67 | }; |
69 | 68 | ||
@@ -85,7 +84,6 @@ static struct platform_device scif0_device = { | |||
85 | static struct plat_sci_port scif1_platform_data = { | 84 | static struct plat_sci_port scif1_platform_data = { |
86 | .flags = UPF_BOOT_AUTOCONF, | 85 | .flags = UPF_BOOT_AUTOCONF, |
87 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 86 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
88 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
89 | .type = PORT_SCIF, | 87 | .type = PORT_SCIF, |
90 | }; | 88 | }; |
91 | 89 | ||
@@ -107,7 +105,6 @@ static struct platform_device scif1_device = { | |||
107 | static struct plat_sci_port scif2_platform_data = { | 105 | static struct plat_sci_port scif2_platform_data = { |
108 | .flags = UPF_BOOT_AUTOCONF, | 106 | .flags = UPF_BOOT_AUTOCONF, |
109 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 107 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
110 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
111 | .type = PORT_SCIF, | 108 | .type = PORT_SCIF, |
112 | }; | 109 | }; |
113 | 110 | ||
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c index 9bdc61143f40..63e996f9a7ed 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c +++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c | |||
@@ -201,7 +201,6 @@ static struct platform_device mtu2_2_device = { | |||
201 | static struct plat_sci_port scif0_platform_data = { | 201 | static struct plat_sci_port scif0_platform_data = { |
202 | .flags = UPF_BOOT_AUTOCONF, | 202 | .flags = UPF_BOOT_AUTOCONF, |
203 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 203 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
204 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
205 | .type = PORT_SCIF, | 204 | .type = PORT_SCIF, |
206 | }; | 205 | }; |
207 | 206 | ||
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c index 7585c4ed7c5c..2c6874461536 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c | |||
@@ -180,7 +180,6 @@ static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups, | |||
180 | static struct plat_sci_port scif0_platform_data = { | 180 | static struct plat_sci_port scif0_platform_data = { |
181 | .flags = UPF_BOOT_AUTOCONF, | 181 | .flags = UPF_BOOT_AUTOCONF, |
182 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 182 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
183 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
184 | .type = PORT_SCIF, | 183 | .type = PORT_SCIF, |
185 | }; | 184 | }; |
186 | 185 | ||
@@ -202,7 +201,6 @@ static struct platform_device scif0_device = { | |||
202 | static struct plat_sci_port scif1_platform_data = { | 201 | static struct plat_sci_port scif1_platform_data = { |
203 | .flags = UPF_BOOT_AUTOCONF, | 202 | .flags = UPF_BOOT_AUTOCONF, |
204 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 203 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
205 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
206 | .type = PORT_SCIF, | 204 | .type = PORT_SCIF, |
207 | }; | 205 | }; |
208 | 206 | ||
@@ -224,7 +222,6 @@ static struct platform_device scif1_device = { | |||
224 | static struct plat_sci_port scif2_platform_data = { | 222 | static struct plat_sci_port scif2_platform_data = { |
225 | .flags = UPF_BOOT_AUTOCONF, | 223 | .flags = UPF_BOOT_AUTOCONF, |
226 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 224 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
227 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
228 | .type = PORT_SCIF, | 225 | .type = PORT_SCIF, |
229 | }; | 226 | }; |
230 | 227 | ||
@@ -246,7 +243,6 @@ static struct platform_device scif2_device = { | |||
246 | static struct plat_sci_port scif3_platform_data = { | 243 | static struct plat_sci_port scif3_platform_data = { |
247 | .flags = UPF_BOOT_AUTOCONF, | 244 | .flags = UPF_BOOT_AUTOCONF, |
248 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 245 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
249 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
250 | .type = PORT_SCIF, | 246 | .type = PORT_SCIF, |
251 | }; | 247 | }; |
252 | 248 | ||
@@ -268,7 +264,6 @@ static struct platform_device scif3_device = { | |||
268 | static struct plat_sci_port scif4_platform_data = { | 264 | static struct plat_sci_port scif4_platform_data = { |
269 | .flags = UPF_BOOT_AUTOCONF, | 265 | .flags = UPF_BOOT_AUTOCONF, |
270 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 266 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
271 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
272 | .type = PORT_SCIF, | 267 | .type = PORT_SCIF, |
273 | }; | 268 | }; |
274 | 269 | ||
@@ -290,7 +285,6 @@ static struct platform_device scif4_device = { | |||
290 | static struct plat_sci_port scif5_platform_data = { | 285 | static struct plat_sci_port scif5_platform_data = { |
291 | .flags = UPF_BOOT_AUTOCONF, | 286 | .flags = UPF_BOOT_AUTOCONF, |
292 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 287 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
293 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
294 | .type = PORT_SCIF, | 288 | .type = PORT_SCIF, |
295 | }; | 289 | }; |
296 | 290 | ||
@@ -312,7 +306,6 @@ static struct platform_device scif5_device = { | |||
312 | static struct plat_sci_port scif6_platform_data = { | 306 | static struct plat_sci_port scif6_platform_data = { |
313 | .flags = UPF_BOOT_AUTOCONF, | 307 | .flags = UPF_BOOT_AUTOCONF, |
314 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 308 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
315 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
316 | .type = PORT_SCIF, | 309 | .type = PORT_SCIF, |
317 | }; | 310 | }; |
318 | 311 | ||
@@ -334,7 +327,6 @@ static struct platform_device scif6_device = { | |||
334 | static struct plat_sci_port scif7_platform_data = { | 327 | static struct plat_sci_port scif7_platform_data = { |
335 | .flags = UPF_BOOT_AUTOCONF, | 328 | .flags = UPF_BOOT_AUTOCONF, |
336 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 329 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
337 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
338 | .type = PORT_SCIF, | 330 | .type = PORT_SCIF, |
339 | }; | 331 | }; |
340 | 332 | ||
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c index f2a9baaa541b..d55a0f30ada3 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c | |||
@@ -177,7 +177,6 @@ static struct plat_sci_port scif0_platform_data = { | |||
177 | .flags = UPF_BOOT_AUTOCONF, | 177 | .flags = UPF_BOOT_AUTOCONF, |
178 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 178 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
179 | SCSCR_REIE, | 179 | SCSCR_REIE, |
180 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
181 | .type = PORT_SCIF, | 180 | .type = PORT_SCIF, |
182 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 181 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
183 | }; | 182 | }; |
@@ -201,7 +200,6 @@ static struct plat_sci_port scif1_platform_data = { | |||
201 | .flags = UPF_BOOT_AUTOCONF, | 200 | .flags = UPF_BOOT_AUTOCONF, |
202 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 201 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
203 | SCSCR_REIE, | 202 | SCSCR_REIE, |
204 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
205 | .type = PORT_SCIF, | 203 | .type = PORT_SCIF, |
206 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 204 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
207 | }; | 205 | }; |
@@ -225,7 +223,6 @@ static struct plat_sci_port scif2_platform_data = { | |||
225 | .flags = UPF_BOOT_AUTOCONF, | 223 | .flags = UPF_BOOT_AUTOCONF, |
226 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 224 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
227 | SCSCR_REIE, | 225 | SCSCR_REIE, |
228 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
229 | .type = PORT_SCIF, | 226 | .type = PORT_SCIF, |
230 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 227 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
231 | }; | 228 | }; |
@@ -249,7 +246,6 @@ static struct plat_sci_port scif3_platform_data = { | |||
249 | .flags = UPF_BOOT_AUTOCONF, | 246 | .flags = UPF_BOOT_AUTOCONF, |
250 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 247 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
251 | SCSCR_REIE, | 248 | SCSCR_REIE, |
252 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
253 | .type = PORT_SCIF, | 249 | .type = PORT_SCIF, |
254 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 250 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
255 | }; | 251 | }; |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c index fc7cacd36729..241e745e3ced 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c | |||
@@ -136,7 +136,6 @@ static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups, | |||
136 | static struct plat_sci_port scif0_platform_data = { | 136 | static struct plat_sci_port scif0_platform_data = { |
137 | .flags = UPF_BOOT_AUTOCONF, | 137 | .flags = UPF_BOOT_AUTOCONF, |
138 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 138 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
139 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
140 | .type = PORT_SCIF, | 139 | .type = PORT_SCIF, |
141 | }; | 140 | }; |
142 | 141 | ||
@@ -158,7 +157,6 @@ static struct platform_device scif0_device = { | |||
158 | static struct plat_sci_port scif1_platform_data = { | 157 | static struct plat_sci_port scif1_platform_data = { |
159 | .flags = UPF_BOOT_AUTOCONF, | 158 | .flags = UPF_BOOT_AUTOCONF, |
160 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 159 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
161 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
162 | .type = PORT_SCIF, | 160 | .type = PORT_SCIF, |
163 | }; | 161 | }; |
164 | 162 | ||
@@ -180,7 +178,6 @@ static struct platform_device scif1_device = { | |||
180 | static struct plat_sci_port scif2_platform_data = { | 178 | static struct plat_sci_port scif2_platform_data = { |
181 | .flags = UPF_BOOT_AUTOCONF, | 179 | .flags = UPF_BOOT_AUTOCONF, |
182 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 180 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
183 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
184 | .type = PORT_SCIF, | 181 | .type = PORT_SCIF, |
185 | }; | 182 | }; |
186 | 183 | ||
@@ -202,7 +199,6 @@ static struct platform_device scif2_device = { | |||
202 | static struct plat_sci_port scif3_platform_data = { | 199 | static struct plat_sci_port scif3_platform_data = { |
203 | .flags = UPF_BOOT_AUTOCONF, | 200 | .flags = UPF_BOOT_AUTOCONF, |
204 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 201 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
205 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
206 | .type = PORT_SCIF, | 202 | .type = PORT_SCIF, |
207 | }; | 203 | }; |
208 | 204 | ||
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c index 00edbdabcaa1..ad5b0f429882 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c | |||
@@ -229,7 +229,6 @@ static struct plat_sci_port scif0_platform_data = { | |||
229 | .flags = UPF_BOOT_AUTOCONF, | 229 | .flags = UPF_BOOT_AUTOCONF, |
230 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 230 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
231 | SCSCR_REIE | SCSCR_TOIE, | 231 | SCSCR_REIE | SCSCR_TOIE, |
232 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
233 | .type = PORT_SCIF, | 232 | .type = PORT_SCIF, |
234 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 233 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
235 | }; | 234 | }; |
@@ -256,7 +255,6 @@ static struct plat_sci_port scif1_platform_data = { | |||
256 | .flags = UPF_BOOT_AUTOCONF, | 255 | .flags = UPF_BOOT_AUTOCONF, |
257 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 256 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
258 | SCSCR_REIE | SCSCR_TOIE, | 257 | SCSCR_REIE | SCSCR_TOIE, |
259 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
260 | .type = PORT_SCIF, | 258 | .type = PORT_SCIF, |
261 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 259 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
262 | }; | 260 | }; |
@@ -283,7 +281,6 @@ static struct plat_sci_port scif2_platform_data = { | |||
283 | .flags = UPF_BOOT_AUTOCONF, | 281 | .flags = UPF_BOOT_AUTOCONF, |
284 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 282 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
285 | SCSCR_REIE | SCSCR_TOIE, | 283 | SCSCR_REIE | SCSCR_TOIE, |
286 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
287 | .type = PORT_SCIF, | 284 | .type = PORT_SCIF, |
288 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 285 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
289 | }; | 286 | }; |
@@ -310,7 +307,6 @@ static struct plat_sci_port scif3_platform_data = { | |||
310 | .flags = UPF_BOOT_AUTOCONF, | 307 | .flags = UPF_BOOT_AUTOCONF, |
311 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 308 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
312 | SCSCR_REIE | SCSCR_TOIE, | 309 | SCSCR_REIE | SCSCR_TOIE, |
313 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
314 | .type = PORT_SCIF, | 310 | .type = PORT_SCIF, |
315 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 311 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
316 | }; | 312 | }; |
@@ -337,7 +333,6 @@ static struct plat_sci_port scif4_platform_data = { | |||
337 | .flags = UPF_BOOT_AUTOCONF, | 333 | .flags = UPF_BOOT_AUTOCONF, |
338 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 334 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
339 | SCSCR_REIE | SCSCR_TOIE, | 335 | SCSCR_REIE | SCSCR_TOIE, |
340 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
341 | .type = PORT_SCIF, | 336 | .type = PORT_SCIF, |
342 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 337 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
343 | }; | 338 | }; |
@@ -364,7 +359,6 @@ static struct plat_sci_port scif5_platform_data = { | |||
364 | .flags = UPF_BOOT_AUTOCONF, | 359 | .flags = UPF_BOOT_AUTOCONF, |
365 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 360 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
366 | SCSCR_REIE | SCSCR_TOIE, | 361 | SCSCR_REIE | SCSCR_TOIE, |
367 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
368 | .type = PORT_SCIF, | 362 | .type = PORT_SCIF, |
369 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 363 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
370 | }; | 364 | }; |
@@ -391,7 +385,6 @@ static struct plat_sci_port scif6_platform_data = { | |||
391 | .flags = UPF_BOOT_AUTOCONF, | 385 | .flags = UPF_BOOT_AUTOCONF, |
392 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 386 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
393 | SCSCR_REIE | SCSCR_TOIE, | 387 | SCSCR_REIE | SCSCR_TOIE, |
394 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
395 | .type = PORT_SCIF, | 388 | .type = PORT_SCIF, |
396 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 389 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
397 | }; | 390 | }; |
@@ -418,7 +411,6 @@ static struct plat_sci_port scif7_platform_data = { | |||
418 | .flags = UPF_BOOT_AUTOCONF, | 411 | .flags = UPF_BOOT_AUTOCONF, |
419 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 412 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
420 | SCSCR_REIE | SCSCR_TOIE, | 413 | SCSCR_REIE | SCSCR_TOIE, |
421 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
422 | .type = PORT_SCIF, | 414 | .type = PORT_SCIF, |
423 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 415 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
424 | }; | 416 | }; |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c index 5cdbaac322a0..3995119f65dc 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c | |||
@@ -251,7 +251,6 @@ static struct plat_sci_port scif0_platform_data = { | |||
251 | .flags = UPF_BOOT_AUTOCONF, | 251 | .flags = UPF_BOOT_AUTOCONF, |
252 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 252 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
253 | SCSCR_REIE | SCSCR_TOIE, | 253 | SCSCR_REIE | SCSCR_TOIE, |
254 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
255 | .type = PORT_SCIF, | 254 | .type = PORT_SCIF, |
256 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 255 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
257 | }; | 256 | }; |
@@ -278,7 +277,6 @@ static struct plat_sci_port scif1_platform_data = { | |||
278 | .flags = UPF_BOOT_AUTOCONF, | 277 | .flags = UPF_BOOT_AUTOCONF, |
279 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 278 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
280 | SCSCR_REIE | SCSCR_TOIE, | 279 | SCSCR_REIE | SCSCR_TOIE, |
281 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
282 | .type = PORT_SCIF, | 280 | .type = PORT_SCIF, |
283 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 281 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
284 | }; | 282 | }; |
@@ -305,7 +303,6 @@ static struct plat_sci_port scif2_platform_data = { | |||
305 | .flags = UPF_BOOT_AUTOCONF, | 303 | .flags = UPF_BOOT_AUTOCONF, |
306 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 304 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
307 | SCSCR_REIE | SCSCR_TOIE, | 305 | SCSCR_REIE | SCSCR_TOIE, |
308 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
309 | .type = PORT_SCIF, | 306 | .type = PORT_SCIF, |
310 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 307 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
311 | }; | 308 | }; |
@@ -332,7 +329,6 @@ static struct plat_sci_port scif3_platform_data = { | |||
332 | .flags = UPF_BOOT_AUTOCONF, | 329 | .flags = UPF_BOOT_AUTOCONF, |
333 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 330 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
334 | SCSCR_REIE | SCSCR_TOIE, | 331 | SCSCR_REIE | SCSCR_TOIE, |
335 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
336 | .type = PORT_SCIF, | 332 | .type = PORT_SCIF, |
337 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 333 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
338 | }; | 334 | }; |
@@ -359,7 +355,6 @@ static struct plat_sci_port scif4_platform_data = { | |||
359 | .flags = UPF_BOOT_AUTOCONF, | 355 | .flags = UPF_BOOT_AUTOCONF, |
360 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 356 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
361 | SCSCR_REIE | SCSCR_TOIE, | 357 | SCSCR_REIE | SCSCR_TOIE, |
362 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
363 | .type = PORT_SCIF, | 358 | .type = PORT_SCIF, |
364 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 359 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
365 | }; | 360 | }; |
@@ -386,7 +381,6 @@ static struct plat_sci_port scif5_platform_data = { | |||
386 | .flags = UPF_BOOT_AUTOCONF, | 381 | .flags = UPF_BOOT_AUTOCONF, |
387 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 382 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
388 | SCSCR_REIE | SCSCR_TOIE, | 383 | SCSCR_REIE | SCSCR_TOIE, |
389 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
390 | .type = PORT_SCIF, | 384 | .type = PORT_SCIF, |
391 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 385 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
392 | }; | 386 | }; |
@@ -413,7 +407,6 @@ static struct plat_sci_port scif6_platform_data = { | |||
413 | .flags = UPF_BOOT_AUTOCONF, | 407 | .flags = UPF_BOOT_AUTOCONF, |
414 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 408 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
415 | SCSCR_REIE | SCSCR_TOIE, | 409 | SCSCR_REIE | SCSCR_TOIE, |
416 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
417 | .type = PORT_SCIF, | 410 | .type = PORT_SCIF, |
418 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 411 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
419 | }; | 412 | }; |
@@ -440,7 +433,6 @@ static struct plat_sci_port scif7_platform_data = { | |||
440 | .flags = UPF_BOOT_AUTOCONF, | 433 | .flags = UPF_BOOT_AUTOCONF, |
441 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 434 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
442 | SCSCR_REIE | SCSCR_TOIE, | 435 | SCSCR_REIE | SCSCR_TOIE, |
443 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
444 | .type = PORT_SCIF, | 436 | .type = PORT_SCIF, |
445 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 437 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
446 | }; | 438 | }; |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c index 10dd0a01d5f8..c76b2543b85f 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c | |||
@@ -73,7 +73,6 @@ static struct plat_sci_port scif0_platform_data = { | |||
73 | .flags = UPF_BOOT_AUTOCONF, | 73 | .flags = UPF_BOOT_AUTOCONF, |
74 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | | 74 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | |
75 | SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, | 75 | SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, |
76 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
77 | .type = PORT_SCIF, | 76 | .type = PORT_SCIF, |
78 | .ops = &sh770x_sci_port_ops, | 77 | .ops = &sh770x_sci_port_ops, |
79 | .regtype = SCIx_SH7705_SCIF_REGTYPE, | 78 | .regtype = SCIx_SH7705_SCIF_REGTYPE, |
@@ -97,7 +96,6 @@ static struct platform_device scif0_device = { | |||
97 | static struct plat_sci_port scif1_platform_data = { | 96 | static struct plat_sci_port scif1_platform_data = { |
98 | .flags = UPF_BOOT_AUTOCONF, | 97 | .flags = UPF_BOOT_AUTOCONF, |
99 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, | 98 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, |
100 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
101 | .type = PORT_SCIF, | 99 | .type = PORT_SCIF, |
102 | .ops = &sh770x_sci_port_ops, | 100 | .ops = &sh770x_sci_port_ops, |
103 | .regtype = SCIx_SH7705_SCIF_REGTYPE, | 101 | .regtype = SCIx_SH7705_SCIF_REGTYPE, |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c index d5541b0a6dc5..ff1465c0519c 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c | |||
@@ -112,7 +112,6 @@ static struct plat_sci_port scif0_platform_data = { | |||
112 | .port_reg = 0xa4000136, | 112 | .port_reg = 0xa4000136, |
113 | .flags = UPF_BOOT_AUTOCONF, | 113 | .flags = UPF_BOOT_AUTOCONF, |
114 | .scscr = SCSCR_TE | SCSCR_RE, | 114 | .scscr = SCSCR_TE | SCSCR_RE, |
115 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
116 | .type = PORT_SCI, | 115 | .type = PORT_SCI, |
117 | .ops = &sh770x_sci_port_ops, | 116 | .ops = &sh770x_sci_port_ops, |
118 | .regshift = 1, | 117 | .regshift = 1, |
@@ -138,7 +137,6 @@ static struct platform_device scif0_device = { | |||
138 | static struct plat_sci_port scif1_platform_data = { | 137 | static struct plat_sci_port scif1_platform_data = { |
139 | .flags = UPF_BOOT_AUTOCONF, | 138 | .flags = UPF_BOOT_AUTOCONF, |
140 | .scscr = SCSCR_TE | SCSCR_RE, | 139 | .scscr = SCSCR_TE | SCSCR_RE, |
141 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
142 | .type = PORT_SCIF, | 140 | .type = PORT_SCIF, |
143 | .ops = &sh770x_sci_port_ops, | 141 | .ops = &sh770x_sci_port_ops, |
144 | .regtype = SCIx_SH3_SCIF_REGTYPE, | 142 | .regtype = SCIx_SH3_SCIF_REGTYPE, |
@@ -165,7 +163,6 @@ static struct plat_sci_port scif2_platform_data = { | |||
165 | .port_reg = SCIx_NOT_SUPPORTED, | 163 | .port_reg = SCIx_NOT_SUPPORTED, |
166 | .flags = UPF_BOOT_AUTOCONF, | 164 | .flags = UPF_BOOT_AUTOCONF, |
167 | .scscr = SCSCR_TE | SCSCR_RE, | 165 | .scscr = SCSCR_TE | SCSCR_RE, |
168 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
169 | .type = PORT_IRDA, | 166 | .type = PORT_IRDA, |
170 | .ops = &sh770x_sci_port_ops, | 167 | .ops = &sh770x_sci_port_ops, |
171 | .regshift = 1, | 168 | .regshift = 1, |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c index de229f5c6b1e..e2ce9360ed5a 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c | |||
@@ -101,7 +101,6 @@ static struct plat_sci_port scif0_platform_data = { | |||
101 | .flags = UPF_BOOT_AUTOCONF, | 101 | .flags = UPF_BOOT_AUTOCONF, |
102 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | | 102 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | |
103 | SCSCR_CKE1 | SCSCR_CKE0, | 103 | SCSCR_CKE1 | SCSCR_CKE0, |
104 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
105 | .type = PORT_SCIF, | 104 | .type = PORT_SCIF, |
106 | }; | 105 | }; |
107 | 106 | ||
@@ -124,7 +123,6 @@ static struct plat_sci_port scif1_platform_data = { | |||
124 | .flags = UPF_BOOT_AUTOCONF, | 123 | .flags = UPF_BOOT_AUTOCONF, |
125 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | | 124 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | |
126 | SCSCR_CKE1 | SCSCR_CKE0, | 125 | SCSCR_CKE1 | SCSCR_CKE0, |
127 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
128 | .type = PORT_SCIF, | 126 | .type = PORT_SCIF, |
129 | }; | 127 | }; |
130 | 128 | ||
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c index ca835819357b..1d5729dc0724 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c | |||
@@ -54,7 +54,6 @@ static struct platform_device rtc_device = { | |||
54 | static struct plat_sci_port scif0_platform_data = { | 54 | static struct plat_sci_port scif0_platform_data = { |
55 | .flags = UPF_BOOT_AUTOCONF, | 55 | .flags = UPF_BOOT_AUTOCONF, |
56 | .scscr = SCSCR_RE | SCSCR_TE, | 56 | .scscr = SCSCR_RE | SCSCR_TE, |
57 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
58 | .type = PORT_SCIF, | 57 | .type = PORT_SCIF, |
59 | .ops = &sh7720_sci_port_ops, | 58 | .ops = &sh7720_sci_port_ops, |
60 | .regtype = SCIx_SH7705_SCIF_REGTYPE, | 59 | .regtype = SCIx_SH7705_SCIF_REGTYPE, |
@@ -78,7 +77,6 @@ static struct platform_device scif0_device = { | |||
78 | static struct plat_sci_port scif1_platform_data = { | 77 | static struct plat_sci_port scif1_platform_data = { |
79 | .flags = UPF_BOOT_AUTOCONF, | 78 | .flags = UPF_BOOT_AUTOCONF, |
80 | .scscr = SCSCR_RE | SCSCR_TE, | 79 | .scscr = SCSCR_RE | SCSCR_TE, |
81 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
82 | .type = PORT_SCIF, | 80 | .type = PORT_SCIF, |
83 | .ops = &sh7720_sci_port_ops, | 81 | .ops = &sh7720_sci_port_ops, |
84 | .regtype = SCIx_SH7705_SCIF_REGTYPE, | 82 | .regtype = SCIx_SH7705_SCIF_REGTYPE, |
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c index 0fc6a105144a..a8bd778d5ac8 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c | |||
@@ -19,7 +19,6 @@ | |||
19 | static struct plat_sci_port scif0_platform_data = { | 19 | static struct plat_sci_port scif0_platform_data = { |
20 | .flags = UPF_BOOT_AUTOCONF, | 20 | .flags = UPF_BOOT_AUTOCONF, |
21 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 21 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
22 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
23 | .type = PORT_SCIF, | 22 | .type = PORT_SCIF, |
24 | }; | 23 | }; |
25 | 24 | ||
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c index 5613c15d8163..a447a248491f 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c | |||
@@ -41,7 +41,6 @@ static struct plat_sci_port sci_platform_data = { | |||
41 | .port_reg = 0xffe0001C, | 41 | .port_reg = 0xffe0001C, |
42 | .flags = UPF_BOOT_AUTOCONF, | 42 | .flags = UPF_BOOT_AUTOCONF, |
43 | .scscr = SCSCR_TE | SCSCR_RE, | 43 | .scscr = SCSCR_TE | SCSCR_RE, |
44 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
45 | .type = PORT_SCI, | 44 | .type = PORT_SCI, |
46 | .regshift = 2, | 45 | .regshift = 2, |
47 | }; | 46 | }; |
@@ -64,7 +63,6 @@ static struct platform_device sci_device = { | |||
64 | static struct plat_sci_port scif_platform_data = { | 63 | static struct plat_sci_port scif_platform_data = { |
65 | .flags = UPF_BOOT_AUTOCONF, | 64 | .flags = UPF_BOOT_AUTOCONF, |
66 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, | 65 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, |
67 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
68 | .type = PORT_SCIF, | 66 | .type = PORT_SCIF, |
69 | }; | 67 | }; |
70 | 68 | ||
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c index a83e6f5a42d0..1abd9fb4a386 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c | |||
@@ -130,7 +130,6 @@ static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups, | |||
130 | static struct plat_sci_port scif0_platform_data = { | 130 | static struct plat_sci_port scif0_platform_data = { |
131 | .flags = UPF_BOOT_AUTOCONF, | 131 | .flags = UPF_BOOT_AUTOCONF, |
132 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 132 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
133 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
134 | .type = PORT_SCIF, | 133 | .type = PORT_SCIF, |
135 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 134 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
136 | }; | 135 | }; |
@@ -157,7 +156,6 @@ static struct plat_sci_port scif1_platform_data = { | |||
157 | .flags = UPF_BOOT_AUTOCONF, | 156 | .flags = UPF_BOOT_AUTOCONF, |
158 | .type = PORT_SCIF, | 157 | .type = PORT_SCIF, |
159 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 158 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
160 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
161 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 159 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
162 | }; | 160 | }; |
163 | 161 | ||
@@ -182,7 +180,6 @@ static struct platform_device scif1_device = { | |||
182 | static struct plat_sci_port scif2_platform_data = { | 180 | static struct plat_sci_port scif2_platform_data = { |
183 | .flags = UPF_BOOT_AUTOCONF, | 181 | .flags = UPF_BOOT_AUTOCONF, |
184 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 182 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
185 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
186 | .type = PORT_SCIF, | 183 | .type = PORT_SCIF, |
187 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 184 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
188 | }; | 185 | }; |
@@ -208,7 +205,6 @@ static struct platform_device scif2_device = { | |||
208 | static struct plat_sci_port scif3_platform_data = { | 205 | static struct plat_sci_port scif3_platform_data = { |
209 | .flags = UPF_BOOT_AUTOCONF, | 206 | .flags = UPF_BOOT_AUTOCONF, |
210 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 207 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
211 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
212 | .type = PORT_SCI, | 208 | .type = PORT_SCI, |
213 | .regshift = 2, | 209 | .regshift = 2, |
214 | }; | 210 | }; |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c index 8b45f672448d..245d19254489 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c | |||
@@ -20,7 +20,6 @@ | |||
20 | static struct plat_sci_port scif0_platform_data = { | 20 | static struct plat_sci_port scif0_platform_data = { |
21 | .flags = UPF_BOOT_AUTOCONF, | 21 | .flags = UPF_BOOT_AUTOCONF, |
22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
23 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
24 | .type = PORT_SCIF, | 23 | .type = PORT_SCIF, |
25 | }; | 24 | }; |
26 | 25 | ||
@@ -42,7 +41,6 @@ static struct platform_device scif0_device = { | |||
42 | static struct plat_sci_port scif1_platform_data = { | 41 | static struct plat_sci_port scif1_platform_data = { |
43 | .flags = UPF_BOOT_AUTOCONF, | 42 | .flags = UPF_BOOT_AUTOCONF, |
44 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 43 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
45 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
46 | .type = PORT_SCIF, | 44 | .type = PORT_SCIF, |
47 | }; | 45 | }; |
48 | 46 | ||
@@ -64,7 +62,6 @@ static struct platform_device scif1_device = { | |||
64 | static struct plat_sci_port scif2_platform_data = { | 62 | static struct plat_sci_port scif2_platform_data = { |
65 | .flags = UPF_BOOT_AUTOCONF, | 63 | .flags = UPF_BOOT_AUTOCONF, |
66 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 64 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
67 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
68 | .type = PORT_SCIF, | 65 | .type = PORT_SCIF, |
69 | }; | 66 | }; |
70 | 67 | ||
@@ -86,7 +83,6 @@ static struct platform_device scif2_device = { | |||
86 | static struct plat_sci_port scif3_platform_data = { | 83 | static struct plat_sci_port scif3_platform_data = { |
87 | .flags = UPF_BOOT_AUTOCONF, | 84 | .flags = UPF_BOOT_AUTOCONF, |
88 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 85 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
89 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
90 | .type = PORT_SCIF, | 86 | .type = PORT_SCIF, |
91 | }; | 87 | }; |
92 | 88 | ||
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c index 317f710a5b2b..6f56cbd76b20 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c | |||
@@ -23,7 +23,6 @@ static struct plat_sci_port scif0_platform_data = { | |||
23 | .port_reg = 0xa405013e, | 23 | .port_reg = 0xa405013e, |
24 | .flags = UPF_BOOT_AUTOCONF, | 24 | .flags = UPF_BOOT_AUTOCONF, |
25 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 25 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
26 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
27 | .type = PORT_SCIF, | 26 | .type = PORT_SCIF, |
28 | }; | 27 | }; |
29 | 28 | ||
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index 6aeebb5299f6..5a94efc8d4ce 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c | |||
@@ -181,7 +181,6 @@ struct platform_device dma_device = { | |||
181 | static struct plat_sci_port scif0_platform_data = { | 181 | static struct plat_sci_port scif0_platform_data = { |
182 | .flags = UPF_BOOT_AUTOCONF, | 182 | .flags = UPF_BOOT_AUTOCONF, |
183 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 183 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
184 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
185 | .type = PORT_SCIF, | 184 | .type = PORT_SCIF, |
186 | .ops = &sh7722_sci_port_ops, | 185 | .ops = &sh7722_sci_port_ops, |
187 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 186 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
@@ -205,7 +204,6 @@ static struct platform_device scif0_device = { | |||
205 | static struct plat_sci_port scif1_platform_data = { | 204 | static struct plat_sci_port scif1_platform_data = { |
206 | .flags = UPF_BOOT_AUTOCONF, | 205 | .flags = UPF_BOOT_AUTOCONF, |
207 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 206 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
208 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
209 | .type = PORT_SCIF, | 207 | .type = PORT_SCIF, |
210 | .ops = &sh7722_sci_port_ops, | 208 | .ops = &sh7722_sci_port_ops, |
211 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 209 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
@@ -229,7 +227,6 @@ static struct platform_device scif1_device = { | |||
229 | static struct plat_sci_port scif2_platform_data = { | 227 | static struct plat_sci_port scif2_platform_data = { |
230 | .flags = UPF_BOOT_AUTOCONF, | 228 | .flags = UPF_BOOT_AUTOCONF, |
231 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 229 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
232 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
233 | .type = PORT_SCIF, | 230 | .type = PORT_SCIF, |
234 | .ops = &sh7722_sci_port_ops, | 231 | .ops = &sh7722_sci_port_ops, |
235 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 232 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index 079951be4122..3c5eb0993a75 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c | |||
@@ -26,7 +26,6 @@ static struct plat_sci_port scif0_platform_data = { | |||
26 | .port_reg = 0xa4050160, | 26 | .port_reg = 0xa4050160, |
27 | .flags = UPF_BOOT_AUTOCONF, | 27 | .flags = UPF_BOOT_AUTOCONF, |
28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
29 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
30 | .type = PORT_SCIF, | 29 | .type = PORT_SCIF, |
31 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 30 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
32 | }; | 31 | }; |
@@ -50,7 +49,6 @@ static struct plat_sci_port scif1_platform_data = { | |||
50 | .port_reg = SCIx_NOT_SUPPORTED, | 49 | .port_reg = SCIx_NOT_SUPPORTED, |
51 | .flags = UPF_BOOT_AUTOCONF, | 50 | .flags = UPF_BOOT_AUTOCONF, |
52 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 51 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
53 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
54 | .type = PORT_SCIF, | 52 | .type = PORT_SCIF, |
55 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 53 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
56 | }; | 54 | }; |
@@ -74,7 +72,6 @@ static struct plat_sci_port scif2_platform_data = { | |||
74 | .port_reg = SCIx_NOT_SUPPORTED, | 72 | .port_reg = SCIx_NOT_SUPPORTED, |
75 | .flags = UPF_BOOT_AUTOCONF, | 73 | .flags = UPF_BOOT_AUTOCONF, |
76 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 74 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
77 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
78 | .type = PORT_SCIF, | 75 | .type = PORT_SCIF, |
79 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 76 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
80 | }; | 77 | }; |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index 59c359469f13..60ebbc6842ff 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c | |||
@@ -293,7 +293,6 @@ static struct plat_sci_port scif0_platform_data = { | |||
293 | .port_reg = SCIx_NOT_SUPPORTED, | 293 | .port_reg = SCIx_NOT_SUPPORTED, |
294 | .flags = UPF_BOOT_AUTOCONF, | 294 | .flags = UPF_BOOT_AUTOCONF, |
295 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 295 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
296 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
297 | .type = PORT_SCIF, | 296 | .type = PORT_SCIF, |
298 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 297 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
299 | }; | 298 | }; |
@@ -317,7 +316,6 @@ static struct plat_sci_port scif1_platform_data = { | |||
317 | .port_reg = SCIx_NOT_SUPPORTED, | 316 | .port_reg = SCIx_NOT_SUPPORTED, |
318 | .flags = UPF_BOOT_AUTOCONF, | 317 | .flags = UPF_BOOT_AUTOCONF, |
319 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 318 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
320 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
321 | .type = PORT_SCIF, | 319 | .type = PORT_SCIF, |
322 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 320 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
323 | }; | 321 | }; |
@@ -341,7 +339,6 @@ static struct plat_sci_port scif2_platform_data = { | |||
341 | .port_reg = SCIx_NOT_SUPPORTED, | 339 | .port_reg = SCIx_NOT_SUPPORTED, |
342 | .flags = UPF_BOOT_AUTOCONF, | 340 | .flags = UPF_BOOT_AUTOCONF, |
343 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 341 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
344 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
345 | .type = PORT_SCIF, | 342 | .type = PORT_SCIF, |
346 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 343 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
347 | }; | 344 | }; |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c index bedf8fb5be6f..dad4ed1b2f94 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c | |||
@@ -27,7 +27,6 @@ | |||
27 | static struct plat_sci_port scif0_platform_data = { | 27 | static struct plat_sci_port scif0_platform_data = { |
28 | .flags = UPF_BOOT_AUTOCONF, | 28 | .flags = UPF_BOOT_AUTOCONF, |
29 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 29 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
30 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
31 | .type = PORT_SCIF, | 30 | .type = PORT_SCIF, |
32 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 31 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
33 | }; | 32 | }; |
@@ -50,7 +49,6 @@ static struct platform_device scif0_device = { | |||
50 | static struct plat_sci_port scif1_platform_data = { | 49 | static struct plat_sci_port scif1_platform_data = { |
51 | .flags = UPF_BOOT_AUTOCONF, | 50 | .flags = UPF_BOOT_AUTOCONF, |
52 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 51 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
53 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
54 | .type = PORT_SCIF, | 52 | .type = PORT_SCIF, |
55 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 53 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
56 | }; | 54 | }; |
@@ -73,7 +71,6 @@ static struct platform_device scif1_device = { | |||
73 | static struct plat_sci_port scif2_platform_data = { | 71 | static struct plat_sci_port scif2_platform_data = { |
74 | .flags = UPF_BOOT_AUTOCONF, | 72 | .flags = UPF_BOOT_AUTOCONF, |
75 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 73 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
76 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
77 | .type = PORT_SCIF, | 74 | .type = PORT_SCIF, |
78 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 75 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
79 | }; | 76 | }; |
@@ -96,7 +93,6 @@ static struct platform_device scif2_device = { | |||
96 | static struct plat_sci_port scif3_platform_data = { | 93 | static struct plat_sci_port scif3_platform_data = { |
97 | .flags = UPF_BOOT_AUTOCONF, | 94 | .flags = UPF_BOOT_AUTOCONF, |
98 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 95 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
99 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
100 | .type = PORT_SCIF, | 96 | .type = PORT_SCIF, |
101 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 97 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
102 | }; | 98 | }; |
@@ -119,7 +115,6 @@ static struct platform_device scif3_device = { | |||
119 | static struct plat_sci_port scif4_platform_data = { | 115 | static struct plat_sci_port scif4_platform_data = { |
120 | .flags = UPF_BOOT_AUTOCONF, | 116 | .flags = UPF_BOOT_AUTOCONF, |
121 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 117 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
122 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
123 | .type = PORT_SCIF, | 118 | .type = PORT_SCIF, |
124 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 119 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
125 | }; | 120 | }; |
@@ -142,7 +137,6 @@ static struct platform_device scif4_device = { | |||
142 | static struct plat_sci_port scif5_platform_data = { | 137 | static struct plat_sci_port scif5_platform_data = { |
143 | .flags = UPF_BOOT_AUTOCONF, | 138 | .flags = UPF_BOOT_AUTOCONF, |
144 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 139 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
145 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
146 | .type = PORT_SCIF, | 140 | .type = PORT_SCIF, |
147 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 141 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
148 | }; | 142 | }; |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c index 6b8d0e61704c..e43e5db53913 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c | |||
@@ -26,7 +26,6 @@ | |||
26 | static struct plat_sci_port scif2_platform_data = { | 26 | static struct plat_sci_port scif2_platform_data = { |
27 | .flags = UPF_BOOT_AUTOCONF, | 27 | .flags = UPF_BOOT_AUTOCONF, |
28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
29 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
30 | .type = PORT_SCIF, | 29 | .type = PORT_SCIF, |
31 | }; | 30 | }; |
32 | 31 | ||
@@ -48,7 +47,6 @@ static struct platform_device scif2_device = { | |||
48 | static struct plat_sci_port scif3_platform_data = { | 47 | static struct plat_sci_port scif3_platform_data = { |
49 | .flags = UPF_BOOT_AUTOCONF, | 48 | .flags = UPF_BOOT_AUTOCONF, |
50 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 49 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
51 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
52 | .type = PORT_SCIF, | 50 | .type = PORT_SCIF, |
53 | }; | 51 | }; |
54 | 52 | ||
@@ -70,7 +68,6 @@ static struct platform_device scif3_device = { | |||
70 | static struct plat_sci_port scif4_platform_data = { | 68 | static struct plat_sci_port scif4_platform_data = { |
71 | .flags = UPF_BOOT_AUTOCONF, | 69 | .flags = UPF_BOOT_AUTOCONF, |
72 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 70 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
73 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
74 | .type = PORT_SCIF, | 71 | .type = PORT_SCIF, |
75 | }; | 72 | }; |
76 | 73 | ||
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c index 940505cec66f..5eebbd7f4c21 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c | |||
@@ -21,7 +21,6 @@ | |||
21 | static struct plat_sci_port scif0_platform_data = { | 21 | static struct plat_sci_port scif0_platform_data = { |
22 | .flags = UPF_BOOT_AUTOCONF, | 22 | .flags = UPF_BOOT_AUTOCONF, |
23 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 23 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
24 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
25 | .type = PORT_SCIF, | 24 | .type = PORT_SCIF, |
26 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 25 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
27 | }; | 26 | }; |
@@ -44,7 +43,6 @@ static struct platform_device scif0_device = { | |||
44 | static struct plat_sci_port scif1_platform_data = { | 43 | static struct plat_sci_port scif1_platform_data = { |
45 | .flags = UPF_BOOT_AUTOCONF, | 44 | .flags = UPF_BOOT_AUTOCONF, |
46 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 45 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
47 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
48 | .type = PORT_SCIF, | 46 | .type = PORT_SCIF, |
49 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 47 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
50 | }; | 48 | }; |
@@ -67,7 +65,6 @@ static struct platform_device scif1_device = { | |||
67 | static struct plat_sci_port scif2_platform_data = { | 65 | static struct plat_sci_port scif2_platform_data = { |
68 | .flags = UPF_BOOT_AUTOCONF, | 66 | .flags = UPF_BOOT_AUTOCONF, |
69 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 67 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
70 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
71 | .type = PORT_SCIF, | 68 | .type = PORT_SCIF, |
72 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 69 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
73 | }; | 70 | }; |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c index f9c04dee4e82..e1ba8cb74e5a 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c | |||
@@ -18,7 +18,6 @@ | |||
18 | static struct plat_sci_port scif0_platform_data = { | 18 | static struct plat_sci_port scif0_platform_data = { |
19 | .flags = UPF_BOOT_AUTOCONF, | 19 | .flags = UPF_BOOT_AUTOCONF, |
20 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 20 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
21 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
22 | .type = PORT_SCIF, | 21 | .type = PORT_SCIF, |
23 | }; | 22 | }; |
24 | 23 | ||
@@ -40,7 +39,6 @@ static struct platform_device scif0_device = { | |||
40 | static struct plat_sci_port scif1_platform_data = { | 39 | static struct plat_sci_port scif1_platform_data = { |
41 | .flags = UPF_BOOT_AUTOCONF, | 40 | .flags = UPF_BOOT_AUTOCONF, |
42 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 41 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
43 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
44 | .type = PORT_SCIF, | 42 | .type = PORT_SCIF, |
45 | }; | 43 | }; |
46 | 44 | ||
@@ -62,7 +60,6 @@ static struct platform_device scif1_device = { | |||
62 | static struct plat_sci_port scif2_platform_data = { | 60 | static struct plat_sci_port scif2_platform_data = { |
63 | .flags = UPF_BOOT_AUTOCONF, | 61 | .flags = UPF_BOOT_AUTOCONF, |
64 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 62 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
65 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
66 | .type = PORT_SCIF, | 63 | .type = PORT_SCIF, |
67 | }; | 64 | }; |
68 | 65 | ||
@@ -84,7 +81,6 @@ static struct platform_device scif2_device = { | |||
84 | static struct plat_sci_port scif3_platform_data = { | 81 | static struct plat_sci_port scif3_platform_data = { |
85 | .flags = UPF_BOOT_AUTOCONF, | 82 | .flags = UPF_BOOT_AUTOCONF, |
86 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 83 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
87 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
88 | .type = PORT_SCIF, | 84 | .type = PORT_SCIF, |
89 | }; | 85 | }; |
90 | 86 | ||
@@ -106,7 +102,6 @@ static struct platform_device scif3_device = { | |||
106 | static struct plat_sci_port scif4_platform_data = { | 102 | static struct plat_sci_port scif4_platform_data = { |
107 | .flags = UPF_BOOT_AUTOCONF, | 103 | .flags = UPF_BOOT_AUTOCONF, |
108 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 104 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
109 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
110 | .type = PORT_SCIF, | 105 | .type = PORT_SCIF, |
111 | }; | 106 | }; |
112 | 107 | ||
@@ -128,7 +123,6 @@ static struct platform_device scif4_device = { | |||
128 | static struct plat_sci_port scif5_platform_data = { | 123 | static struct plat_sci_port scif5_platform_data = { |
129 | .flags = UPF_BOOT_AUTOCONF, | 124 | .flags = UPF_BOOT_AUTOCONF, |
130 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 125 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
131 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
132 | .type = PORT_SCIF, | 126 | .type = PORT_SCIF, |
133 | }; | 127 | }; |
134 | 128 | ||
@@ -150,7 +144,6 @@ static struct platform_device scif5_device = { | |||
150 | static struct plat_sci_port scif6_platform_data = { | 144 | static struct plat_sci_port scif6_platform_data = { |
151 | .flags = UPF_BOOT_AUTOCONF, | 145 | .flags = UPF_BOOT_AUTOCONF, |
152 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 146 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
153 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
154 | .type = PORT_SCIF, | 147 | .type = PORT_SCIF, |
155 | }; | 148 | }; |
156 | 149 | ||
@@ -172,7 +165,6 @@ static struct platform_device scif6_device = { | |||
172 | static struct plat_sci_port scif7_platform_data = { | 165 | static struct plat_sci_port scif7_platform_data = { |
173 | .flags = UPF_BOOT_AUTOCONF, | 166 | .flags = UPF_BOOT_AUTOCONF, |
174 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 167 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
175 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
176 | .type = PORT_SCIF, | 168 | .type = PORT_SCIF, |
177 | }; | 169 | }; |
178 | 170 | ||
@@ -194,7 +186,6 @@ static struct platform_device scif7_device = { | |||
194 | static struct plat_sci_port scif8_platform_data = { | 186 | static struct plat_sci_port scif8_platform_data = { |
195 | .flags = UPF_BOOT_AUTOCONF, | 187 | .flags = UPF_BOOT_AUTOCONF, |
196 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 188 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
197 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
198 | .type = PORT_SCIF, | 189 | .type = PORT_SCIF, |
199 | }; | 190 | }; |
200 | 191 | ||
@@ -216,7 +207,6 @@ static struct platform_device scif8_device = { | |||
216 | static struct plat_sci_port scif9_platform_data = { | 207 | static struct plat_sci_port scif9_platform_data = { |
217 | .flags = UPF_BOOT_AUTOCONF, | 208 | .flags = UPF_BOOT_AUTOCONF, |
218 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 209 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
219 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
220 | .type = PORT_SCIF, | 210 | .type = PORT_SCIF, |
221 | }; | 211 | }; |
222 | 212 | ||
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c index 227f8f4080fa..668e54bafa86 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c | |||
@@ -20,7 +20,6 @@ | |||
20 | static struct plat_sci_port scif0_platform_data = { | 20 | static struct plat_sci_port scif0_platform_data = { |
21 | .flags = UPF_BOOT_AUTOCONF, | 21 | .flags = UPF_BOOT_AUTOCONF, |
22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
23 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
24 | .type = PORT_SCIF, | 23 | .type = PORT_SCIF, |
25 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 24 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
26 | }; | 25 | }; |
@@ -43,7 +42,6 @@ static struct platform_device scif0_device = { | |||
43 | static struct plat_sci_port scif1_platform_data = { | 42 | static struct plat_sci_port scif1_platform_data = { |
44 | .flags = UPF_BOOT_AUTOCONF, | 43 | .flags = UPF_BOOT_AUTOCONF, |
45 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 44 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
46 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
47 | .type = PORT_SCIF, | 45 | .type = PORT_SCIF, |
48 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 46 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
49 | }; | 47 | }; |
@@ -419,9 +417,7 @@ void __init plat_early_device_setup(void) | |||
419 | { | 417 | { |
420 | if (mach_is_sh2007()) { | 418 | if (mach_is_sh2007()) { |
421 | scif0_platform_data.scscr &= ~SCSCR_CKE1; | 419 | scif0_platform_data.scscr &= ~SCSCR_CKE1; |
422 | scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2; | ||
423 | scif1_platform_data.scscr &= ~SCSCR_CKE1; | 420 | scif1_platform_data.scscr &= ~SCSCR_CKE1; |
424 | scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2; | ||
425 | } | 421 | } |
426 | 422 | ||
427 | early_platform_add_devices(sh7780_early_devices, | 423 | early_platform_add_devices(sh7780_early_devices, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index b9f64c1ee895..4aa679140209 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c | |||
@@ -22,7 +22,6 @@ | |||
22 | static struct plat_sci_port scif0_platform_data = { | 22 | static struct plat_sci_port scif0_platform_data = { |
23 | .flags = UPF_BOOT_AUTOCONF, | 23 | .flags = UPF_BOOT_AUTOCONF, |
24 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 24 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
25 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
26 | .type = PORT_SCIF, | 25 | .type = PORT_SCIF, |
27 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 26 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
28 | }; | 27 | }; |
@@ -45,7 +44,6 @@ static struct platform_device scif0_device = { | |||
45 | static struct plat_sci_port scif1_platform_data = { | 44 | static struct plat_sci_port scif1_platform_data = { |
46 | .flags = UPF_BOOT_AUTOCONF, | 45 | .flags = UPF_BOOT_AUTOCONF, |
47 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 46 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
48 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
49 | .type = PORT_SCIF, | 47 | .type = PORT_SCIF, |
50 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 48 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
51 | }; | 49 | }; |
@@ -68,7 +66,6 @@ static struct platform_device scif1_device = { | |||
68 | static struct plat_sci_port scif2_platform_data = { | 66 | static struct plat_sci_port scif2_platform_data = { |
69 | .flags = UPF_BOOT_AUTOCONF, | 67 | .flags = UPF_BOOT_AUTOCONF, |
70 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 68 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
71 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
72 | .type = PORT_SCIF, | 69 | .type = PORT_SCIF, |
73 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 70 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
74 | }; | 71 | }; |
@@ -91,7 +88,6 @@ static struct platform_device scif2_device = { | |||
91 | static struct plat_sci_port scif3_platform_data = { | 88 | static struct plat_sci_port scif3_platform_data = { |
92 | .flags = UPF_BOOT_AUTOCONF, | 89 | .flags = UPF_BOOT_AUTOCONF, |
93 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 90 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
94 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
95 | .type = PORT_SCIF, | 91 | .type = PORT_SCIF, |
96 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 92 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
97 | }; | 93 | }; |
@@ -114,7 +110,6 @@ static struct platform_device scif3_device = { | |||
114 | static struct plat_sci_port scif4_platform_data = { | 110 | static struct plat_sci_port scif4_platform_data = { |
115 | .flags = UPF_BOOT_AUTOCONF, | 111 | .flags = UPF_BOOT_AUTOCONF, |
116 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 112 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
117 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
118 | .type = PORT_SCIF, | 113 | .type = PORT_SCIF, |
119 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 114 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
120 | }; | 115 | }; |
@@ -137,7 +132,6 @@ static struct platform_device scif4_device = { | |||
137 | static struct plat_sci_port scif5_platform_data = { | 132 | static struct plat_sci_port scif5_platform_data = { |
138 | .flags = UPF_BOOT_AUTOCONF, | 133 | .flags = UPF_BOOT_AUTOCONF, |
139 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 134 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
140 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
141 | .type = PORT_SCIF, | 135 | .type = PORT_SCIF, |
142 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 136 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
143 | }; | 137 | }; |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index 92b95ceabd6e..5d619a551a3b 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c | |||
@@ -30,7 +30,6 @@ | |||
30 | static struct plat_sci_port scif0_platform_data = { | 30 | static struct plat_sci_port scif0_platform_data = { |
31 | .flags = UPF_BOOT_AUTOCONF, | 31 | .flags = UPF_BOOT_AUTOCONF, |
32 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 32 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
33 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
34 | .type = PORT_SCIF, | 33 | .type = PORT_SCIF, |
35 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 34 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
36 | }; | 35 | }; |
@@ -59,7 +58,6 @@ static struct platform_device scif0_device = { | |||
59 | static struct plat_sci_port scif1_platform_data = { | 58 | static struct plat_sci_port scif1_platform_data = { |
60 | .flags = UPF_BOOT_AUTOCONF, | 59 | .flags = UPF_BOOT_AUTOCONF, |
61 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 60 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
62 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
63 | .type = PORT_SCIF, | 61 | .type = PORT_SCIF, |
64 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 62 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
65 | }; | 63 | }; |
@@ -91,7 +89,6 @@ static struct platform_device scif1_device = { | |||
91 | static struct plat_sci_port scif2_platform_data = { | 89 | static struct plat_sci_port scif2_platform_data = { |
92 | .flags = UPF_BOOT_AUTOCONF, | 90 | .flags = UPF_BOOT_AUTOCONF, |
93 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 91 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
94 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
95 | .type = PORT_SCIF, | 92 | .type = PORT_SCIF, |
96 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 93 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
97 | }; | 94 | }; |
@@ -114,7 +111,6 @@ static struct platform_device scif2_device = { | |||
114 | static struct plat_sci_port scif3_platform_data = { | 111 | static struct plat_sci_port scif3_platform_data = { |
115 | .flags = UPF_BOOT_AUTOCONF, | 112 | .flags = UPF_BOOT_AUTOCONF, |
116 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 113 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
117 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
118 | .type = PORT_SCIF, | 114 | .type = PORT_SCIF, |
119 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 115 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
120 | }; | 116 | }; |
@@ -137,7 +133,6 @@ static struct platform_device scif3_device = { | |||
137 | static struct plat_sci_port scif4_platform_data = { | 133 | static struct plat_sci_port scif4_platform_data = { |
138 | .flags = UPF_BOOT_AUTOCONF, | 134 | .flags = UPF_BOOT_AUTOCONF, |
139 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 135 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
140 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
141 | .type = PORT_SCIF, | 136 | .type = PORT_SCIF, |
142 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 137 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
143 | }; | 138 | }; |
@@ -160,7 +155,6 @@ static struct platform_device scif4_device = { | |||
160 | static struct plat_sci_port scif5_platform_data = { | 155 | static struct plat_sci_port scif5_platform_data = { |
161 | .flags = UPF_BOOT_AUTOCONF, | 156 | .flags = UPF_BOOT_AUTOCONF, |
162 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 157 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
163 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
164 | .type = PORT_SCIF, | 158 | .type = PORT_SCIF, |
165 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 159 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
166 | }; | 160 | }; |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index 4d65be9be001..0856bcbb1da0 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c | |||
@@ -30,7 +30,6 @@ | |||
30 | static struct plat_sci_port scif0_platform_data = { | 30 | static struct plat_sci_port scif0_platform_data = { |
31 | .flags = UPF_BOOT_AUTOCONF, | 31 | .flags = UPF_BOOT_AUTOCONF, |
32 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 32 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
33 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
34 | .type = PORT_SCIF, | 33 | .type = PORT_SCIF, |
35 | }; | 34 | }; |
36 | 35 | ||
@@ -55,7 +54,6 @@ static struct platform_device scif0_device = { | |||
55 | static struct plat_sci_port scif1_platform_data = { | 54 | static struct plat_sci_port scif1_platform_data = { |
56 | .flags = UPF_BOOT_AUTOCONF, | 55 | .flags = UPF_BOOT_AUTOCONF, |
57 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 56 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
58 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
59 | .type = PORT_SCIF, | 57 | .type = PORT_SCIF, |
60 | }; | 58 | }; |
61 | 59 | ||
@@ -80,7 +78,6 @@ static struct platform_device scif1_device = { | |||
80 | static struct plat_sci_port scif2_platform_data = { | 78 | static struct plat_sci_port scif2_platform_data = { |
81 | .flags = UPF_BOOT_AUTOCONF, | 79 | .flags = UPF_BOOT_AUTOCONF, |
82 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 80 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
83 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
84 | .type = PORT_SCIF, | 81 | .type = PORT_SCIF, |
85 | }; | 82 | }; |
86 | 83 | ||
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c index 64b098162c98..14d68213d16b 100644 --- a/arch/sh/kernel/cpu/sh5/setup-sh5.c +++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c | |||
@@ -19,7 +19,6 @@ | |||
19 | static struct plat_sci_port scif0_platform_data = { | 19 | static struct plat_sci_port scif0_platform_data = { |
20 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | 20 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, |
21 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 21 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
22 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
23 | .type = PORT_SCIF, | 22 | .type = PORT_SCIF, |
24 | }; | 23 | }; |
25 | 24 | ||