MIPS: MT: Remove SMTC support

Nobody is maintaining SMTC anymore and there also seems to be no userbase.
Which is a pity - the SMTC technology primarily developed by Kevin D.
Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT
ASE's power and elegance.

Based on Markos Chandras <Markos.Chandras@imgtec.com> patch
https://patchwork.linux-mips.org/patch/6719/ which while very similar did
no longer apply cleanly when I tried to merge it plus some additional
post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to
merge once upon a time.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

6 files changed, 7 insertions, 132 deletions

diff --git a/arch/mips/pmcs-msp71xx/Makefile b/arch/mips/pmcs-msp71xx/Makefile
index 9201c8b3858d..d4f7220f2485 100644
--- a/arch/mips/pmcs-msp71xx/Makefile
+++ b/arch/mips/pmcs-msp71xx/Makefile
@@ -10,4 +10,3 @@ obj-$(CONFIG_PCI) += msp_pci.o
 obj-$(CONFIG_MSP_HAS_MAC) += msp_eth.o
 obj-$(CONFIG_MSP_HAS_USB) += msp_usb.o
 obj-$(CONFIG_MIPS_MT_SMP) += msp_smp.o
-obj-$(CONFIG_MIPS_MT_SMTC) += msp_smtc.o
diff --git a/arch/mips/pmcs-msp71xx/msp_irq.c b/arch/mips/pmcs-msp71xx/msp_irq.c
index 9da5619c00a5..941744aabb51 100644
--- a/arch/mips/pmcs-msp71xx/msp_irq.c
+++ b/arch/mips/pmcs-msp71xx/msp_irq.c
@@ -32,7 +32,7 @@ extern void msp_vsmp_int_init(void);
 
 /* vectored interrupt implementation */
 
-/* SW0/1 interrupts are used for SMP/SMTC */
+/* SW0/1 interrupts are used for SMP  */
 static inline void mac0_int_dispatch(void) { do_IRQ(MSP_INT_MAC0); }
 static inline void mac1_int_dispatch(void) { do_IRQ(MSP_INT_MAC1); }
 static inline void mac2_int_dispatch(void) { do_IRQ(MSP_INT_SAR); }
@@ -138,14 +138,6 @@ void __init arch_init_irq(void)
         set_vi_handler(MSP_INT_SEC, sec_int_dispatch);
 #ifdef CONFIG_MIPS_MT_SMP
         msp_vsmp_int_init();
-#elif defined CONFIG_MIPS_MT_SMTC
-        /*Set hwmask for all platform devices */
-        irq_hwmask[MSP_INT_MAC0] = C_IRQ0;
-        irq_hwmask[MSP_INT_MAC1] = C_IRQ1;
-        irq_hwmask[MSP_INT_USB] = C_IRQ2;
-        irq_hwmask[MSP_INT_SAR] = C_IRQ3;
-        irq_hwmask[MSP_INT_SEC] = C_IRQ5;
-
 #endif  /* CONFIG_MIPS_MT_SMP */
 #endif  /* CONFIG_MIPS_MT */
         /* setup the cascaded interrupts */
@@ -153,8 +145,10 @@ void __init arch_init_irq(void)
         setup_irq(MSP_INT_PER, &per_cascade_msp);
 
 #else
-        /* setup the 2nd-level SLP register based interrupt controller */
-        /* VSMP /SMTC support support is not enabled for SLP */
+        /*
+         * Setup the 2nd-level SLP register based interrupt controller.
+         * VSMP support support is not enabled for SLP.
+         */
         msp_slp_irq_init();
 
         /* setup the cascaded SLP/PER interrupts */
diff --git a/arch/mips/pmcs-msp71xx/msp_irq_cic.c b/arch/mips/pmcs-msp71xx/msp_irq_cic.c
index e49b499f66db..b8df2f7b3328 100644
--- a/arch/mips/pmcs-msp71xx/msp_irq_cic.c
+++ b/arch/mips/pmcs-msp71xx/msp_irq_cic.c
@@ -120,10 +120,9 @@ static void msp_cic_irq_ack(struct irq_data *d)
         * hurt for the others
         */
         *CIC_STS_REG = (1 << (d->irq - MSP_CIC_INTBASE));
-        smtc_im_ack_irq(d->irq);
 }
 
-/*Note: Limiting to VSMP . Not tested in SMTC */
+/* Note: Limiting to VSMP.  */
 
 #ifdef CONFIG_MIPS_MT_SMP
 static int msp_cic_irq_set_affinity(struct irq_data *d,
@@ -183,10 +182,6 @@ void __init msp_cic_irq_init(void)
         for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) {
                 irq_set_chip_and_handler(i, &msp_cic_irq_controller,
                                          handle_level_irq);
-#ifdef CONFIG_MIPS_MT_SMTC
-                /* Mask of CIC interrupt */
-                irq_hwmask[i] = C_IRQ4;
-#endif
         }
 
         /* Initialize the PER interrupt sub-system */
diff --git a/arch/mips/pmcs-msp71xx/msp_irq_per.c b/arch/mips/pmcs-msp71xx/msp_irq_per.c
index d1fd530479d4..a111836bcec2 100644
--- a/arch/mips/pmcs-msp71xx/msp_irq_per.c
+++ b/arch/mips/pmcs-msp71xx/msp_irq_per.c
@@ -113,9 +113,6 @@ void __init msp_per_irq_init(void)
         /* initialize all the IRQ descriptors */
         for (i = MSP_PER_INTBASE; i < MSP_PER_INTBASE + 32; i++) {
                 irq_set_chip(i, &msp_per_irq_controller);
-#ifdef CONFIG_MIPS_MT_SMTC
-                irq_hwmask[i] = C_IRQ4;
-#endif
         }
 }
 
diff --git a/arch/mips/pmcs-msp71xx/msp_setup.c b/arch/mips/pmcs-msp71xx/msp_setup.c
index ba9d518dc624..4f925e06c414 100644
--- a/arch/mips/pmcs-msp71xx/msp_setup.c
+++ b/arch/mips/pmcs-msp71xx/msp_setup.c
@@ -147,8 +147,6 @@ void __init plat_mem_setup(void)
         pm_power_off = msp_power_off;
 }
 
-extern struct plat_smp_ops msp_smtc_smp_ops;
-
 void __init prom_init(void)
 {
         unsigned long family;
@@ -229,9 +227,5 @@ void __init prom_init(void)
          */
         msp_serial_setup();
 
-        if (register_vsmp_smp_ops()) {
-#ifdef CONFIG_MIPS_MT_SMTC
-                register_smp_ops(&msp_smtc_smp_ops);
-#endif
-        }
+        register_vsmp_smp_ops();
 }
diff --git a/arch/mips/pmcs-msp71xx/msp_smtc.c b/arch/mips/pmcs-msp71xx/msp_smtc.c
deleted file mode 100644
index 6b5607fce279..000000000000
--- a/arch/mips/pmcs-msp71xx/msp_smtc.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * MSP71xx Platform-specific hooks for SMP operation
- */
-#include <linux/irq.h>
-#include <linux/init.h>
-
-#include <asm/mipsmtregs.h>
-#include <asm/mipsregs.h>
-#include <asm/smtc.h>
-#include <asm/smtc_ipi.h>
-
-/* VPE/SMP Prototype implements platform interfaces directly */
-
-/*
- * Cause the specified action to be performed on a targeted "CPU"
- */
-
-static void msp_smtc_send_ipi_single(int cpu, unsigned int action)
-{
-        /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
-        smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
-}
-
-static void msp_smtc_send_ipi_mask(const struct cpumask *mask,
-                                                unsigned int action)
-{
-        unsigned int i;
-
-        for_each_cpu(i, mask)
-                msp_smtc_send_ipi_single(i, action);
-}
-
-/*
- * Post-config but pre-boot cleanup entry point
- */
-static void msp_smtc_init_secondary(void)
-{
-        int myvpe;
-
-        /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
-        myvpe = read_c0_tcbind() & TCBIND_CURVPE;
-        if (myvpe > 0)
-                change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
-                                STATUSF_IP6 | STATUSF_IP7);
-        smtc_init_secondary();
-}
-
-/*
- * Platform "CPU" startup hook
- */
-static void msp_smtc_boot_secondary(int cpu, struct task_struct *idle)
-{
-        smtc_boot_secondary(cpu, idle);
-}
-
-/*
- * SMP initialization finalization entry point
- */
-static void msp_smtc_smp_finish(void)
-{
-        smtc_smp_finish();
-}
-
-/*
- * Hook for after all CPUs are online
- */
-
-static void msp_smtc_cpus_done(void)
-{
-}
-
-/*
- * Platform SMP pre-initialization
- *
- * As noted above, we can assume a single CPU for now
- * but it may be multithreaded.
- */
-
-static void __init msp_smtc_smp_setup(void)
-{
-        /*
-         * we won't get the definitive value until
-         * we've run smtc_prepare_cpus later, but
-         */
-
-        if (read_c0_config3() & (1 << 2))
-                smp_num_siblings = smtc_build_cpu_map(0);
-}
-
-static void __init msp_smtc_prepare_cpus(unsigned int max_cpus)
-{
-        smtc_prepare_cpus(max_cpus);
-}
-
-struct plat_smp_ops msp_smtc_smp_ops = {
-        .send_ipi_single        = msp_smtc_send_ipi_single,
-        .send_ipi_mask          = msp_smtc_send_ipi_mask,
-        .init_secondary         = msp_smtc_init_secondary,
-        .smp_finish             = msp_smtc_smp_finish,
-        .cpus_done              = msp_smtc_cpus_done,
-        .boot_secondary         = msp_smtc_boot_secondary,
-        .smp_setup              = msp_smtc_smp_setup,
-        .prepare_cpus           = msp_smtc_prepare_cpus,
-};