Merge tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Paul Burton:
 "A light batch this time around but significant improvements for
  certain systems:

   - Removal of readq & writeq for MIPS32 kernels where they would
     simply BUG() anyway, allowing drivers or other code that #ifdefs on
     their presence to work properly.

   - Improvements for Ingenic JZ4740 systems, including support for the
     external memory controller & pinmuxing fixes for qi_lb60/NanoNote
     systems.

   - Improvements for Lantiq systems, in particular around SMP & IPIs.

   - DT updates for ralink/MediaTek MT7628a systems to probe & configure
     a bunch more devices.

   - Miscellaneous cleanups & build fixes"

* tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits)
  MIPS: fix some more fall through errors in arch/mips
  MIPS: perf events: handle switch statement falling through warnings
  mips/kprobes: Export kprobe_fault_handler()
  MAINTAINERS: Add myself as Ingenic SoCs maintainer
  MIPS: ralink: mt7628a.dtsi: Add watchdog controller DT node
  MIPS: ralink: mt7628a.dtsi: Add SPI controller DT node
  MIPS: ralink: mt7628a.dtsi: Add GPIO controller DT node
  MIPS: ralink: mt7628a.dtsi: Add pinctrl DT properties to the UART nodes
  MIPS: ralink: mt7628a.dtsi: Add pinmux DT node
  MIPS: ralink: mt7628a.dtsi: Add SPDX GPL-2.0 license identifier
  MIPS: lantiq: Add SMP support for lantiq interrupt controller
  MIPS: lantiq: Shorten register names, remove unused macros
  MIPS: lantiq: Fix bitfield masking
  MIPS: lantiq: Remove unused macros
  MIPS: lantiq: Fix attributes of of_device_id structure
  MIPS: lantiq: Change variables to the same type as the source
  MIPS: lantiq: Move macro directly to iomem function
  mips: Remove q-accessors from non-64bit platforms
  FDDI: defza: Include linux/io-64-nonatomic-lo-hi.h
  MIPS: configs: Remove useless UEVENT_HELPER_PATH
  ...

2 files changed, 27 insertions, 26 deletions

diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index 4b5e1f2bfbce..2625232bfe52 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -333,20 +333,21 @@ void prepare_ftrace_return(unsigned long *parent_ra_addr, unsigned long self_ra,
                 return;
 
         /*
-         * "parent_ra_addr" is the stack address saved the return address of
-         * the caller of _mcount.
+         * "parent_ra_addr" is the stack address where the return address of
+         * the caller of _mcount is saved.
          *
-         * if the gcc < 4.5, a leaf function does not save the return address
-         * in the stack address, so, we "emulate" one in _mcount's stack space,
-         * and hijack it directly, but for a non-leaf function, it save the
-         * return address to the its own stack space, we can not hijack it
-         * directly, but need to find the real stack address,
-         * ftrace_get_parent_addr() does it!
+         * If gcc < 4.5, a leaf function does not save the return address
+         * in the stack address, so we "emulate" one in _mcount's stack space,
+         * and hijack it directly.
+         * For a non-leaf function, it does save the return address to its own
+         * stack space, so we can not hijack it directly, but need to find the
+         * real stack address, which is done by ftrace_get_parent_addr().
          *
-         * if gcc>= 4.5, with the new -mmcount-ra-address option, for a
+         * If gcc >= 4.5, with the new -mmcount-ra-address option, for a
          * non-leaf function, the location of the return address will be saved
-         * to $12 for us, and for a leaf function, only put a zero into $12. we
-         * do it in ftrace_graph_caller of mcount.S.
+         * to $12 for us.
+         * For a leaf function, it just puts a zero into $12, so we handle
+         * it in ftrace_graph_caller() of mcount.S.
          */
 
         /* old_parent_ra = *parent_ra_addr; */
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index e0ebaa0a333e..a3e2da8391ea 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -790,15 +790,19 @@ static void reset_counters(void *arg)
         case 4:
                 mipsxx_pmu_write_control(3, 0);
                 mipspmu.write_counter(3, 0);
+                /* fall through */
         case 3:
                 mipsxx_pmu_write_control(2, 0);
                 mipspmu.write_counter(2, 0);
+                /* fall through */
         case 2:
                 mipsxx_pmu_write_control(1, 0);
                 mipspmu.write_counter(1, 0);
+                /* fall through */
         case 1:
                 mipsxx_pmu_write_control(0, 0);
                 mipspmu.write_counter(0, 0);
+                /* fall through */
         }
 }
 
@@ -1380,7 +1384,7 @@ static int mipsxx_pmu_handle_shared_irq(void)
         struct perf_sample_data data;
         unsigned int counters = mipspmu.num_counters;
         u64 counter;
-        int handled = IRQ_NONE;
+        int n, handled = IRQ_NONE;
         struct pt_regs *regs;
 
         if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
@@ -1401,20 +1405,16 @@ static int mipsxx_pmu_handle_shared_irq(void)
 
         perf_sample_data_init(&data, 0, 0);
 
-        switch (counters) {
-#define HANDLE_COUNTER(n)                                               \
-        case n + 1:                                                     \
-                if (test_bit(n, cpuc->used_mask)) {                     \
-                        counter = mipspmu.read_counter(n);              \
-                        if (counter & mipspmu.overflow) {               \
-                                handle_associated_event(cpuc, n, &data, regs); \
-                                handled = IRQ_HANDLED;                  \
-                        }                                               \
-                }
-        HANDLE_COUNTER(3)
-        HANDLE_COUNTER(2)
-        HANDLE_COUNTER(1)
-        HANDLE_COUNTER(0)
+        for (n = counters - 1; n >= 0; n--) {
+                if (!test_bit(n, cpuc->used_mask))
+                        continue;
+
+                counter = mipspmu.read_counter(n);
+                if (!(counter & mipspmu.overflow))
+                        continue;
+
+                handle_associated_event(cpuc, n, &data, regs);
+                handled = IRQ_HANDLED;
         }
 
 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS