mips/atomic: Fix cmpxchg64 barriers

There were no memory barriers on the 32bit implementation of
cmpxchg64(). Fix this.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>

1 files changed, 5 insertions, 2 deletions

diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index f345a873742d..59cf5cbb3883 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -290,10 +290,13 @@ static inline unsigned long __cmpxchg64(volatile void *ptr,
          * will cause a build error unless cpu_has_64bits is a          \
          * compile-time constant 1.                                     \
          */                                                             \
-        if (cpu_has_64bits && kernel_uses_llsc)                         \
+        if (cpu_has_64bits && kernel_uses_llsc) {                       \
+                smp_mb__before_llsc();                                  \
                 __res = __cmpxchg64((ptr), __old, __new);               \
-        else                                                            \
+                smp_llsc_mb();                                          \
+        } else {                                                        \
                 __res = __cmpxchg64_unsupported();                      \
+        }                                                               \
                                                                         \
         __res;                                                          \
 })