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authorSonic Zhang <sonic.zhang@analog.com>2013-05-30 06:37:28 -0400
committerSteven Miao <realmz6@gmail.com>2013-11-15 04:33:42 -0500
commit54e4ff4d402450af5cec599f1cd9ab34997b3149 (patch)
tree2b4c53899c774b45fa37dbfc0440e459b2fdc16b /arch/blackfin
parent036c5df1839f709ed2018d4cd3bed1934eb26b83 (diff)
blackfin: adi gpio driver and pinctrl driver support
Remove gpio driver for new gpio controller on BF54x and BF60x. Build the bfin_gpio driver only when other BF5xx processors are selected. Replace the prefix of some gpio and peripheral functions with adi. add portmux platform data in machine portmux.h Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Steven Miao <realmz6@gmail.com>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/Kconfig8
-rw-r--r--arch/blackfin/include/asm/gpio.h157
-rw-r--r--arch/blackfin/include/asm/irq.h3
-rw-r--r--arch/blackfin/include/asm/irq_handler.h6
-rw-r--r--arch/blackfin/include/asm/portmux.h19
-rw-r--r--arch/blackfin/kernel/Makefile3
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c138
-rw-r--r--arch/blackfin/mach-bf548/Kconfig34
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c495
-rw-r--r--arch/blackfin/mach-bf548/include/mach/gpio.h8
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/portmux.h2
-rw-r--r--arch/blackfin/mach-bf609/Kconfig42
-rw-r--r--arch/blackfin/mach-bf609/boards/ezkit.c471
-rw-r--r--arch/blackfin/mach-bf609/include/mach/gpio.h8
-rw-r--r--arch/blackfin/mach-bf609/include/mach/irq.h2
-rw-r--r--arch/blackfin/mach-bf609/include/mach/portmux.h6
-rw-r--r--arch/blackfin/mach-common/ints-priority.c421
-rw-r--r--arch/blackfin/mach-common/pm.c15
19 files changed, 1044 insertions, 796 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index f78c9a2c7e28..c1ef4e2ed7b0 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -317,6 +317,14 @@ config BF53x
317 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) 317 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
318 default y 318 default y
319 319
320config GPIO_ADI
321 def_bool y
322 depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
323
324config PINCTRL
325 def_bool y
326 depends on BF54x || BF60x
327
320config MEM_MT48LC64M4A2FB_7E 328config MEM_MT48LC64M4A2FB_7E
321 bool 329 bool
322 depends on (BFIN533_STAMP) 330 depends on (BFIN533_STAMP)
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 98d0133346b5..99d338ca2ea4 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -25,8 +25,12 @@
25 25
26#ifndef __ASSEMBLY__ 26#ifndef __ASSEMBLY__
27 27
28#ifndef CONFIG_PINCTRL
29
28#include <linux/compiler.h> 30#include <linux/compiler.h>
29#include <linux/gpio.h> 31#include <asm/blackfin.h>
32#include <asm/portmux.h>
33#include <asm/irq_handler.h>
30 34
31/*********************************************************** 35/***********************************************************
32* 36*
@@ -45,7 +49,6 @@
45* MODIFICATION HISTORY : 49* MODIFICATION HISTORY :
46**************************************************************/ 50**************************************************************/
47 51
48#if !BFIN_GPIO_PINT
49void set_gpio_dir(unsigned, unsigned short); 52void set_gpio_dir(unsigned, unsigned short);
50void set_gpio_inen(unsigned, unsigned short); 53void set_gpio_inen(unsigned, unsigned short);
51void set_gpio_polar(unsigned, unsigned short); 54void set_gpio_polar(unsigned, unsigned short);
@@ -115,7 +118,6 @@ struct gpio_port_t {
115 unsigned short dummy16; 118 unsigned short dummy16;
116 unsigned short inen; 119 unsigned short inen;
117}; 120};
118#endif
119 121
120#ifdef BFIN_SPECIAL_GPIO_BANKS 122#ifdef BFIN_SPECIAL_GPIO_BANKS
121void bfin_special_gpio_free(unsigned gpio); 123void bfin_special_gpio_free(unsigned gpio);
@@ -127,25 +129,21 @@ void bfin_special_gpio_pm_hibernate_suspend(void);
127#endif 129#endif
128 130
129#ifdef CONFIG_PM 131#ifdef CONFIG_PM
130int bfin_pm_standby_ctrl(unsigned ctrl); 132void bfin_gpio_pm_hibernate_restore(void);
133void bfin_gpio_pm_hibernate_suspend(void);
134int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
135int bfin_gpio_pm_standby_ctrl(unsigned ctrl);
131 136
132static inline int bfin_pm_standby_setup(void) 137static inline int bfin_pm_standby_setup(void)
133{ 138{
134 return bfin_pm_standby_ctrl(1); 139 return bfin_gpio_pm_standby_ctrl(1);
135} 140}
136 141
137static inline void bfin_pm_standby_restore(void) 142static inline void bfin_pm_standby_restore(void)
138{ 143{
139 bfin_pm_standby_ctrl(0); 144 bfin_gpio_pm_standby_ctrl(0);
140} 145}
141 146
142void bfin_gpio_pm_hibernate_restore(void);
143void bfin_gpio_pm_hibernate_suspend(void);
144void bfin_pint_suspend(void);
145void bfin_pint_resume(void);
146
147# if !BFIN_GPIO_PINT
148int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
149 147
150struct gpio_port_s { 148struct gpio_port_s {
151 unsigned short data; 149 unsigned short data;
@@ -161,7 +159,6 @@ struct gpio_port_s {
161 unsigned short reserved; 159 unsigned short reserved;
162 unsigned short mux; 160 unsigned short mux;
163}; 161};
164# endif
165#endif /*CONFIG_PM*/ 162#endif /*CONFIG_PM*/
166 163
167/*********************************************************** 164/***********************************************************
@@ -178,36 +175,29 @@ struct gpio_port_s {
178************************************************************* 175*************************************************************
179* MODIFICATION HISTORY : 176* MODIFICATION HISTORY :
180**************************************************************/ 177**************************************************************/
181
182int bfin_gpio_request(unsigned gpio, const char *label);
183void bfin_gpio_free(unsigned gpio);
184int bfin_gpio_irq_request(unsigned gpio, const char *label); 178int bfin_gpio_irq_request(unsigned gpio, const char *label);
185void bfin_gpio_irq_free(unsigned gpio); 179void bfin_gpio_irq_free(unsigned gpio);
186int bfin_gpio_direction_input(unsigned gpio); 180void bfin_gpio_irq_prepare(unsigned gpio);
187int bfin_gpio_direction_output(unsigned gpio, int value); 181
188int bfin_gpio_get_value(unsigned gpio); 182static inline int irq_to_gpio(unsigned irq)
189void bfin_gpio_set_value(unsigned gpio, int value); 183{
184 return irq - GPIO_IRQ_BASE;
185}
186#endif /* CONFIG_PINCTRL */
190 187
191#include <asm/irq.h> 188#include <asm/irq.h>
192#include <asm/errno.h> 189#include <asm/errno.h>
193 190
194#ifdef CONFIG_GPIOLIB
195#include <asm-generic/gpio.h> /* cansleep wrappers */ 191#include <asm-generic/gpio.h> /* cansleep wrappers */
196 192
197static inline int gpio_get_value(unsigned int gpio) 193static inline int gpio_get_value(unsigned int gpio)
198{ 194{
199 if (gpio < MAX_BLACKFIN_GPIOS) 195 return __gpio_get_value(gpio);
200 return bfin_gpio_get_value(gpio);
201 else
202 return __gpio_get_value(gpio);
203} 196}
204 197
205static inline void gpio_set_value(unsigned int gpio, int value) 198static inline void gpio_set_value(unsigned int gpio, int value)
206{ 199{
207 if (gpio < MAX_BLACKFIN_GPIOS) 200 __gpio_set_value(gpio, value);
208 bfin_gpio_set_value(gpio, value);
209 else
210 __gpio_set_value(gpio, value);
211} 201}
212 202
213static inline int gpio_cansleep(unsigned int gpio) 203static inline int gpio_cansleep(unsigned int gpio)
@@ -219,113 +209,6 @@ static inline int gpio_to_irq(unsigned gpio)
219{ 209{
220 return __gpio_to_irq(gpio); 210 return __gpio_to_irq(gpio);
221} 211}
222
223#else /* !CONFIG_GPIOLIB */
224
225static inline int gpio_request(unsigned gpio, const char *label)
226{
227 return bfin_gpio_request(gpio, label);
228}
229
230static inline void gpio_free(unsigned gpio)
231{
232 return bfin_gpio_free(gpio);
233}
234
235static inline int gpio_direction_input(unsigned gpio)
236{
237 return bfin_gpio_direction_input(gpio);
238}
239
240static inline int gpio_direction_output(unsigned gpio, int value)
241{
242 return bfin_gpio_direction_output(gpio, value);
243}
244
245static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
246{
247 return -EINVAL;
248}
249
250static inline int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
251{
252 int err;
253
254 err = bfin_gpio_request(gpio, label);
255 if (err)
256 return err;
257
258 if (flags & GPIOF_DIR_IN)
259 err = bfin_gpio_direction_input(gpio);
260 else
261 err = bfin_gpio_direction_output(gpio,
262 (flags & GPIOF_INIT_HIGH) ? 1 : 0);
263
264 if (err)
265 bfin_gpio_free(gpio);
266
267 return err;
268}
269
270static inline int gpio_request_array(const struct gpio *array, size_t num)
271{
272 int i, err;
273
274 for (i = 0; i < num; i++, array++) {
275 err = gpio_request_one(array->gpio, array->flags, array->label);
276 if (err)
277 goto err_free;
278 }
279 return 0;
280
281err_free:
282 while (i--)
283 bfin_gpio_free((--array)->gpio);
284 return err;
285}
286
287static inline void gpio_free_array(const struct gpio *array, size_t num)
288{
289 while (num--)
290 bfin_gpio_free((array++)->gpio);
291}
292
293static inline int __gpio_get_value(unsigned gpio)
294{
295 return bfin_gpio_get_value(gpio);
296}
297
298static inline void __gpio_set_value(unsigned gpio, int value)
299{
300 return bfin_gpio_set_value(gpio, value);
301}
302
303static inline int gpio_get_value(unsigned gpio)
304{
305 return __gpio_get_value(gpio);
306}
307
308static inline void gpio_set_value(unsigned gpio, int value)
309{
310 return __gpio_set_value(gpio, value);
311}
312
313static inline int gpio_to_irq(unsigned gpio)
314{
315 if (likely(gpio < MAX_BLACKFIN_GPIOS))
316 return gpio + GPIO_IRQ_BASE;
317
318 return -EINVAL;
319}
320
321#include <asm-generic/gpio.h> /* cansleep wrappers */
322#endif /* !CONFIG_GPIOLIB */
323
324static inline int irq_to_gpio(unsigned irq)
325{
326 return (irq - GPIO_IRQ_BASE);
327}
328
329#endif /* __ASSEMBLY__ */ 212#endif /* __ASSEMBLY__ */
330 213
331#endif /* __ARCH_BLACKFIN_GPIO_H__ */ 214#endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 4ae1144a4578..2fd04f10cc26 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -23,8 +23,7 @@
23/* 23/*
24 * pm save bfin pint registers 24 * pm save bfin pint registers
25 */ 25 */
26struct bfin_pm_pint_save { 26struct adi_pm_pint_save {
27 u32 mask_set;
28 u32 assign; 27 u32 assign;
29 u32 edge_set; 28 u32 edge_set;
30 u32 invert_set; 29 u32 invert_set;
diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h
index 4fbf83575db1..4b2a992794d7 100644
--- a/arch/blackfin/include/asm/irq_handler.h
+++ b/arch/blackfin/include/asm/irq_handler.h
@@ -12,11 +12,11 @@
12#include <mach/irq.h> 12#include <mach/irq.h>
13 13
14/* init functions only */ 14/* init functions only */
15extern int __init init_arch_irq(void); 15extern int init_arch_irq(void);
16extern void init_exception_vectors(void); 16extern void init_exception_vectors(void);
17extern void __init program_IAR(void); 17extern void program_IAR(void);
18#ifdef init_mach_irq 18#ifdef init_mach_irq
19extern void __init init_mach_irq(void); 19extern void init_mach_irq(void);
20#else 20#else
21# define init_mach_irq() 21# define init_mach_irq()
22#endif 22#endif
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
index 9b1e2c37b324..7aa20436e799 100644
--- a/arch/blackfin/include/asm/portmux.h
+++ b/arch/blackfin/include/asm/portmux.h
@@ -17,14 +17,29 @@
17#define P_MAYSHARE 0x2000 17#define P_MAYSHARE 0x2000
18#define P_DONTCARE 0x1000 18#define P_DONTCARE 0x1000
19 19
20 20#ifdef CONFIG_PINCTRL
21#include <asm/irq_handler.h>
22
23#define gpio_pint_regs bfin_pint_regs
24#define adi_internal_set_wake bfin_internal_set_wake
25
26#define peripheral_request(per, label) 0
27#define peripheral_free(per)
28#define peripheral_request_list(per, label) \
29 (pdev ? (IS_ERR(devm_pinctrl_get_select_default(&pdev->dev)) \
30 ? -EINVAL : 0) : 0)
31#define peripheral_free_list(per)
32#else
21int peripheral_request(unsigned short per, const char *label); 33int peripheral_request(unsigned short per, const char *label);
22void peripheral_free(unsigned short per); 34void peripheral_free(unsigned short per);
23int peripheral_request_list(const unsigned short per[], const char *label); 35int peripheral_request_list(const unsigned short per[], const char *label);
24void peripheral_free_list(const unsigned short per[]); 36void peripheral_free_list(const unsigned short per[]);
37#endif
25 38
26#include <asm/gpio.h> 39#include <linux/err.h>
40#include <linux/pinctrl/pinctrl.h>
27#include <mach/portmux.h> 41#include <mach/portmux.h>
42#include <linux/gpio.h>
28 43
29#ifndef P_SPORT2_TFS 44#ifndef P_SPORT2_TFS
30#define P_SPORT2_TFS P_UNDEF 45#define P_SPORT2_TFS P_UNDEF
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 735f24e07425..703dc7cf2ecc 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -7,7 +7,7 @@ extra-y := vmlinux.lds
7obj-y := \ 7obj-y := \
8 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ 8 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
9 sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \ 9 sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \
10 fixed_code.o reboot.o bfin_gpio.o bfin_dma.o \ 10 fixed_code.o reboot.o bfin_dma.o \
11 exception.o dumpstack.o 11 exception.o dumpstack.o
12 12
13ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y) 13ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y)
@@ -16,6 +16,7 @@ else
16 obj-y += time.o 16 obj-y += time.o
17endif 17endif
18 18
19obj-$(CONFIG_GPIO_ADI) += bfin_gpio.o
19obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o 20obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
20obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o 21obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o
21obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o 22obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 780d27db1257..a017359c1826 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -11,11 +11,8 @@
11#include <linux/err.h> 11#include <linux/err.h>
12#include <linux/proc_fs.h> 12#include <linux/proc_fs.h>
13#include <linux/seq_file.h> 13#include <linux/seq_file.h>
14#include <asm/blackfin.h> 14#include <linux/gpio.h>
15#include <asm/gpio.h>
16#include <asm/portmux.h>
17#include <linux/irq.h> 15#include <linux/irq.h>
18#include <asm/irq_handler.h>
19 16
20#if ANOMALY_05000311 || ANOMALY_05000323 17#if ANOMALY_05000311 || ANOMALY_05000323
21enum { 18enum {
@@ -58,19 +55,6 @@ static struct gpio_port_t * const gpio_array[] = {
58 (struct gpio_port_t *) FIO0_FLAG_D, 55 (struct gpio_port_t *) FIO0_FLAG_D,
59 (struct gpio_port_t *) FIO1_FLAG_D, 56 (struct gpio_port_t *) FIO1_FLAG_D,
60 (struct gpio_port_t *) FIO2_FLAG_D, 57 (struct gpio_port_t *) FIO2_FLAG_D,
61#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
62 (struct gpio_port_t *)PORTA_FER,
63 (struct gpio_port_t *)PORTB_FER,
64 (struct gpio_port_t *)PORTC_FER,
65 (struct gpio_port_t *)PORTD_FER,
66 (struct gpio_port_t *)PORTE_FER,
67 (struct gpio_port_t *)PORTF_FER,
68 (struct gpio_port_t *)PORTG_FER,
69# if defined(CONFIG_BF54x)
70 (struct gpio_port_t *)PORTH_FER,
71 (struct gpio_port_t *)PORTI_FER,
72 (struct gpio_port_t *)PORTJ_FER,
73# endif
74#else 58#else
75# error no gpio arrays defined 59# error no gpio arrays defined
76#endif 60#endif
@@ -169,12 +153,6 @@ DECLARE_RESERVED_MAP(gpio_irq, GPIO_BANK_NUM);
169 153
170inline int check_gpio(unsigned gpio) 154inline int check_gpio(unsigned gpio)
171{ 155{
172#if defined(CONFIG_BF54x)
173 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
174 || gpio == GPIO_PH14 || gpio == GPIO_PH15
175 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
176 return -EINVAL;
177#endif
178 if (gpio >= MAX_BLACKFIN_GPIOS) 156 if (gpio >= MAX_BLACKFIN_GPIOS)
179 return -EINVAL; 157 return -EINVAL;
180 return 0; 158 return 0;
@@ -212,12 +190,6 @@ static void port_setup(unsigned gpio, unsigned short usage)
212 else 190 else
213 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); 191 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
214 SSYNC(); 192 SSYNC();
215#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
216 if (usage == GPIO_USAGE)
217 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
218 else
219 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
220 SSYNC();
221#endif 193#endif
222} 194}
223 195
@@ -306,31 +278,6 @@ static void portmux_setup(unsigned short per)
306 278
307 bfin_write_PORT_MUX(pmux); 279 bfin_write_PORT_MUX(pmux);
308} 280}
309#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
310inline void portmux_setup(unsigned short per)
311{
312 u16 ident = P_IDENT(per);
313 u16 function = P_FUNCT2MUX(per);
314 u32 pmux;
315
316 pmux = gpio_array[gpio_bank(ident)]->port_mux;
317
318 pmux &= ~(0x3 << (2 * gpio_sub_n(ident)));
319 pmux |= (function & 0x3) << (2 * gpio_sub_n(ident));
320
321 gpio_array[gpio_bank(ident)]->port_mux = pmux;
322}
323
324inline u16 get_portmux(unsigned short per)
325{
326 u16 ident = P_IDENT(per);
327 u32 pmux = gpio_array[gpio_bank(ident)]->port_mux;
328 return (pmux >> (2 * gpio_sub_n(ident)) & 0x3);
329}
330static int portmux_group_check(unsigned short per)
331{
332 return 0;
333}
334#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) 281#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
335static int portmux_group_check(unsigned short per) 282static int portmux_group_check(unsigned short per)
336{ 283{
@@ -384,7 +331,6 @@ static int portmux_group_check(unsigned short per)
384} 331}
385#endif 332#endif
386 333
387#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
388/*********************************************************** 334/***********************************************************
389* 335*
390* FUNCTIONS: Blackfin General Purpose Ports Access Functions 336* FUNCTIONS: Blackfin General Purpose Ports Access Functions
@@ -577,7 +523,7 @@ static const unsigned int sic_iwr_irqs[] = {
577************************************************************* 523*************************************************************
578* MODIFICATION HISTORY : 524* MODIFICATION HISTORY :
579**************************************************************/ 525**************************************************************/
580int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl) 526int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
581{ 527{
582 unsigned long flags; 528 unsigned long flags;
583 529
@@ -596,7 +542,7 @@ int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
596 return 0; 542 return 0;
597} 543}
598 544
599int bfin_pm_standby_ctrl(unsigned ctrl) 545int bfin_gpio_pm_standby_ctrl(unsigned ctrl)
600{ 546{
601 u16 bank, mask, i; 547 u16 bank, mask, i;
602 548
@@ -687,53 +633,6 @@ void bfin_gpio_pm_hibernate_restore(void)
687 633
688 634
689#endif 635#endif
690#else /* CONFIG_BF54x || CONFIG_BF60x */
691#ifdef CONFIG_PM
692
693int bfin_pm_standby_ctrl(unsigned ctrl)
694{
695 return 0;
696}
697
698void bfin_gpio_pm_hibernate_suspend(void)
699{
700 int i, bank;
701
702 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
703 bank = gpio_bank(i);
704
705 gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer;
706 gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux;
707 gpio_bank_saved[bank].data = gpio_array[bank]->data;
708 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
709 gpio_bank_saved[bank].dir = gpio_array[bank]->dir_set;
710 }
711}
712
713void bfin_gpio_pm_hibernate_restore(void)
714{
715 int i, bank;
716
717 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
718 bank = gpio_bank(i);
719
720 gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
721 gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
722 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
723 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
724 & gpio_bank_saved[bank].dir;
725 gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
726 }
727}
728#endif
729
730unsigned short get_gpio_dir(unsigned gpio)
731{
732 return (0x01 & (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio)));
733}
734EXPORT_SYMBOL(get_gpio_dir);
735
736#endif /* CONFIG_BF54x || CONFIG_BF60x */
737 636
738/*********************************************************** 637/***********************************************************
739* 638*
@@ -790,11 +689,7 @@ int peripheral_request(unsigned short per, const char *label)
790 * be requested and used by several drivers 689 * be requested and used by several drivers
791 */ 690 */
792 691
793#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
794 if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
795#else
796 if (!(per & P_MAYSHARE)) { 692 if (!(per & P_MAYSHARE)) {
797#endif
798 /* 693 /*
799 * Allow that the identical pin function can 694 * Allow that the identical pin function can
800 * be requested from the same driver twice 695 * be requested from the same driver twice
@@ -943,12 +838,9 @@ int bfin_gpio_request(unsigned gpio, const char *label)
943 if (unlikely(is_reserved(gpio_irq, gpio, 1))) { 838 if (unlikely(is_reserved(gpio_irq, gpio, 1))) {
944 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!" 839 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
945 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio); 840 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
946 } 841 } else { /* Reset POLAR setting when acquiring a gpio for the first time */
947#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
948 else { /* Reset POLAR setting when acquiring a gpio for the first time */
949 set_gpio_polar(gpio, 0); 842 set_gpio_polar(gpio, 0);
950 } 843 }
951#endif
952 844
953 reserve(gpio, gpio); 845 reserve(gpio, gpio);
954 set_label(gpio, label); 846 set_label(gpio, label);
@@ -1117,11 +1009,7 @@ void bfin_gpio_irq_free(unsigned gpio)
1117 1009
1118static inline void __bfin_gpio_direction_input(unsigned gpio) 1010static inline void __bfin_gpio_direction_input(unsigned gpio)
1119{ 1011{
1120#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1121 gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
1122#else
1123 gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio); 1012 gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1124#endif
1125 gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio); 1013 gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
1126} 1014}
1127 1015
@@ -1145,17 +1033,7 @@ EXPORT_SYMBOL(bfin_gpio_direction_input);
1145 1033
1146void bfin_gpio_irq_prepare(unsigned gpio) 1034void bfin_gpio_irq_prepare(unsigned gpio)
1147{ 1035{
1148#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1149 unsigned long flags;
1150#endif
1151
1152 port_setup(gpio, GPIO_USAGE); 1036 port_setup(gpio, GPIO_USAGE);
1153
1154#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1155 flags = hard_local_irq_save();
1156 __bfin_gpio_direction_input(gpio);
1157 hard_local_irq_restore(flags);
1158#endif
1159} 1037}
1160 1038
1161void bfin_gpio_set_value(unsigned gpio, int arg) 1039void bfin_gpio_set_value(unsigned gpio, int arg)
@@ -1180,11 +1058,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
1180 1058
1181 gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); 1059 gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1182 gpio_set_value(gpio, value); 1060 gpio_set_value(gpio, value);
1183#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1184 gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
1185#else
1186 gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio); 1061 gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
1187#endif
1188 1062
1189 AWA_DUMMY_READ(dir); 1063 AWA_DUMMY_READ(dir);
1190 hard_local_irq_restore(flags); 1064 hard_local_irq_restore(flags);
@@ -1195,9 +1069,6 @@ EXPORT_SYMBOL(bfin_gpio_direction_output);
1195 1069
1196int bfin_gpio_get_value(unsigned gpio) 1070int bfin_gpio_get_value(unsigned gpio)
1197{ 1071{
1198#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1199 return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
1200#else
1201 unsigned long flags; 1072 unsigned long flags;
1202 1073
1203 if (unlikely(get_gpio_edge(gpio))) { 1074 if (unlikely(get_gpio_edge(gpio))) {
@@ -1210,7 +1081,6 @@ int bfin_gpio_get_value(unsigned gpio)
1210 return ret; 1081 return ret;
1211 } else 1082 } else
1212 return get_gpio_data(gpio); 1083 return get_gpio_data(gpio);
1213#endif
1214} 1084}
1215EXPORT_SYMBOL(bfin_gpio_get_value); 1085EXPORT_SYMBOL(bfin_gpio_get_value);
1216 1086
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
index 94acb586832e..334ec7b12188 100644
--- a/arch/blackfin/mach-bf548/Kconfig
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -377,40 +377,6 @@ config IRQ_PINT3
377 377
378endmenu 378endmenu
379 379
380comment "Pin Interrupt to Port Assignment"
381menu "Assignment"
382
383config PINTx_REASSIGN
384 bool "Reprogram PINT Assignment"
385 default y
386 help
387 The interrupt assignment registers controls the pin-to-interrupt
388 assignment in a byte-wide manner. Each option allows you to select
389 a set of pins (High/Low Byte) of an specific Port being mapped
390 to one of the four PIN Interrupts IRQ_PINTx.
391
392 You shouldn't change any of these unless you know exactly what you're doing.
393 Please consult the Blackfin BF54x Processor Hardware Reference Manual.
394
395config PINT0_ASSIGN
396 hex "PINT0_ASSIGN"
397 depends on PINTx_REASSIGN
398 default 0x00000101
399config PINT1_ASSIGN
400 hex "PINT1_ASSIGN"
401 depends on PINTx_REASSIGN
402 default 0x01010000
403config PINT2_ASSIGN
404 hex "PINT2_ASSIGN"
405 depends on PINTx_REASSIGN
406 default 0x07000101
407config PINT3_ASSIGN
408 hex "PINT3_ASSIGN"
409 depends on PINTx_REASSIGN
410 default 0x02020303
411
412endmenu
413
414endmenu 380endmenu
415 381
416endif 382endif
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 372eb54944ef..984b3f9984cd 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -17,6 +17,9 @@
17#include <linux/i2c.h> 17#include <linux/i2c.h>
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/usb/musb.h> 19#include <linux/usb/musb.h>
20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinconf-generic.h>
22#include <linux/platform_data/pinctrl-adi2.h>
20#include <asm/bfin5xx_spi.h> 23#include <asm/bfin5xx_spi.h>
21#include <asm/dma.h> 24#include <asm/dma.h>
22#include <asm/gpio.h> 25#include <asm/gpio.h>
@@ -1058,6 +1061,411 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1058}; 1061};
1059#endif 1062#endif
1060 1063
1064#ifdef CONFIG_PINCTRL_ADI2
1065
1066# define ADI_PINT_DEVNAME "adi-gpio-pint"
1067# define ADI_GPIO_DEVNAME "adi-gpio"
1068# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
1069
1070static struct platform_device bfin_pinctrl_device = {
1071 .name = ADI_PINCTRL_DEVNAME,
1072 .id = 0,
1073};
1074
1075static struct resource bfin_pint0_resources[] = {
1076 {
1077 .start = PINT0_MASK_SET,
1078 .end = PINT0_LATCH + 3,
1079 .flags = IORESOURCE_MEM,
1080 },
1081 {
1082 .start = IRQ_PINT0,
1083 .end = IRQ_PINT0,
1084 .flags = IORESOURCE_IRQ,
1085 },
1086};
1087
1088static struct platform_device bfin_pint0_device = {
1089 .name = ADI_PINT_DEVNAME,
1090 .id = 0,
1091 .num_resources = ARRAY_SIZE(bfin_pint0_resources),
1092 .resource = bfin_pint0_resources,
1093};
1094
1095static struct resource bfin_pint1_resources[] = {
1096 {
1097 .start = PINT1_MASK_SET,
1098 .end = PINT1_LATCH + 3,
1099 .flags = IORESOURCE_MEM,
1100 },
1101 {
1102 .start = IRQ_PINT1,
1103 .end = IRQ_PINT1,
1104 .flags = IORESOURCE_IRQ,
1105 },
1106};
1107
1108static struct platform_device bfin_pint1_device = {
1109 .name = ADI_PINT_DEVNAME,
1110 .id = 1,
1111 .num_resources = ARRAY_SIZE(bfin_pint1_resources),
1112 .resource = bfin_pint1_resources,
1113};
1114
1115static struct resource bfin_pint2_resources[] = {
1116 {
1117 .start = PINT2_MASK_SET,
1118 .end = PINT2_LATCH + 3,
1119 .flags = IORESOURCE_MEM,
1120 },
1121 {
1122 .start = IRQ_PINT2,
1123 .end = IRQ_PINT2,
1124 .flags = IORESOURCE_IRQ,
1125 },
1126};
1127
1128static struct platform_device bfin_pint2_device = {
1129 .name = ADI_PINT_DEVNAME,
1130 .id = 2,
1131 .num_resources = ARRAY_SIZE(bfin_pint2_resources),
1132 .resource = bfin_pint2_resources,
1133};
1134
1135static struct resource bfin_pint3_resources[] = {
1136 {
1137 .start = PINT3_MASK_SET,
1138 .end = PINT3_LATCH + 3,
1139 .flags = IORESOURCE_MEM,
1140 },
1141 {
1142 .start = IRQ_PINT3,
1143 .end = IRQ_PINT3,
1144 .flags = IORESOURCE_IRQ,
1145 },
1146};
1147
1148static struct platform_device bfin_pint3_device = {
1149 .name = ADI_PINT_DEVNAME,
1150 .id = 3,
1151 .num_resources = ARRAY_SIZE(bfin_pint3_resources),
1152 .resource = bfin_pint3_resources,
1153};
1154
1155static struct resource bfin_gpa_resources[] = {
1156 {
1157 .start = PORTA_FER,
1158 .end = PORTA_MUX + 3,
1159 .flags = IORESOURCE_MEM,
1160 },
1161 { /* optional */
1162 .start = IRQ_PA0,
1163 .end = IRQ_PA0,
1164 .flags = IORESOURCE_IRQ,
1165 },
1166};
1167
1168static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
1169 .port_gpio_base = GPIO_PA0, /* Optional */
1170 .port_pin_base = GPIO_PA0,
1171 .port_width = GPIO_BANKSIZE,
1172 .pint_id = 0, /* PINT0 */
1173 .pint_assign = true, /* PINT upper 16 bit */
1174 .pint_map = 0, /* mapping mask in PINT */
1175};
1176
1177static struct platform_device bfin_gpa_device = {
1178 .name = ADI_GPIO_DEVNAME,
1179 .id = 0,
1180 .num_resources = ARRAY_SIZE(bfin_gpa_resources),
1181 .resource = bfin_gpa_resources,
1182 .dev = {
1183 .platform_data = &bfin_gpa_pdata, /* Passed to driver */
1184 },
1185};
1186
1187static struct resource bfin_gpb_resources[] = {
1188 {
1189 .start = PORTB_FER,
1190 .end = PORTB_MUX + 3,
1191 .flags = IORESOURCE_MEM,
1192 },
1193 {
1194 .start = IRQ_PB0,
1195 .end = IRQ_PB0,
1196 .flags = IORESOURCE_IRQ,
1197 },
1198};
1199
1200static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
1201 .port_gpio_base = GPIO_PB0,
1202 .port_pin_base = GPIO_PB0,
1203 .port_width = 15,
1204 .pint_id = 0,
1205 .pint_assign = true,
1206 .pint_map = 1,
1207};
1208
1209static struct platform_device bfin_gpb_device = {
1210 .name = ADI_GPIO_DEVNAME,
1211 .id = 1,
1212 .num_resources = ARRAY_SIZE(bfin_gpb_resources),
1213 .resource = bfin_gpb_resources,
1214 .dev = {
1215 .platform_data = &bfin_gpb_pdata, /* Passed to driver */
1216 },
1217};
1218
1219static struct resource bfin_gpc_resources[] = {
1220 {
1221 .start = PORTC_FER,
1222 .end = PORTC_MUX + 3,
1223 .flags = IORESOURCE_MEM,
1224 },
1225 {
1226 .start = IRQ_PC0,
1227 .end = IRQ_PC0,
1228 .flags = IORESOURCE_IRQ,
1229 },
1230};
1231
1232static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
1233 .port_gpio_base = GPIO_PC0,
1234 .port_pin_base = GPIO_PC0,
1235 .port_width = 14,
1236 .pint_id = 2,
1237 .pint_assign = true,
1238 .pint_map = 0,
1239};
1240
1241static struct platform_device bfin_gpc_device = {
1242 .name = ADI_GPIO_DEVNAME,
1243 .id = 2,
1244 .num_resources = ARRAY_SIZE(bfin_gpc_resources),
1245 .resource = bfin_gpc_resources,
1246 .dev = {
1247 .platform_data = &bfin_gpc_pdata, /* Passed to driver */
1248 },
1249};
1250
1251static struct resource bfin_gpd_resources[] = {
1252 {
1253 .start = PORTD_FER,
1254 .end = PORTD_MUX + 3,
1255 .flags = IORESOURCE_MEM,
1256 },
1257 {
1258 .start = IRQ_PD0,
1259 .end = IRQ_PD0,
1260 .flags = IORESOURCE_IRQ,
1261 },
1262};
1263
1264static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
1265 .port_gpio_base = GPIO_PD0,
1266 .port_pin_base = GPIO_PD0,
1267 .port_width = GPIO_BANKSIZE,
1268 .pint_id = 2,
1269 .pint_assign = false,
1270 .pint_map = 1,
1271};
1272
1273static struct platform_device bfin_gpd_device = {
1274 .name = ADI_GPIO_DEVNAME,
1275 .id = 3,
1276 .num_resources = ARRAY_SIZE(bfin_gpd_resources),
1277 .resource = bfin_gpd_resources,
1278 .dev = {
1279 .platform_data = &bfin_gpd_pdata, /* Passed to driver */
1280 },
1281};
1282
1283static struct resource bfin_gpe_resources[] = {
1284 {
1285 .start = PORTE_FER,
1286 .end = PORTE_MUX + 3,
1287 .flags = IORESOURCE_MEM,
1288 },
1289 {
1290 .start = IRQ_PE0,
1291 .end = IRQ_PE0,
1292 .flags = IORESOURCE_IRQ,
1293 },
1294};
1295
1296static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
1297 .port_gpio_base = GPIO_PE0,
1298 .port_pin_base = GPIO_PE0,
1299 .port_width = GPIO_BANKSIZE,
1300 .pint_id = 3,
1301 .pint_assign = true,
1302 .pint_map = 2,
1303};
1304
1305static struct platform_device bfin_gpe_device = {
1306 .name = ADI_GPIO_DEVNAME,
1307 .id = 4,
1308 .num_resources = ARRAY_SIZE(bfin_gpe_resources),
1309 .resource = bfin_gpe_resources,
1310 .dev = {
1311 .platform_data = &bfin_gpe_pdata, /* Passed to driver */
1312 },
1313};
1314
1315static struct resource bfin_gpf_resources[] = {
1316 {
1317 .start = PORTF_FER,
1318 .end = PORTF_MUX + 3,
1319 .flags = IORESOURCE_MEM,
1320 },
1321 {
1322 .start = IRQ_PF0,
1323 .end = IRQ_PF0,
1324 .flags = IORESOURCE_IRQ,
1325 },
1326};
1327
1328static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
1329 .port_gpio_base = GPIO_PF0,
1330 .port_pin_base = GPIO_PF0,
1331 .port_width = GPIO_BANKSIZE,
1332 .pint_id = 3,
1333 .pint_assign = false,
1334 .pint_map = 3,
1335};
1336
1337static struct platform_device bfin_gpf_device = {
1338 .name = ADI_GPIO_DEVNAME,
1339 .id = 5,
1340 .num_resources = ARRAY_SIZE(bfin_gpf_resources),
1341 .resource = bfin_gpf_resources,
1342 .dev = {
1343 .platform_data = &bfin_gpf_pdata, /* Passed to driver */
1344 },
1345};
1346
1347static struct resource bfin_gpg_resources[] = {
1348 {
1349 .start = PORTG_FER,
1350 .end = PORTG_MUX + 3,
1351 .flags = IORESOURCE_MEM,
1352 },
1353 {
1354 .start = IRQ_PG0,
1355 .end = IRQ_PG0,
1356 .flags = IORESOURCE_IRQ,
1357 },
1358};
1359
1360static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
1361 .port_gpio_base = GPIO_PG0,
1362 .port_pin_base = GPIO_PG0,
1363 .port_width = GPIO_BANKSIZE,
1364 .pint_id = -1,
1365};
1366
1367static struct platform_device bfin_gpg_device = {
1368 .name = ADI_GPIO_DEVNAME,
1369 .id = 6,
1370 .num_resources = ARRAY_SIZE(bfin_gpg_resources),
1371 .resource = bfin_gpg_resources,
1372 .dev = {
1373 .platform_data = &bfin_gpg_pdata, /* Passed to driver */
1374 },
1375};
1376
1377static struct resource bfin_gph_resources[] = {
1378 {
1379 .start = PORTH_FER,
1380 .end = PORTH_MUX + 3,
1381 .flags = IORESOURCE_MEM,
1382 },
1383 {
1384 .start = IRQ_PH0,
1385 .end = IRQ_PH0,
1386 .flags = IORESOURCE_IRQ,
1387 },
1388};
1389
1390static struct adi_pinctrl_gpio_platform_data bfin_gph_pdata = {
1391 .port_gpio_base = GPIO_PH0,
1392 .port_pin_base = GPIO_PH0,
1393 .port_width = 14,
1394 .pint_id = -1,
1395};
1396
1397static struct platform_device bfin_gph_device = {
1398 .name = ADI_GPIO_DEVNAME,
1399 .id = 7,
1400 .num_resources = ARRAY_SIZE(bfin_gph_resources),
1401 .resource = bfin_gph_resources,
1402 .dev = {
1403 .platform_data = &bfin_gph_pdata, /* Passed to driver */
1404 },
1405};
1406
1407static struct resource bfin_gpi_resources[] = {
1408 {
1409 .start = PORTI_FER,
1410 .end = PORTI_MUX + 3,
1411 .flags = IORESOURCE_MEM,
1412 },
1413 {
1414 .start = IRQ_PI0,
1415 .end = IRQ_PI0,
1416 .flags = IORESOURCE_IRQ,
1417 },
1418};
1419
1420static struct adi_pinctrl_gpio_platform_data bfin_gpi_pdata = {
1421 .port_gpio_base = GPIO_PI0,
1422 .port_pin_base = GPIO_PI0,
1423 .port_width = GPIO_BANKSIZE,
1424 .pint_id = -1,
1425};
1426
1427static struct platform_device bfin_gpi_device = {
1428 .name = ADI_GPIO_DEVNAME,
1429 .id = 8,
1430 .num_resources = ARRAY_SIZE(bfin_gpi_resources),
1431 .resource = bfin_gpi_resources,
1432 .dev = {
1433 .platform_data = &bfin_gpi_pdata, /* Passed to driver */
1434 },
1435};
1436
1437static struct resource bfin_gpj_resources[] = {
1438 {
1439 .start = PORTJ_FER,
1440 .end = PORTJ_MUX + 3,
1441 .flags = IORESOURCE_MEM,
1442 },
1443 {
1444 .start = IRQ_PJ0,
1445 .end = IRQ_PJ0,
1446 .flags = IORESOURCE_IRQ,
1447 },
1448};
1449
1450static struct adi_pinctrl_gpio_platform_data bfin_gpj_pdata = {
1451 .port_gpio_base = GPIO_PJ0,
1452 .port_pin_base = GPIO_PJ0,
1453 .port_width = 14,
1454 .pint_id = -1,
1455};
1456
1457static struct platform_device bfin_gpj_device = {
1458 .name = ADI_GPIO_DEVNAME,
1459 .id = 9,
1460 .num_resources = ARRAY_SIZE(bfin_gpj_resources),
1461 .resource = bfin_gpj_resources,
1462 .dev = {
1463 .platform_data = &bfin_gpj_pdata, /* Passed to driver */
1464 },
1465};
1466
1467#endif
1468
1061static struct spi_board_info bfin_spi_board_info[] __initdata = { 1469static struct spi_board_info bfin_spi_board_info[] __initdata = {
1062#if defined(CONFIG_MTD_M25P80) \ 1470#if defined(CONFIG_MTD_M25P80) \
1063 || defined(CONFIG_MTD_M25P80_MODULE) 1471 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -1066,7 +1474,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1066 .modalias = "m25p80", /* Name of spi_driver for this device */ 1474 .modalias = "m25p80", /* Name of spi_driver for this device */
1067 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 1475 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1068 .bus_num = 0, /* Framework bus number */ 1476 .bus_num = 0, /* Framework bus number */
1069 .chip_select = 1, /* SPI_SSEL1*/ 1477 .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1*/
1070 .platform_data = &bfin_spi_flash_data, 1478 .platform_data = &bfin_spi_flash_data,
1071 .controller_data = &spi_flash_chip_info, 1479 .controller_data = &spi_flash_chip_info,
1072 .mode = SPI_MODE_3, 1480 .mode = SPI_MODE_3,
@@ -1078,7 +1486,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1078 .modalias = "ad183x", 1486 .modalias = "ad183x",
1079 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 1487 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1080 .bus_num = 1, 1488 .bus_num = 1,
1081 .chip_select = 4, 1489 .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
1082 }, 1490 },
1083#endif 1491#endif
1084#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 1492#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
@@ -1088,7 +1496,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1088 .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */ 1496 .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
1089 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 1497 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1090 .bus_num = 0, 1498 .bus_num = 0,
1091 .chip_select = 2, 1499 .chip_select = MAX_CTRL_CS + GPIO_PE5, /* SPI_SSEL2 */
1092 }, 1500 },
1093#endif 1501#endif
1094#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) 1502#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -1096,7 +1504,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1096 .modalias = "spidev", 1504 .modalias = "spidev",
1097 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 1505 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1098 .bus_num = 0, 1506 .bus_num = 0,
1099 .chip_select = 1, 1507 .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1 */
1100 }, 1508 },
1101#endif 1509#endif
1102#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE) 1510#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
@@ -1106,7 +1514,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1106 .irq = IRQ_PC5, 1514 .irq = IRQ_PC5,
1107 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 1515 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1108 .bus_num = 1, 1516 .bus_num = 1,
1109 .chip_select = 2, 1517 .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
1110 .mode = SPI_MODE_3, 1518 .mode = SPI_MODE_3,
1111 }, 1519 },
1112#endif 1520#endif
@@ -1152,7 +1560,7 @@ static struct resource bfin_spi1_resource[] = {
1152 1560
1153/* SPI controller data */ 1561/* SPI controller data */
1154static struct bfin5xx_spi_master bf54x_spi_master_info0 = { 1562static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
1155 .num_chipselect = 4, 1563 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1156 .enable_dma = 1, /* master has the ability to do dma transfer */ 1564 .enable_dma = 1, /* master has the ability to do dma transfer */
1157 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, 1565 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1158}; 1566};
@@ -1168,7 +1576,7 @@ static struct platform_device bf54x_spi_master0 = {
1168}; 1576};
1169 1577
1170static struct bfin5xx_spi_master bf54x_spi_master_info1 = { 1578static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
1171 .num_chipselect = 4, 1579 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1172 .enable_dma = 1, /* master has the ability to do dma transfer */ 1580 .enable_dma = 1, /* master has the ability to do dma transfer */
1173 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, 1581 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1174}; 1582};
@@ -1508,6 +1916,23 @@ static struct platform_device bfin_ac97 = {
1508static struct platform_device *ezkit_devices[] __initdata = { 1916static struct platform_device *ezkit_devices[] __initdata = {
1509 1917
1510 &bfin_dpmc, 1918 &bfin_dpmc,
1919#if defined(CONFIG_PINCTRL_ADI2)
1920 &bfin_pinctrl_device,
1921 &bfin_pint0_device,
1922 &bfin_pint1_device,
1923 &bfin_pint2_device,
1924 &bfin_pint3_device,
1925 &bfin_gpa_device,
1926 &bfin_gpb_device,
1927 &bfin_gpc_device,
1928 &bfin_gpd_device,
1929 &bfin_gpe_device,
1930 &bfin_gpf_device,
1931 &bfin_gpg_device,
1932 &bfin_gph_device,
1933 &bfin_gpi_device,
1934 &bfin_gpj_device,
1935#endif
1511 1936
1512#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 1937#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1513 &rtc_device, 1938 &rtc_device,
@@ -1644,10 +2069,66 @@ static struct platform_device *ezkit_devices[] __initdata = {
1644#endif 2069#endif
1645}; 2070};
1646 2071
2072/* Pin control settings */
2073static struct pinctrl_map __initdata bfin_pinmux_map[] = {
2074 /* per-device maps */
2075 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
2076 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
2077#ifdef CONFIG_BFIN_UART1_CTSRTS
2078 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1_ctsrts"),
2079#endif
2080 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.2", "pinctrl-adi2.0", NULL, "uart2"),
2081 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3"),
2082#ifdef CONFIG_BFIN_UART3_CTSRTS
2083 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3_ctsrts"),
2084#endif
2085 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
2086 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
2087 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.2", "pinctrl-adi2.0", NULL, "uart2"),
2088 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.3", "pinctrl-adi2.0", NULL, "uart3"),
2089 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
2090 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.0", "pinctrl-adi2.0", NULL, "spi0"),
2091 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.1", "pinctrl-adi2.0", NULL, "spi1"),
2092 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
2093#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
2094 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
2095#endif
2096 PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
2097 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
2098 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.1", "pinctrl-adi2.0", NULL, "can1"),
2099 PIN_MAP_MUX_GROUP_DEFAULT("bf54x-lq043", "pinctrl-adi2.0", NULL, "ppi0_24b"),
2100 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
2101 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
2102 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.0", "pinctrl-adi2.0", NULL, "sport0"),
2103 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
2104 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
2105 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.1", "pinctrl-adi2.0", NULL, "sport1"),
2106 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
2107 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
2108 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.2", "pinctrl-adi2.0", NULL, "sport2"),
2109 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.3", "pinctrl-adi2.0", NULL, "sport3"),
2110 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.3", "pinctrl-adi2.0", NULL, "sport3"),
2111 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.3", "pinctrl-adi2.0", NULL, "sport3"),
2112 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.0", "pinctrl-adi2.0", NULL, "sport0"),
2113 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.1", "pinctrl-adi2.0", NULL, "sport1"),
2114 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.2", "pinctrl-adi2.0", NULL, "sport2"),
2115 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.3", "pinctrl-adi2.0", NULL, "sport3"),
2116 PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi"),
2117#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
2118 PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi_alter"),
2119#endif
2120 PIN_MAP_MUX_GROUP_DEFAULT("bf5xx-nand.0", "pinctrl-adi2.0", NULL, "nfc0"),
2121 PIN_MAP_MUX_GROUP_DEFAULT("bf54x-keys", "pinctrl-adi2.0", NULL, "keys_4x4"),
2122};
2123
1647static int __init ezkit_init(void) 2124static int __init ezkit_init(void)
1648{ 2125{
1649 printk(KERN_INFO "%s(): registering device resources\n", __func__); 2126 printk(KERN_INFO "%s(): registering device resources\n", __func__);
1650 2127
2128 /* Initialize pinmuxing */
2129 pinctrl_register_mappings(bfin_pinmux_map,
2130 ARRAY_SIZE(bfin_pinmux_map));
2131
1651 i2c_register_board_info(0, bfin_i2c_board_info0, 2132 i2c_register_board_info(0, bfin_i2c_board_info0,
1652 ARRAY_SIZE(bfin_i2c_board_info0)); 2133 ARRAY_SIZE(bfin_i2c_board_info0));
1653#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ 2134#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
index be9edb28f96b..006da1edcf84 100644
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf548/include/mach/gpio.h
@@ -194,14 +194,6 @@ struct gpio_port_t {
194 unsigned int port_mux; 194 unsigned int port_mux;
195}; 195};
196 196
197struct gpio_port_s {
198 unsigned short fer;
199 unsigned short data;
200 unsigned short dir;
201 unsigned short inen;
202 unsigned int mux;
203};
204
205#endif 197#endif
206 198
207#include <mach-common/ports-a.h> 199#include <mach-common/ports-a.h>
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 10dc142c518d..cf7cb725cfa2 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -433,7 +433,7 @@
433#include <linux/types.h> 433#include <linux/types.h>
434 434
435/* 435/*
436 * bfin pint registers layout 436 * gpio pint registers layout
437 */ 437 */
438struct bfin_pint_regs { 438struct bfin_pint_regs {
439 u32 mask_set; 439 u32 mask_set;
diff --git a/arch/blackfin/mach-bf548/include/mach/portmux.h b/arch/blackfin/mach-bf548/include/mach/portmux.h
index e22246202730..d9f8632d7d09 100644
--- a/arch/blackfin/mach-bf548/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf548/include/mach/portmux.h
@@ -7,8 +7,6 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
11
12#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) 10#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
13#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) 11#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
14#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) 12#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig
index 2bcbf94b1edf..b0fca44110b0 100644
--- a/arch/blackfin/mach-bf609/Kconfig
+++ b/arch/blackfin/mach-bf609/Kconfig
@@ -9,48 +9,6 @@ source "arch/blackfin/mach-bf609/boards/Kconfig"
9 9
10menu "BF609 Specific Configuration" 10menu "BF609 Specific Configuration"
11 11
12comment "Pin Interrupt to Port Assignment"
13menu "Assignment"
14
15config PINTx_REASSIGN
16 bool "Reprogram PINT Assignment"
17 default y
18 help
19 The interrupt assignment registers controls the pin-to-interrupt
20 assignment in a byte-wide manner. Each option allows you to select
21 a set of pins (High/Low Byte) of an specific Port being mapped
22 to one of the four PIN Interrupts IRQ_PINTx.
23
24 You shouldn't change any of these unless you know exactly what you're doing.
25 Please consult the Blackfin BF60x Processor Hardware Reference Manual.
26
27config PINT0_ASSIGN
28 hex "PINT0_ASSIGN"
29 depends on PINTx_REASSIGN
30 default 0x00000101
31config PINT1_ASSIGN
32 hex "PINT1_ASSIGN"
33 depends on PINTx_REASSIGN
34 default 0x00000101
35config PINT2_ASSIGN
36 hex "PINT2_ASSIGN"
37 depends on PINTx_REASSIGN
38 default 0x00000101
39config PINT3_ASSIGN
40 hex "PINT3_ASSIGN"
41 depends on PINTx_REASSIGN
42 default 0x00000101
43config PINT4_ASSIGN
44 hex "PINT3_ASSIGN"
45 depends on PINTx_REASSIGN
46 default 0x00000101
47config PINT5_ASSIGN
48 hex "PINT3_ASSIGN"
49 depends on PINTx_REASSIGN
50 default 0x00000101
51
52endmenu
53
54config SEC_IRQ_PRIORITY_LEVELS 12config SEC_IRQ_PRIORITY_LEVELS
55 int "SEC interrupt priority levels" 13 int "SEC interrupt priority levels"
56 default 7 14 default 7
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
index d56a55ad83a7..9da44b360426 100644
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ b/arch/blackfin/mach-bf609/boards/ezkit.c
@@ -17,6 +17,9 @@
17#include <linux/i2c.h> 17#include <linux/i2c.h>
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/usb/musb.h> 19#include <linux/usb/musb.h>
20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinconf-generic.h>
22#include <linux/platform_data/pinctrl-adi2.h>
20#include <asm/bfin_spi3.h> 23#include <asm/bfin_spi3.h>
21#include <asm/dma.h> 24#include <asm/dma.h>
22#include <asm/gpio.h> 25#include <asm/gpio.h>
@@ -106,8 +109,6 @@ static struct platform_device bfin_rotary_device = {
106#include <linux/stmmac.h> 109#include <linux/stmmac.h>
107#include <linux/phy.h> 110#include <linux/phy.h>
108 111
109static unsigned short pins[] = P_RMII0;
110
111static struct stmmac_mdio_bus_data phy_private_data = { 112static struct stmmac_mdio_bus_data phy_private_data = {
112 .phy_mask = 1, 113 .phy_mask = 1,
113}; 114};
@@ -674,7 +675,7 @@ static struct mtd_partition ezkit_partitions[] = {
674 }, 675 },
675}; 676};
676 677
677int bf609_nor_flash_init(struct platform_device *dev) 678int bf609_nor_flash_init(struct platform_device *pdev)
678{ 679{
679#define CONFIG_SMC_GCTL_VAL 0x00000010 680#define CONFIG_SMC_GCTL_VAL 0x00000010
680 const unsigned short pins[] = { 681 const unsigned short pins[] = {
@@ -1319,6 +1320,367 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1319}; 1320};
1320#endif 1321#endif
1321 1322
1323#ifdef CONFIG_PINCTRL_ADI2
1324
1325# define ADI_PINT_DEVNAME "adi-gpio-pint"
1326# define ADI_GPIO_DEVNAME "adi-gpio"
1327# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
1328
1329static struct platform_device bfin_pinctrl_device = {
1330 .name = ADI_PINCTRL_DEVNAME,
1331 .id = 0,
1332};
1333
1334#ifdef CONFIG_PINCTRL_ADI2
1335
1336# define ADI_PINT_DEVNAME "adi-gpio-pint"
1337# define ADI_GPIO_DEVNAME "adi-gpio"
1338# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
1339
1340static struct platform_device bfin_pinctrl_device = {
1341 .name = ADI_PINCTRL_DEVNAME,
1342 .id = 0,
1343};
1344
1345static struct resource bfin_pint0_resources[] = {
1346 {
1347 .start = PINT0_MASK_SET,
1348 .end = PINT0_LATCH + 3,
1349 .flags = IORESOURCE_MEM,
1350 },
1351 {
1352 .start = IRQ_PINT0,
1353 .end = IRQ_PINT0,
1354 .flags = IORESOURCE_IRQ,
1355 },
1356};
1357
1358static struct platform_device bfin_pint0_device = {
1359 .name = ADI_PINT_DEVNAME,
1360 .id = 0,
1361 .num_resources = ARRAY_SIZE(bfin_pint0_resources),
1362 .resource = bfin_pint0_resources,
1363};
1364
1365static struct resource bfin_pint1_resources[] = {
1366 {
1367 .start = PINT1_MASK_SET,
1368 .end = PINT1_LATCH + 3,
1369 .flags = IORESOURCE_MEM,
1370 },
1371 {
1372 .start = IRQ_PINT1,
1373 .end = IRQ_PINT1,
1374 .flags = IORESOURCE_IRQ,
1375 },
1376};
1377
1378static struct platform_device bfin_pint1_device = {
1379 .name = ADI_PINT_DEVNAME,
1380 .id = 1,
1381 .num_resources = ARRAY_SIZE(bfin_pint1_resources),
1382 .resource = bfin_pint1_resources,
1383};
1384
1385static struct resource bfin_pint2_resources[] = {
1386 {
1387 .start = PINT2_MASK_SET,
1388 .end = PINT2_LATCH + 3,
1389 .flags = IORESOURCE_MEM,
1390 },
1391 {
1392 .start = IRQ_PINT2,
1393 .end = IRQ_PINT2,
1394 .flags = IORESOURCE_IRQ,
1395 },
1396};
1397
1398static struct platform_device bfin_pint2_device = {
1399 .name = ADI_PINT_DEVNAME,
1400 .id = 2,
1401 .num_resources = ARRAY_SIZE(bfin_pint2_resources),
1402 .resource = bfin_pint2_resources,
1403};
1404
1405static struct resource bfin_pint3_resources[] = {
1406 {
1407 .start = PINT3_MASK_SET,
1408 .end = PINT3_LATCH + 3,
1409 .flags = IORESOURCE_MEM,
1410 },
1411 {
1412 .start = IRQ_PINT3,
1413 .end = IRQ_PINT3,
1414 .flags = IORESOURCE_IRQ,
1415 },
1416};
1417
1418static struct platform_device bfin_pint3_device = {
1419 .name = ADI_PINT_DEVNAME,
1420 .id = 3,
1421 .num_resources = ARRAY_SIZE(bfin_pint3_resources),
1422 .resource = bfin_pint3_resources,
1423};
1424
1425static struct resource bfin_pint4_resources[] = {
1426 {
1427 .start = PINT4_MASK_SET,
1428 .end = PINT4_LATCH + 3,
1429 .flags = IORESOURCE_MEM,
1430 },
1431 {
1432 .start = IRQ_PINT4,
1433 .end = IRQ_PINT4,
1434 .flags = IORESOURCE_IRQ,
1435 },
1436};
1437
1438static struct platform_device bfin_pint4_device = {
1439 .name = ADI_PINT_DEVNAME,
1440 .id = 4,
1441 .num_resources = ARRAY_SIZE(bfin_pint4_resources),
1442 .resource = bfin_pint4_resources,
1443};
1444
1445static struct resource bfin_pint5_resources[] = {
1446 {
1447 .start = PINT5_MASK_SET,
1448 .end = PINT5_LATCH + 3,
1449 .flags = IORESOURCE_MEM,
1450 },
1451 {
1452 .start = IRQ_PINT5,
1453 .end = IRQ_PINT5,
1454 .flags = IORESOURCE_IRQ,
1455 },
1456};
1457
1458static struct platform_device bfin_pint5_device = {
1459 .name = ADI_PINT_DEVNAME,
1460 .id = 5,
1461 .num_resources = ARRAY_SIZE(bfin_pint5_resources),
1462 .resource = bfin_pint5_resources,
1463};
1464
1465static struct resource bfin_gpa_resources[] = {
1466 {
1467 .start = PORTA_FER,
1468 .end = PORTA_MUX + 3,
1469 .flags = IORESOURCE_MEM,
1470 },
1471 { /* optional */
1472 .start = IRQ_PA0,
1473 .end = IRQ_PA0,
1474 .flags = IORESOURCE_IRQ,
1475 },
1476};
1477
1478static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
1479 .port_pin_base = GPIO_PA0,
1480 .port_width = GPIO_BANKSIZE,
1481 .pint_id = 0, /* PINT0 */
1482 .pint_assign = true, /* PINT upper 16 bit */
1483 .pint_map = 0, /* mapping mask in PINT */
1484};
1485
1486static struct platform_device bfin_gpa_device = {
1487 .name = ADI_GPIO_DEVNAME,
1488 .id = 0,
1489 .num_resources = ARRAY_SIZE(bfin_gpa_resources),
1490 .resource = bfin_gpa_resources,
1491 .dev = {
1492 .platform_data = &bfin_gpa_pdata, /* Passed to driver */
1493 },
1494};
1495
1496static struct resource bfin_gpb_resources[] = {
1497 {
1498 .start = PORTB_FER,
1499 .end = PORTB_MUX + 3,
1500 .flags = IORESOURCE_MEM,
1501 },
1502 {
1503 .start = IRQ_PB0,
1504 .end = IRQ_PB0,
1505 .flags = IORESOURCE_IRQ,
1506 },
1507};
1508
1509static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
1510 .port_pin_base = GPIO_PB0,
1511 .port_width = GPIO_BANKSIZE,
1512 .pint_id = 0,
1513 .pint_assign = false,
1514 .pint_map = 1,
1515};
1516
1517static struct platform_device bfin_gpb_device = {
1518 .name = ADI_GPIO_DEVNAME,
1519 .id = 1,
1520 .num_resources = ARRAY_SIZE(bfin_gpb_resources),
1521 .resource = bfin_gpb_resources,
1522 .dev = {
1523 .platform_data = &bfin_gpb_pdata, /* Passed to driver */
1524 },
1525};
1526
1527static struct resource bfin_gpc_resources[] = {
1528 {
1529 .start = PORTC_FER,
1530 .end = PORTC_MUX + 3,
1531 .flags = IORESOURCE_MEM,
1532 },
1533 {
1534 .start = IRQ_PC0,
1535 .end = IRQ_PC0,
1536 .flags = IORESOURCE_IRQ,
1537 },
1538};
1539
1540static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
1541 .port_pin_base = GPIO_PC0,
1542 .port_width = GPIO_BANKSIZE,
1543 .pint_id = 1,
1544 .pint_assign = false,
1545 .pint_map = 1,
1546};
1547
1548static struct platform_device bfin_gpc_device = {
1549 .name = ADI_GPIO_DEVNAME,
1550 .id = 2,
1551 .num_resources = ARRAY_SIZE(bfin_gpc_resources),
1552 .resource = bfin_gpc_resources,
1553 .dev = {
1554 .platform_data = &bfin_gpc_pdata, /* Passed to driver */
1555 },
1556};
1557
1558static struct resource bfin_gpd_resources[] = {
1559 {
1560 .start = PORTD_FER,
1561 .end = PORTD_MUX + 3,
1562 .flags = IORESOURCE_MEM,
1563 },
1564 {
1565 .start = IRQ_PD0,
1566 .end = IRQ_PD0,
1567 .flags = IORESOURCE_IRQ,
1568 },
1569};
1570
1571static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
1572 .port_pin_base = GPIO_PD0,
1573 .port_width = GPIO_BANKSIZE,
1574 .pint_id = 2,
1575 .pint_assign = false,
1576 .pint_map = 1,
1577};
1578
1579static struct platform_device bfin_gpd_device = {
1580 .name = ADI_GPIO_DEVNAME,
1581 .id = 3,
1582 .num_resources = ARRAY_SIZE(bfin_gpd_resources),
1583 .resource = bfin_gpd_resources,
1584 .dev = {
1585 .platform_data = &bfin_gpd_pdata, /* Passed to driver */
1586 },
1587};
1588
1589static struct resource bfin_gpe_resources[] = {
1590 {
1591 .start = PORTE_FER,
1592 .end = PORTE_MUX + 3,
1593 .flags = IORESOURCE_MEM,
1594 },
1595 {
1596 .start = IRQ_PE0,
1597 .end = IRQ_PE0,
1598 .flags = IORESOURCE_IRQ,
1599 },
1600};
1601
1602static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
1603 .port_pin_base = GPIO_PE0,
1604 .port_width = GPIO_BANKSIZE,
1605 .pint_id = 3,
1606 .pint_assign = false,
1607 .pint_map = 1,
1608};
1609
1610static struct platform_device bfin_gpe_device = {
1611 .name = ADI_GPIO_DEVNAME,
1612 .id = 4,
1613 .num_resources = ARRAY_SIZE(bfin_gpe_resources),
1614 .resource = bfin_gpe_resources,
1615 .dev = {
1616 .platform_data = &bfin_gpe_pdata, /* Passed to driver */
1617 },
1618};
1619
1620static struct resource bfin_gpf_resources[] = {
1621 {
1622 .start = PORTF_FER,
1623 .end = PORTF_MUX + 3,
1624 .flags = IORESOURCE_MEM,
1625 },
1626 {
1627 .start = IRQ_PF0,
1628 .end = IRQ_PF0,
1629 .flags = IORESOURCE_IRQ,
1630 },
1631};
1632
1633static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
1634 .port_pin_base = GPIO_PF0,
1635 .port_width = GPIO_BANKSIZE,
1636 .pint_id = 4,
1637 .pint_assign = false,
1638 .pint_map = 1,
1639};
1640
1641static struct platform_device bfin_gpf_device = {
1642 .name = ADI_GPIO_DEVNAME,
1643 .id = 5,
1644 .num_resources = ARRAY_SIZE(bfin_gpf_resources),
1645 .resource = bfin_gpf_resources,
1646 .dev = {
1647 .platform_data = &bfin_gpf_pdata, /* Passed to driver */
1648 },
1649};
1650
1651static struct resource bfin_gpg_resources[] = {
1652 {
1653 .start = PORTG_FER,
1654 .end = PORTG_MUX + 3,
1655 .flags = IORESOURCE_MEM,
1656 },
1657 {
1658 .start = IRQ_PG0,
1659 .end = IRQ_PG0,
1660 .flags = IORESOURCE_IRQ,
1661 },
1662};
1663
1664static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
1665 .port_pin_base = GPIO_PG0,
1666 .port_width = GPIO_BANKSIZE,
1667 .pint_id = 5,
1668 .pint_assign = false,
1669 .pint_map = 1,
1670};
1671
1672static struct platform_device bfin_gpg_device = {
1673 .name = ADI_GPIO_DEVNAME,
1674 .id = 6,
1675 .num_resources = ARRAY_SIZE(bfin_gpg_resources),
1676 .resource = bfin_gpg_resources,
1677 .dev = {
1678 .platform_data = &bfin_gpg_pdata, /* Passed to driver */
1679 },
1680};
1681
1682#endif
1683
1322#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) 1684#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1323#include <linux/input.h> 1685#include <linux/input.h>
1324#include <linux/gpio_keys.h> 1686#include <linux/gpio_keys.h>
@@ -1349,7 +1711,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1349 .modalias = "m25p80", /* Name of spi_driver for this device */ 1711 .modalias = "m25p80", /* Name of spi_driver for this device */
1350 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 1712 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1351 .bus_num = 0, /* Framework bus number */ 1713 .bus_num = 0, /* Framework bus number */
1352 .chip_select = 1, /* SPI_SSEL1*/ 1714 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
1353 .platform_data = &bfin_spi_flash_data, 1715 .platform_data = &bfin_spi_flash_data,
1354 .controller_data = &spi_flash_chip_info, 1716 .controller_data = &spi_flash_chip_info,
1355 .mode = SPI_MODE_3, 1717 .mode = SPI_MODE_3,
@@ -1362,7 +1724,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1362 .irq = IRQ_PD9, 1724 .irq = IRQ_PD9,
1363 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 1725 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1364 .bus_num = 0, 1726 .bus_num = 0,
1365 .chip_select = 4, 1727 .chip_select = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
1366 }, 1728 },
1367#endif 1729#endif
1368#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) 1730#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -1370,7 +1732,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1370 .modalias = "spidev", 1732 .modalias = "spidev",
1371 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 1733 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1372 .bus_num = 0, 1734 .bus_num = 0,
1373 .chip_select = 1, 1735 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
1374 .controller_data = &spidev_chip_info, 1736 .controller_data = &spidev_chip_info,
1375 }, 1737 },
1376#endif 1738#endif
@@ -1565,6 +1927,22 @@ static struct platform_device bfin_dpmc = {
1565static struct platform_device *ezkit_devices[] __initdata = { 1927static struct platform_device *ezkit_devices[] __initdata = {
1566 1928
1567 &bfin_dpmc, 1929 &bfin_dpmc,
1930#if defined(CONFIG_PINCTRL_ADI2)
1931 &bfin_pinctrl_device,
1932 &bfin_pint0_device,
1933 &bfin_pint1_device,
1934 &bfin_pint2_device,
1935 &bfin_pint3_device,
1936 &bfin_pint4_device,
1937 &bfin_pint5_device,
1938 &bfin_gpa_device,
1939 &bfin_gpb_device,
1940 &bfin_gpc_device,
1941 &bfin_gpd_device,
1942 &bfin_gpe_device,
1943 &bfin_gpf_device,
1944 &bfin_gpg_device,
1945#endif
1568 1946
1569#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 1947#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1570 &rtc_device, 1948 &rtc_device,
@@ -1681,20 +2059,91 @@ static struct platform_device *ezkit_devices[] __initdata = {
1681 2059
1682}; 2060};
1683 2061
2062/* Pin control settings */
2063static struct pinctrl_map __initdata bfin_pinmux_map[] = {
2064 /* per-device maps */
2065 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
2066 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
2067 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
2068 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
2069 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
2070 PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
2071 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
2072 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
2073 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
2074 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
2075 PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
2076 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
2077 PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
2078 PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.2", "pinctrl-adi2.0", NULL, "ppi2_16b"),
2079 PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
2080#if defined(CONFIG_VIDEO_MT9M114) || defined(CONFIG_VIDEO_MT9M114_MODULE)
2081 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_8b"),
2082#elif defined(CONFIG_VIDEO_VS6624) || defined(CONFIG_VIDEO_VS6624_MODULE)
2083 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
2084#else
2085 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_24b"),
2086#endif
2087 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
2088 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
2089 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
2090 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
2091 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
2092 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
2093};
2094
2095/* Pin control settings */
2096static struct pinctrl_map __initdata bfin_pinmux_map[] = {
2097 /* per-device maps */
2098 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
2099#ifdef CONFIG_BFIN_UART0_CTSRTS
2100 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0_ctsrts"),
2101#endif
2102 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
2103#ifdef CONFIG_BFIN_UART1_CTSRTS
2104 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1_ctsrts"),
2105#endif
2106 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
2107 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
2108 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
2109 PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
2110 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
2111 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
2112 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
2113 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
2114 PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
2115 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
2116 PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
2117 PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.2", "pinctrl-adi2.0", NULL, "ppi2_16b"),
2118 PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", NULL, "ppi2_16b"),
2119#if defined(CONFIG_VIDEO_MT9M114) || defined(CONFIG_VIDEO_MT9M114_MODULE)
2120 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_8b"),
2121#elif defined(CONFIG_VIDEO_VS6624) || defined(CONFIG_VIDEO_VS6624_MODULE)
2122 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
2123#else
2124 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_24b"),
2125#endif
2126 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
2127 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
2128 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
2129 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
2130 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
2131 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
2132};
2133
1684static int __init ezkit_init(void) 2134static int __init ezkit_init(void)
1685{ 2135{
1686 printk(KERN_INFO "%s(): registering device resources\n", __func__); 2136 printk(KERN_INFO "%s(): registering device resources\n", __func__);
1687 2137
2138 /* Initialize pinmuxing */
2139 pinctrl_register_mappings(bfin_pinmux_map,
2140 ARRAY_SIZE(bfin_pinmux_map));
2141
1688 i2c_register_board_info(0, bfin_i2c_board_info0, 2142 i2c_register_board_info(0, bfin_i2c_board_info0,
1689 ARRAY_SIZE(bfin_i2c_board_info0)); 2143 ARRAY_SIZE(bfin_i2c_board_info0));
1690 i2c_register_board_info(1, bfin_i2c_board_info1, 2144 i2c_register_board_info(1, bfin_i2c_board_info1,
1691 ARRAY_SIZE(bfin_i2c_board_info1)); 2145 ARRAY_SIZE(bfin_i2c_board_info1));
1692 2146
1693#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
1694 if (!peripheral_request_list(pins, "emac0"))
1695 printk(KERN_ERR "%s(): request emac pins failed\n", __func__);
1696#endif
1697
1698 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices)); 2147 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
1699 2148
1700 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 2149 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h
index c32c8cc8db2e..07182513e794 100644
--- a/arch/blackfin/mach-bf609/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf609/include/mach/gpio.h
@@ -152,14 +152,6 @@ struct gpio_port_t {
152 unsigned long revid; 152 unsigned long revid;
153}; 153};
154 154
155struct gpio_port_s {
156 unsigned short fer;
157 unsigned short data;
158 unsigned short dir;
159 unsigned short inen;
160 unsigned int mux;
161};
162
163#endif 155#endif
164 156
165#include <mach-common/ports-a.h> 157#include <mach-common/ports-a.h>
diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h
index fa0843d5d77a..d1cb6a86f80a 100644
--- a/arch/blackfin/mach-bf609/include/mach/irq.h
+++ b/arch/blackfin/mach-bf609/include/mach/irq.h
@@ -298,7 +298,7 @@
298extern u8 sec_int_priority[]; 298extern u8 sec_int_priority[];
299 299
300/* 300/*
301 * bfin pint registers layout 301 * gpio pint registers layout
302 */ 302 */
303struct bfin_pint_regs { 303struct bfin_pint_regs {
304 u32 mask_set; 304 u32 mask_set;
diff --git a/arch/blackfin/mach-bf609/include/mach/portmux.h b/arch/blackfin/mach-bf609/include/mach/portmux.h
index 2e1a51c25098..c48bb71a55ce 100644
--- a/arch/blackfin/mach-bf609/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf609/include/mach/portmux.h
@@ -7,8 +7,6 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
11
12/* EMAC RMII Port Mux */ 10/* EMAC RMII Port Mux */
13#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0)) 11#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
14#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0)) 12#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
@@ -21,6 +19,7 @@
21#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0)) 19#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
22#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0)) 20#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
23#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0)) 21#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
22#define P_MII0_PTPPPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
24 23
25#define P_RMII0 {\ 24#define P_RMII0 {\
26 P_MII0_ETxD0, \ 25 P_MII0_ETxD0, \
@@ -32,6 +31,7 @@
32 P_MII0_TxCLK, \ 31 P_MII0_TxCLK, \
33 P_MII0_PHYINT, \ 32 P_MII0_PHYINT, \
34 P_MII0_CRS, \ 33 P_MII0_CRS, \
34 P_MII0_PTPPPS, \
35 P_MII0_MDC, \ 35 P_MII0_MDC, \
36 P_MII0_MDIO, 0} 36 P_MII0_MDIO, 0}
37 37
@@ -46,6 +46,7 @@
46#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0)) 46#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
47#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0)) 47#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
48#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) 48#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
49#define P_MII1_PTPPPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
49 50
50#define P_RMII1 {\ 51#define P_RMII1 {\
51 P_MII1_ETxD0, \ 52 P_MII1_ETxD0, \
@@ -57,6 +58,7 @@
57 P_MII1_TxCLK, \ 58 P_MII1_TxCLK, \
58 P_MII1_PHYINT, \ 59 P_MII1_PHYINT, \
59 P_MII1_CRS, \ 60 P_MII1_CRS, \
61 P_MII1_PTPPPS, \
60 P_MII1_MDC, \ 62 P_MII1_MDC, \
61 P_MII1_MDIO, 0} 63 P_MII1_MDIO, 0}
62 64
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index d143fd8d2bc5..ca75613231c8 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -704,10 +704,9 @@ static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
704 __irq_set_handler_locked(irq, handle); 704 __irq_set_handler_locked(irq, handle);
705} 705}
706 706
707static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); 707#ifdef CONFIG_GPIO_ADI
708extern void bfin_gpio_irq_prepare(unsigned gpio);
709 708
710#if !BFIN_GPIO_PINT 709static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
711 710
712static void bfin_gpio_ack_irq(struct irq_data *d) 711static void bfin_gpio_ack_irq(struct irq_data *d)
713{ 712{
@@ -821,15 +820,6 @@ static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
821 return 0; 820 return 0;
822} 821}
823 822
824#ifdef CONFIG_PM
825static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
826{
827 return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
828}
829#else
830# define bfin_gpio_set_wake NULL
831#endif
832
833static void bfin_demux_gpio_block(unsigned int irq) 823static void bfin_demux_gpio_block(unsigned int irq)
834{ 824{
835 unsigned int gpio, mask; 825 unsigned int gpio, mask;
@@ -896,279 +886,40 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
896 bfin_demux_gpio_block(irq); 886 bfin_demux_gpio_block(irq);
897} 887}
898 888
899#else
900
901#define NR_PINT_BITS 32
902#define IRQ_NOT_AVAIL 0xFF
903
904#define PINT_2_BANK(x) ((x) >> 5)
905#define PINT_2_BIT(x) ((x) & 0x1F)
906#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
907
908static unsigned char irq2pint_lut[NR_PINTS];
909static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
910
911static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
912 (struct bfin_pint_regs *)PINT0_MASK_SET,
913 (struct bfin_pint_regs *)PINT1_MASK_SET,
914 (struct bfin_pint_regs *)PINT2_MASK_SET,
915 (struct bfin_pint_regs *)PINT3_MASK_SET,
916#ifdef CONFIG_BF60x
917 (struct bfin_pint_regs *)PINT4_MASK_SET,
918 (struct bfin_pint_regs *)PINT5_MASK_SET,
919#endif
920};
921
922inline unsigned int get_irq_base(u32 bank, u8 bmap)
923{
924 unsigned int irq_base;
925
926#ifndef CONFIG_BF60x
927 if (bank < 2) { /*PA-PB */
928 irq_base = IRQ_PA0 + bmap * 16;
929 } else { /*PC-PJ */
930 irq_base = IRQ_PC0 + bmap * 16;
931 }
932#else
933 irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
934#endif
935 return irq_base;
936}
937
938 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
939void init_pint_lut(void)
940{
941 u16 bank, bit, irq_base, bit_pos;
942 u32 pint_assign;
943 u8 bmap;
944
945 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
946
947 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
948
949 pint_assign = pint[bank]->assign;
950
951 for (bit = 0; bit < NR_PINT_BITS; bit++) {
952
953 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
954
955 irq_base = get_irq_base(bank, bmap);
956
957 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
958 bit_pos = bit + bank * NR_PINT_BITS;
959
960 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
961 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
962 }
963 }
964}
965
966static void bfin_gpio_ack_irq(struct irq_data *d)
967{
968 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
969 u32 pintbit = PINT_BIT(pint_val);
970 u32 bank = PINT_2_BANK(pint_val);
971
972 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
973 if (pint[bank]->invert_set & pintbit)
974 pint[bank]->invert_clear = pintbit;
975 else
976 pint[bank]->invert_set = pintbit;
977 }
978 pint[bank]->request = pintbit;
979
980}
981
982static void bfin_gpio_mask_ack_irq(struct irq_data *d)
983{
984 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
985 u32 pintbit = PINT_BIT(pint_val);
986 u32 bank = PINT_2_BANK(pint_val);
987
988 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
989 if (pint[bank]->invert_set & pintbit)
990 pint[bank]->invert_clear = pintbit;
991 else
992 pint[bank]->invert_set = pintbit;
993 }
994
995 pint[bank]->request = pintbit;
996 pint[bank]->mask_clear = pintbit;
997}
998
999static void bfin_gpio_mask_irq(struct irq_data *d)
1000{
1001 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1002
1003 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
1004}
1005
1006static void bfin_gpio_unmask_irq(struct irq_data *d)
1007{
1008 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
1009 u32 pintbit = PINT_BIT(pint_val);
1010 u32 bank = PINT_2_BANK(pint_val);
1011
1012 pint[bank]->mask_set = pintbit;
1013}
1014
1015static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
1016{
1017 unsigned int irq = d->irq;
1018 u32 gpionr = irq_to_gpio(irq);
1019 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
1020
1021 if (pint_val == IRQ_NOT_AVAIL) {
1022 printk(KERN_ERR
1023 "GPIO IRQ %d :Not in PINT Assign table "
1024 "Reconfigure Interrupt to Port Assignemt\n", irq);
1025 return -ENODEV;
1026 }
1027
1028 if (__test_and_set_bit(gpionr, gpio_enabled))
1029 bfin_gpio_irq_prepare(gpionr);
1030
1031 bfin_gpio_unmask_irq(d);
1032
1033 return 0;
1034}
1035
1036static void bfin_gpio_irq_shutdown(struct irq_data *d)
1037{
1038 u32 gpionr = irq_to_gpio(d->irq);
1039
1040 bfin_gpio_mask_irq(d);
1041 __clear_bit(gpionr, gpio_enabled);
1042 bfin_gpio_irq_free(gpionr);
1043}
1044
1045static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
1046{
1047 unsigned int irq = d->irq;
1048 int ret;
1049 char buf[16];
1050 u32 gpionr = irq_to_gpio(irq);
1051 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
1052 u32 pintbit = PINT_BIT(pint_val);
1053 u32 bank = PINT_2_BANK(pint_val);
1054
1055 if (pint_val == IRQ_NOT_AVAIL)
1056 return -ENODEV;
1057
1058 if (type == IRQ_TYPE_PROBE) {
1059 /* only probe unenabled GPIO interrupt lines */
1060 if (test_bit(gpionr, gpio_enabled))
1061 return 0;
1062 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1063 }
1064
1065 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
1066 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
1067
1068 snprintf(buf, 16, "gpio-irq%d", irq);
1069 ret = bfin_gpio_irq_request(gpionr, buf);
1070 if (ret)
1071 return ret;
1072
1073 if (__test_and_set_bit(gpionr, gpio_enabled))
1074 bfin_gpio_irq_prepare(gpionr);
1075
1076 } else {
1077 __clear_bit(gpionr, gpio_enabled);
1078 return 0;
1079 }
1080
1081 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
1082 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
1083 else
1084 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
1085
1086 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
1087 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1088 if (gpio_get_value(gpionr))
1089 pint[bank]->invert_set = pintbit;
1090 else
1091 pint[bank]->invert_clear = pintbit;
1092 }
1093
1094 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1095 pint[bank]->edge_set = pintbit;
1096 bfin_set_irq_handler(irq, handle_edge_irq);
1097 } else {
1098 pint[bank]->edge_clear = pintbit;
1099 bfin_set_irq_handler(irq, handle_level_irq);
1100 }
1101
1102 return 0;
1103}
1104
1105#ifdef CONFIG_PM 889#ifdef CONFIG_PM
1106static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS];
1107static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
1108 890
1109static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) 891static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
1110{ 892{
1111 u32 pint_irq; 893 return bfin_gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
1112 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; 894}
1113 u32 bank = PINT_2_BANK(pint_val);
1114
1115 switch (bank) {
1116 case 0:
1117 pint_irq = IRQ_PINT0;
1118 break;
1119 case 2:
1120 pint_irq = IRQ_PINT2;
1121 break;
1122 case 3:
1123 pint_irq = IRQ_PINT3;
1124 break;
1125 case 1:
1126 pint_irq = IRQ_PINT1;
1127 break;
1128#ifdef CONFIG_BF60x
1129 case 4:
1130 pint_irq = IRQ_PINT4;
1131 break;
1132 case 5:
1133 pint_irq = IRQ_PINT5;
1134 break;
1135#endif
1136 default:
1137 return -EINVAL;
1138 }
1139 895
1140#ifndef SEC_GCTL 896#else
1141 bfin_internal_set_wake(pint_irq, state);
1142#endif
1143 897
1144 return 0; 898# define bfin_gpio_set_wake NULL
1145}
1146 899
1147void bfin_pint_suspend(void) 900#endif
1148{
1149 u32 bank;
1150 901
1151 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { 902static struct irq_chip bfin_gpio_irqchip = {
1152 save_pint_reg[bank].mask_set = pint[bank]->mask_set; 903 .name = "GPIO",
1153 save_pint_reg[bank].assign = pint[bank]->assign; 904 .irq_ack = bfin_gpio_ack_irq,
1154 save_pint_reg[bank].edge_set = pint[bank]->edge_set; 905 .irq_mask = bfin_gpio_mask_irq,
1155 save_pint_reg[bank].invert_set = pint[bank]->invert_set; 906 .irq_mask_ack = bfin_gpio_mask_ack_irq,
1156 } 907 .irq_unmask = bfin_gpio_unmask_irq,
1157} 908 .irq_disable = bfin_gpio_mask_irq,
909 .irq_enable = bfin_gpio_unmask_irq,
910 .irq_set_type = bfin_gpio_irq_type,
911 .irq_startup = bfin_gpio_irq_startup,
912 .irq_shutdown = bfin_gpio_irq_shutdown,
913 .irq_set_wake = bfin_gpio_set_wake,
914};
1158 915
1159void bfin_pint_resume(void) 916#endif
1160{
1161 u32 bank;
1162 917
1163 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { 918#ifdef CONFIG_PM
1164 pint[bank]->mask_set = save_pint_reg[bank].mask_set;
1165 pint[bank]->assign = save_pint_reg[bank].assign;
1166 pint[bank]->edge_set = save_pint_reg[bank].edge_set;
1167 pint[bank]->invert_set = save_pint_reg[bank].invert_set;
1168 }
1169}
1170 919
1171#ifdef SEC_GCTL 920#ifdef SEC_GCTL
921static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
922
1172static int sec_suspend(void) 923static int sec_suspend(void)
1173{ 924{
1174 u32 bank; 925 u32 bank;
@@ -1195,92 +946,10 @@ static struct syscore_ops sec_pm_syscore_ops = {
1195 .suspend = sec_suspend, 946 .suspend = sec_suspend,
1196 .resume = sec_resume, 947 .resume = sec_resume,
1197}; 948};
1198
1199#endif
1200#else
1201# define bfin_gpio_set_wake NULL
1202#endif
1203
1204void bfin_demux_gpio_irq(unsigned int inta_irq,
1205 struct irq_desc *desc)
1206{
1207 u32 bank, pint_val;
1208 u32 request, irq;
1209 u32 level_mask;
1210 int umask = 0;
1211 struct irq_chip *chip = irq_desc_get_chip(desc);
1212
1213 if (chip->irq_mask_ack) {
1214 chip->irq_mask_ack(&desc->irq_data);
1215 } else {
1216 chip->irq_mask(&desc->irq_data);
1217 if (chip->irq_ack)
1218 chip->irq_ack(&desc->irq_data);
1219 }
1220
1221 switch (inta_irq) {
1222 case IRQ_PINT0:
1223 bank = 0;
1224 break;
1225 case IRQ_PINT2:
1226 bank = 2;
1227 break;
1228 case IRQ_PINT3:
1229 bank = 3;
1230 break;
1231 case IRQ_PINT1:
1232 bank = 1;
1233 break;
1234#ifdef CONFIG_BF60x
1235 case IRQ_PINT4:
1236 bank = 4;
1237 break;
1238 case IRQ_PINT5:
1239 bank = 5;
1240 break;
1241#endif 949#endif
1242 default:
1243 return;
1244 }
1245
1246 pint_val = bank * NR_PINT_BITS;
1247
1248 request = pint[bank]->request;
1249
1250 level_mask = pint[bank]->edge_set & request;
1251
1252 while (request) {
1253 if (request & 1) {
1254 irq = pint2irq_lut[pint_val] + SYS_IRQS;
1255 if (level_mask & PINT_BIT(pint_val)) {
1256 umask = 1;
1257 chip->irq_unmask(&desc->irq_data);
1258 }
1259 bfin_handle_irq(irq);
1260 }
1261 pint_val++;
1262 request >>= 1;
1263 }
1264 950
1265 if (!umask)
1266 chip->irq_unmask(&desc->irq_data);
1267}
1268#endif 951#endif
1269 952
1270static struct irq_chip bfin_gpio_irqchip = {
1271 .name = "GPIO",
1272 .irq_ack = bfin_gpio_ack_irq,
1273 .irq_mask = bfin_gpio_mask_irq,
1274 .irq_mask_ack = bfin_gpio_mask_ack_irq,
1275 .irq_unmask = bfin_gpio_unmask_irq,
1276 .irq_disable = bfin_gpio_mask_irq,
1277 .irq_enable = bfin_gpio_unmask_irq,
1278 .irq_set_type = bfin_gpio_irq_type,
1279 .irq_startup = bfin_gpio_irq_startup,
1280 .irq_shutdown = bfin_gpio_irq_shutdown,
1281 .irq_set_wake = bfin_gpio_set_wake,
1282};
1283
1284void init_exception_vectors(void) 953void init_exception_vectors(void)
1285{ 954{
1286 /* cannot program in software: 955 /* cannot program in software:
@@ -1331,17 +1000,6 @@ int __init init_arch_irq(void)
1331 1000
1332 local_irq_disable(); 1001 local_irq_disable();
1333 1002
1334#if BFIN_GPIO_PINT
1335# ifdef CONFIG_PINTx_REASSIGN
1336 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1337 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1338 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1339 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1340# endif
1341 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1342 init_pint_lut();
1343#endif
1344
1345 for (irq = 0; irq <= SYS_IRQS; irq++) { 1003 for (irq = 0; irq <= SYS_IRQS; irq++) {
1346 if (irq <= IRQ_CORETMR) 1004 if (irq <= IRQ_CORETMR)
1347 irq_set_chip(irq, &bfin_core_irqchip); 1005 irq_set_chip(irq, &bfin_core_irqchip);
@@ -1349,12 +1007,8 @@ int __init init_arch_irq(void)
1349 irq_set_chip(irq, &bfin_internal_irqchip); 1007 irq_set_chip(irq, &bfin_internal_irqchip);
1350 1008
1351 switch (irq) { 1009 switch (irq) {
1352#if BFIN_GPIO_PINT 1010#if !BFIN_GPIO_PINT
1353 case IRQ_PINT0: 1011#if defined(BF537_FAMILY)
1354 case IRQ_PINT1:
1355 case IRQ_PINT2:
1356 case IRQ_PINT3:
1357#elif defined(BF537_FAMILY)
1358 case IRQ_PH_INTA_MAC_RX: 1012 case IRQ_PH_INTA_MAC_RX:
1359 case IRQ_PF_INTA_PG_INTA: 1013 case IRQ_PF_INTA_PG_INTA:
1360#elif defined(BF533_FAMILY) 1014#elif defined(BF533_FAMILY)
@@ -1372,6 +1026,7 @@ int __init init_arch_irq(void)
1372#endif 1026#endif
1373 irq_set_chained_handler(irq, bfin_demux_gpio_irq); 1027 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1374 break; 1028 break;
1029#endif
1375#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 1030#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1376 case IRQ_MAC_ERROR: 1031 case IRQ_MAC_ERROR:
1377 irq_set_chained_handler(irq, 1032 irq_set_chained_handler(irq,
@@ -1419,10 +1074,12 @@ int __init init_arch_irq(void)
1419 handle_level_irq); 1074 handle_level_irq);
1420#endif 1075#endif
1421 /* if configured as edge, then will be changed to do_edge_IRQ */ 1076 /* if configured as edge, then will be changed to do_edge_IRQ */
1077#ifdef CONFIG_GPIO_ADI
1422 for (irq = GPIO_IRQ_BASE; 1078 for (irq = GPIO_IRQ_BASE;
1423 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) 1079 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1424 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, 1080 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1425 handle_level_irq); 1081 handle_level_irq);
1082#endif
1426 bfin_write_IMASK(0); 1083 bfin_write_IMASK(0);
1427 CSYNC(); 1084 CSYNC();
1428 ilat = bfin_read_ILAT(); 1085 ilat = bfin_read_ILAT();
@@ -1525,19 +1182,6 @@ int __init init_arch_irq(void)
1525 1182
1526 local_irq_disable(); 1183 local_irq_disable();
1527 1184
1528#if BFIN_GPIO_PINT
1529# ifdef CONFIG_PINTx_REASSIGN
1530 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1531 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1532 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1533 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1534 pint[4]->assign = CONFIG_PINT4_ASSIGN;
1535 pint[5]->assign = CONFIG_PINT5_ASSIGN;
1536# endif
1537 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1538 init_pint_lut();
1539#endif
1540
1541 for (irq = 0; irq <= SYS_IRQS; irq++) { 1185 for (irq = 0; irq <= SYS_IRQS; irq++) {
1542 if (irq <= IRQ_CORETMR) { 1186 if (irq <= IRQ_CORETMR) {
1543 irq_set_chip_and_handler(irq, &bfin_core_irqchip, 1187 irq_set_chip_and_handler(irq, &bfin_core_irqchip,
@@ -1546,9 +1190,6 @@ int __init init_arch_irq(void)
1546 if (irq == IRQ_CORETMR) 1190 if (irq == IRQ_CORETMR)
1547 irq_set_handler(irq, handle_percpu_irq); 1191 irq_set_handler(irq, handle_percpu_irq);
1548#endif 1192#endif
1549 } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
1550 irq_set_chip(irq, &bfin_sec_irqchip);
1551 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1552 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) { 1193 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
1553 irq_set_chip_and_handler(irq, &bfin_sec_irqchip, 1194 irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1554 handle_percpu_irq); 1195 handle_percpu_irq);
@@ -1563,10 +1204,6 @@ int __init init_arch_irq(void)
1563 __irq_set_preflow_handler(irq, bfin_sec_preflow_handler); 1204 __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1564 } 1205 }
1565 } 1206 }
1566 for (irq = GPIO_IRQ_BASE;
1567 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1568 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1569 handle_level_irq);
1570 1207
1571 bfin_write_IMASK(0); 1208 bfin_write_IMASK(0);
1572 CSYNC(); 1209 CSYNC();
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 87bfe549ad3f..675ffb148fbc 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -27,7 +27,7 @@ struct bfin_cpu_pm_fns *bfin_cpu_pm;
27 27
28void bfin_pm_suspend_standby_enter(void) 28void bfin_pm_suspend_standby_enter(void)
29{ 29{
30#ifndef CONFIG_BF60x 30#if !BFIN_GPIO_PINT
31 bfin_pm_standby_setup(); 31 bfin_pm_standby_setup();
32#endif 32#endif
33 33
@@ -41,7 +41,7 @@ void bfin_pm_suspend_standby_enter(void)
41# endif 41# endif
42#endif 42#endif
43 43
44#ifndef CONFIG_BF60x 44#if !BFIN_GPIO_PINT
45 bfin_pm_standby_restore(); 45 bfin_pm_standby_restore();
46#endif 46#endif
47 47
@@ -128,6 +128,7 @@ static void flushinv_all_dcache(void)
128 if ((status & 0x3) != 0x3) 128 if ((status & 0x3) != 0x3)
129 continue; 129 continue;
130 130
131
131 /* construct the address using the tag */ 132 /* construct the address using the tag */
132 addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5); 133 addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
133 134
@@ -170,10 +171,8 @@ int bfin_pm_suspend_mem_enter(void)
170 return ret; 171 return ret;
171 } 172 }
172 173
174#ifdef CONFIG_GPIO_ADI
173 bfin_gpio_pm_hibernate_suspend(); 175 bfin_gpio_pm_hibernate_suspend();
174
175#if BFIN_GPIO_PINT
176 bfin_pint_suspend();
177#endif 176#endif
178 177
179#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) 178#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
@@ -194,11 +193,9 @@ int bfin_pm_suspend_mem_enter(void)
194 _enable_icplb(); 193 _enable_icplb();
195 _enable_dcplb(); 194 _enable_dcplb();
196 195
197#if BFIN_GPIO_PINT 196#ifdef CONFIG_GPIO_ADI
198 bfin_pint_resume();
199#endif
200
201 bfin_gpio_pm_hibernate_restore(); 197 bfin_gpio_pm_hibernate_restore();
198#endif
202 blackfin_dma_resume(); 199 blackfin_dma_resume();
203 200
204 kfree(memptr); 201 kfree(memptr);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-15 17:25:17 -0500