blackfin: Support L1 SRAM parity checking feature on bf60x

Move code for the SEC faults from the IRQ hanlders into IRQ actions.
refine bfin fault routine handle

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Steven Miao <realmz6@gmail.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index ca67145c6a45..c5c8d8a3a5fa 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -544,6 +544,7 @@ do { \
 #define DCBS_P                  0x04    /* L1 Data Cache Bank Select */
 #define PORT_PREF0_P            0x12    /* DAG0 Port Preference */
 #define PORT_PREF1_P            0x13    /* DAG1 Port Preference */
+#define RDCHK                   0x9     /* Enable L1 Parity Check */
 
 /* Masks */
 #define ENDM               0x00000001   /* (doesn't really exist) Enable