arm64: arch_timer: Add workaround for ARM erratum 1188873

When running on Cortex-A76, a timer access from an AArch32 EL0
task may end up with a corrupted value or register. The workaround for
this is to trap these accesses at EL1/EL2 and execute them there.

This only affects versions r0p0, r1p0 and r2p0 of the CPU.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

1 files changed, 12 insertions, 0 deletions

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index da5e6f085561..52985d175e5a 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -481,6 +481,18 @@ config ARM64_ERRATUM_1024718
 
           If unsure, say Y.
 
+config ARM64_ERRATUM_1188873
+        bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
+        default y
+        help
+          This option adds work arounds for ARM Cortex-A76 erratum 1188873
+
+          Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
+          register corruption when accessing the timer registers from
+          AArch32 userspace.
+
+          If unsure, say Y.
+
 config CAVIUM_ERRATUM_22375
         bool "Cavium erratum 22375, 24313"
         default y