Merge branch 'next/cleanup-s3c24xx' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup

From Kukjin Kim:
Basically, this patch merges mach-s3c2410, mach-s3c2412 and mach-s3c2440
into mach-s3c24xx.

* 'next/cleanup-s3c24xx' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: S3C24XX: Move mach-s3c2440/ pll into mach-s3c24xx/
  ARM: S3C24XX: Move mach-s3c2440/ cpufreq driver into mach-s3c24xx/
  ARM: S3C24XX: Move mach-s3c2412/ cpufreq driver into mach-s3c24xx/
  ARM: S3C2412: Remove useless codes mach-s3c2412/gpio.c
  ARM: S3C24XX: Move mach-s3c2410/ pll into mach-s3c24xx/
  ARM: S3C24XX: Move mach-s3c2410/ cpufreq into mach-s3c24xx/

9 files changed, 1110 insertions, 6 deletions

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 25df14a9e268..67df58bdc096 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -127,6 +127,20 @@ config S3C2410_PM
 
 if CPU_S3C2410
 
+config S3C2410_CPUFREQ
+        bool
+        depends on CPU_FREQ_S3C24XX && CPU_S3C2410
+        select S3C2410_CPUFREQ_UTILS
+        help
+          CPU Frequency scaling support for S3C2410
+
+config S3C2410_PLL
+        bool
+        depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL
+        default y
+        help
+          Select the PLL table for the S3C2410
+
 config S3C24XX_SIMTEC_NOR
         bool
         help
@@ -266,6 +280,14 @@ config CPU_S3C2412_ONLY
                    !CPU_S3C2443 && CPU_S3C2412
         default y
 
+config S3C2412_CPUFREQ
+        bool
+        depends on CPU_FREQ_S3C24XX && CPU_S3C2412
+        default y
+        select S3C2412_IOTIMING
+        help
+          CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
+
 config S3C2412_DMA
         bool
         help
@@ -365,11 +387,45 @@ endif	# CPU_S3C2416
 
 if CPU_S3C2440
 
+config S3C2440_CPUFREQ
+        bool "S3C2440/S3C2442 CPU Frequency scaling support"
+        depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
+        default y
+        select S3C2410_CPUFREQ_UTILS
+        help
+          CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
+
 config S3C2440_DMA
         bool
         help
           Support for S3C2440 specific DMA code5A
 
+config S3C2440_XTAL_12000000
+        bool
+        help
+          Indicate that the build needs to support 12MHz system
+          crystal.
+
+config S3C2440_XTAL_16934400
+        bool
+        help
+          Indicate that the build needs to support 16.9344MHz system
+          crystal.
+
+config S3C2440_PLL_12000000
+        bool
+        depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000
+        default y if CPU_FREQ_S3C24XX_PLL
+        help
+          PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
+
+config S3C2440_PLL_16934400
+        bool
+        depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400
+        default y if CPU_FREQ_S3C24XX_PLL
+        help
+          PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
+
 comment "S3C2440 Boards"
 
 #
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 0ab6ab15da4c..08b87cdb98b7 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -17,10 +17,13 @@ obj-				:=
 obj-y                           += common.o
 
 obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
+obj-$(CONFIG_S3C2410_CPUFREQ)   += cpufreq-s3c2410.o
 obj-$(CONFIG_S3C2410_DMA)       += dma-s3c2410.o
+obj-$(CONFIG_S3C2410_PLL)       += pll-s3c2410.o
 obj-$(CONFIG_S3C2410_PM)        += pm-s3c2410.o sleep-s3c2410.o
 
 obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o irq-s3c2412.o clock-s3c2412.o
+obj-$(CONFIG_S3C2412_CPUFREQ)   += cpufreq-s3c2412.o
 obj-$(CONFIG_S3C2412_DMA)       += dma-s3c2412.o
 obj-$(CONFIG_S3C2412_PM)        += pm-s3c2412.o
 obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep-s3c2412.o
@@ -31,7 +34,10 @@ obj-$(CONFIG_S3C2416_PM)	+= pm-s3c2416.o
 obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o irq-s3c2440.o clock-s3c2440.o
 obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
 obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o irq-s3c244x.o clock-s3c244x.o
+obj-$(CONFIG_S3C2440_CPUFREQ)   += cpufreq-s3c2440.o
 obj-$(CONFIG_S3C2440_DMA)       += dma-s3c2440.o
+obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
+obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
 
 obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o irq-s3c2443.o clock-s3c2443.o
 
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c
new file mode 100644
index 000000000000..cfa0dd8723ec
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2006-2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 CPU Frequency scaling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/regs-clock.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/cpu-freq-core.h>
+
+/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
+
+static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        u32 clkdiv = 0;
+
+        if (cfg->divs.h_divisor == 2)
+                clkdiv |= S3C2410_CLKDIVN_HDIVN;
+
+        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
+                clkdiv |= S3C2410_CLKDIVN_PDIVN;
+
+        __raw_writel(clkdiv, S3C2410_CLKDIVN);
+}
+
+static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long hclk, fclk, pclk;
+        unsigned int hdiv, pdiv;
+        unsigned long hclk_max;
+
+        fclk = cfg->freq.fclk;
+        hclk_max = cfg->max.hclk;
+
+        cfg->freq.armclk = fclk;
+
+        s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
+                      __func__, fclk, hclk_max);
+
+        hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
+        hclk = fclk / hdiv;
+
+        if (hclk > cfg->max.hclk) {
+                s3c_freq_dbg("%s: hclk too big\n", __func__);
+                return -EINVAL;
+        }
+
+        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
+        pclk = hclk / pdiv;
+
+        if (pclk > cfg->max.pclk) {
+                s3c_freq_dbg("%s: pclk too big\n", __func__);
+                return -EINVAL;
+        }
+
+        pdiv *= hdiv;
+
+        /* record the result */
+        cfg->divs.p_divisor = pdiv;
+        cfg->divs.h_divisor = hdiv;
+
+        return 0;
+}
+
+static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
+        .max            = {
+                .fclk   = 200000000,
+                .hclk   = 100000000,
+                .pclk   =  50000000,
+        },
+
+        /* transition latency is about 5ms worst-case, so
+         * set 10ms to be sure */
+        .latency        = 10000000,
+
+        .locktime_m     = 150,
+        .locktime_u     = 150,
+        .locktime_bits  = 12,
+
+        .need_pll       = 1,
+
+        .name           = "s3c2410",
+        .calc_iotiming  = s3c2410_iotiming_calc,
+        .set_iotiming   = s3c2410_iotiming_set,
+        .get_iotiming   = s3c2410_iotiming_get,
+        .resume_clocks  = s3c2410_setup_clocks,
+
+        .set_fvco       = s3c2410_set_fvco,
+        .set_refresh    = s3c2410_cpufreq_setrefresh,
+        .set_divs       = s3c2410_cpufreq_setdivs,
+        .calc_divs      = s3c2410_cpufreq_calcdivs,
+
+        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
+};
+
+static int s3c2410_cpufreq_add(struct device *dev,
+                               struct subsys_interface *sif)
+{
+        return s3c_cpufreq_register(&s3c2410_cpufreq_info);
+}
+
+static struct subsys_interface s3c2410_cpufreq_interface = {
+        .name           = "s3c2410_cpufreq",
+        .subsys         = &s3c2410_subsys,
+        .add_dev        = s3c2410_cpufreq_add,
+};
+
+static int __init s3c2410_cpufreq_init(void)
+{
+        return subsys_interface_register(&s3c2410_cpufreq_interface);
+}
+arch_initcall(s3c2410_cpufreq_init);
+
+static int s3c2410a_cpufreq_add(struct device *dev,
+                                struct subsys_interface *sif)
+{
+        /* alter the maximum freq settings for S3C2410A. If a board knows
+         * it only has a maximum of 200, then it should register its own
+         * limits. */
+
+        s3c2410_cpufreq_info.max.fclk = 266000000;
+        s3c2410_cpufreq_info.max.hclk = 133000000;
+        s3c2410_cpufreq_info.max.pclk =  66500000;
+        s3c2410_cpufreq_info.name = "s3c2410a";
+
+        return s3c2410_cpufreq_add(dev, sif);
+}
+
+static struct subsys_interface s3c2410a_cpufreq_interface = {
+        .name           = "s3c2410a_cpufreq",
+        .subsys         = &s3c2410a_subsys,
+        .add_dev        = s3c2410a_cpufreq_add,
+};
+
+static int __init s3c2410a_cpufreq_init(void)
+{
+        return subsys_interface_register(&s3c2410a_cpufreq_interface);
+}
+arch_initcall(s3c2410a_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
new file mode 100644
index 000000000000..c8f05f309eee
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
@@ -0,0 +1,257 @@
+/*
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2412 CPU Frequency scalling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-s3c2412-mem.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/cpu-freq-core.h>
+
+/* our clock resources. */
+static struct clk *xtal;
+static struct clk *fclk;
+static struct clk *hclk;
+static struct clk *armclk;
+
+/* HDIV: 1, 2, 3, 4, 6, 8 */
+
+static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned int hdiv, pdiv, armdiv, dvs;
+        unsigned long hclk, fclk, armclk, armdiv_clk;
+        unsigned long hclk_max;
+
+        fclk = cfg->freq.fclk;
+        armclk = cfg->freq.armclk;
+        hclk_max = cfg->max.hclk;
+
+        /* We can't run hclk above armclk as at the best we have to
+         * have armclk and hclk in dvs mode. */
+
+        if (hclk_max > armclk)
+                hclk_max = armclk;
+
+        s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n",
+                     __func__, fclk, armclk, hclk_max);
+        s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n",
+                     __func__, cfg->freq.fclk, cfg->freq.armclk,
+                     cfg->freq.hclk, cfg->freq.pclk);
+
+        armdiv = fclk / armclk;
+
+        if (armdiv < 1)
+                armdiv = 1;
+        if (armdiv > 2)
+                armdiv = 2;
+
+        cfg->divs.arm_divisor = armdiv;
+        armdiv_clk = fclk / armdiv;
+
+        hdiv = armdiv_clk / hclk_max;
+        if (hdiv < 1)
+                hdiv = 1;
+
+        cfg->freq.hclk = hclk = armdiv_clk / hdiv;
+
+        /* set dvs depending on whether we reached armclk or not. */
+        cfg->divs.dvs = dvs = armclk < armdiv_clk;
+
+        /* update the actual armclk we achieved. */
+        cfg->freq.armclk = dvs ? hclk : armdiv_clk;
+
+        s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n",
+                     __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs);
+
+        if (hdiv > 4)
+                goto invalid;
+
+        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
+
+        if ((hclk / pdiv) > cfg->max.pclk)
+                pdiv++;
+
+        cfg->freq.pclk = hclk / pdiv;
+
+        s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
+
+        if (pdiv > 2)
+                goto invalid;
+
+        pdiv *= hdiv;
+
+        /* store the result, and then return */
+
+        cfg->divs.h_divisor = hdiv * armdiv;
+        cfg->divs.p_divisor = pdiv * armdiv;
+
+        return 0;
+
+invalid:
+        return -EINVAL;
+}
+
+static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long clkdiv;
+        unsigned long olddiv;
+
+        olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN);
+
+        /* clear off current clock info */
+
+        clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN;
+        clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK;
+        clkdiv &= ~S3C2412_CLKDIVN_PDIVN;
+
+        if (cfg->divs.arm_divisor == 2)
+                clkdiv |= S3C2412_CLKDIVN_ARMDIVN;
+
+        clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1);
+
+        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
+                clkdiv |= S3C2412_CLKDIVN_PDIVN;
+
+        s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
+        __raw_writel(clkdiv, S3C2410_CLKDIVN);
+
+        clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
+}
+
+static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
+{
+        struct s3c_cpufreq_board *board = cfg->board;
+        unsigned long refresh;
+
+        s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__,
+                     board->refresh, cfg->freq.hclk);
+
+        /* Reduce both the refresh time (in ns) and the frequency (in MHz)
+         * by 10 each to ensure that we do not overflow 32 bit numbers. This
+         * should work for HCLK up to 133MHz and refresh period up to 30usec.
+         */
+
+        refresh = (board->refresh / 10);
+        refresh *= (cfg->freq.hclk / 100);
+        refresh /= (1 * 1000 * 1000);   /* 10^6 */
+
+        s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh);
+        __raw_writel(refresh, S3C2412_REFRESH);
+}
+
+/* set the default cpu frequency information, based on an 200MHz part
+ * as we have no other way of detecting the speed rating in software.
+ */
+
+static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
+        .max            = {
+                .fclk   = 200000000,
+                .hclk   = 100000000,
+                .pclk   =  50000000,
+        },
+
+        .latency        = 5000000, /* 5ms */
+
+        .locktime_m     = 150,
+        .locktime_u     = 150,
+        .locktime_bits  = 16,
+
+        .name           = "s3c2412",
+        .set_refresh    = s3c2412_cpufreq_setrefresh,
+        .set_divs       = s3c2412_cpufreq_setdivs,
+        .calc_divs      = s3c2412_cpufreq_calcdivs,
+
+        .calc_iotiming  = s3c2412_iotiming_calc,
+        .set_iotiming   = s3c2412_iotiming_set,
+        .get_iotiming   = s3c2412_iotiming_get,
+
+        .resume_clocks  = s3c2412_setup_clocks,
+
+        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
+};
+
+static int s3c2412_cpufreq_add(struct device *dev,
+                               struct subsys_interface *sif)
+{
+        unsigned long fclk_rate;
+
+        hclk = clk_get(NULL, "hclk");
+        if (IS_ERR(hclk)) {
+                printk(KERN_ERR "%s: cannot find hclk clock\n", __func__);
+                return -ENOENT;
+        }
+
+        fclk = clk_get(NULL, "fclk");
+        if (IS_ERR(fclk)) {
+                printk(KERN_ERR "%s: cannot find fclk clock\n", __func__);
+                goto err_fclk;
+        }
+
+        fclk_rate = clk_get_rate(fclk);
+        if (fclk_rate > 200000000) {
+                printk(KERN_INFO
+                       "%s: fclk %ld MHz, assuming 266MHz capable part\n",
+                       __func__, fclk_rate / 1000000);
+                s3c2412_cpufreq_info.max.fclk = 266000000;
+                s3c2412_cpufreq_info.max.hclk = 133000000;
+                s3c2412_cpufreq_info.max.pclk =  66000000;
+        }
+
+        armclk = clk_get(NULL, "armclk");
+        if (IS_ERR(armclk)) {
+                printk(KERN_ERR "%s: cannot find arm clock\n", __func__);
+                goto err_armclk;
+        }
+
+        xtal = clk_get(NULL, "xtal");
+        if (IS_ERR(xtal)) {
+                printk(KERN_ERR "%s: cannot find xtal clock\n", __func__);
+                goto err_xtal;
+        }
+
+        return s3c_cpufreq_register(&s3c2412_cpufreq_info);
+
+err_xtal:
+        clk_put(armclk);
+err_armclk:
+        clk_put(fclk);
+err_fclk:
+        clk_put(hclk);
+
+        return -ENOENT;
+}
+
+static struct subsys_interface s3c2412_cpufreq_interface = {
+        .name           = "s3c2412_cpufreq",
+        .subsys         = &s3c2412_subsys,
+        .add_dev        = s3c2412_cpufreq_add,
+};
+
+static int s3c2412_cpufreq_init(void)
+{
+        return subsys_interface_register(&s3c2412_cpufreq_interface);
+}
+arch_initcall(s3c2412_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c
new file mode 100644
index 000000000000..72b2cc8a5a85
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c
@@ -0,0 +1,312 @@
+/*
+ * Copyright (c) 2006-2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@simtec.co.uk>
+ *
+ * S3C2440/S3C2442 CPU Frequency scaling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/regs-clock.h>
+
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+#include <plat/clock.h>
+
+static struct clk *xtal;
+static struct clk *fclk;
+static struct clk *hclk;
+static struct clk *armclk;
+
+/* HDIV: 1, 2, 3, 4, 6, 8 */
+
+static inline int within_khz(unsigned long a, unsigned long b)
+{
+        long diff = a - b;
+
+        return (diff >= -1000 && diff <= 1000);
+}
+
+/**
+ * s3c2440_cpufreq_calcdivs - calculate divider settings
+ * @cfg: The cpu frequency settings.
+ *
+ * Calcualte the divider values for the given frequency settings
+ * specified in @cfg. The values are stored in @cfg for later use
+ * by the relevant set routine if the request settings can be reached.
+ */
+int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned int hdiv, pdiv;
+        unsigned long hclk, fclk, armclk;
+        unsigned long hclk_max;
+
+        fclk = cfg->freq.fclk;
+        armclk = cfg->freq.armclk;
+        hclk_max = cfg->max.hclk;
+
+        s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n",
+                     __func__, fclk, armclk, hclk_max);
+
+        if (armclk > fclk) {
+                printk(KERN_WARNING "%s: armclk > fclk\n", __func__);
+                armclk = fclk;
+        }
+
+        /* if we are in DVS, we need HCLK to be <= ARMCLK */
+        if (armclk < fclk && armclk < hclk_max)
+                hclk_max = armclk;
+
+        for (hdiv = 1; hdiv < 9; hdiv++) {
+                if (hdiv == 5 || hdiv == 7)
+                        hdiv++;
+
+                hclk = (fclk / hdiv);
+                if (hclk <= hclk_max || within_khz(hclk, hclk_max))
+                        break;
+        }
+
+        s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv);
+
+        if (hdiv > 8)
+                goto invalid;
+
+        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
+
+        if ((hclk / pdiv) > cfg->max.pclk)
+                pdiv++;
+
+        s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
+
+        if (pdiv > 2)
+                goto invalid;
+
+        pdiv *= hdiv;
+
+        /* calculate a valid armclk */
+
+        if (armclk < hclk)
+                armclk = hclk;
+
+        /* if we're running armclk lower than fclk, this really means
+         * that the system should go into dvs mode, which means that
+         * armclk is connected to hclk. */
+        if (armclk < fclk) {
+                cfg->divs.dvs = 1;
+                armclk = hclk;
+        } else
+                cfg->divs.dvs = 0;
+
+        cfg->freq.armclk = armclk;
+
+        /* store the result, and then return */
+
+        cfg->divs.h_divisor = hdiv;
+        cfg->divs.p_divisor = pdiv;
+
+        return 0;
+
+ invalid:
+        return -EINVAL;
+}
+
+#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \
+                           S3C2440_CAMDIVN_HCLK4_HALF)
+
+/**
+ * s3c2440_cpufreq_setdivs - set the cpu frequency divider settings
+ * @cfg: The cpu frequency settings.
+ *
+ * Set the divisors from the settings in @cfg, which where generated
+ * during the calculation phase by s3c2440_cpufreq_calcdivs().
+ */
+static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long clkdiv, camdiv;
+
+        s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__,
+                     cfg->divs.h_divisor, cfg->divs.p_divisor);
+
+        clkdiv = __raw_readl(S3C2410_CLKDIVN);
+        camdiv = __raw_readl(S3C2440_CAMDIVN);
+
+        clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN);
+        camdiv &= ~CAMDIVN_HCLK_HALF;
+
+        switch (cfg->divs.h_divisor) {
+        case 1:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_1;
+                break;
+
+        case 2:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_2;
+                break;
+
+        case 6:
+                camdiv |= S3C2440_CAMDIVN_HCLK3_HALF;
+        case 3:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6;
+                break;
+
+        case 8:
+                camdiv |= S3C2440_CAMDIVN_HCLK4_HALF;
+        case 4:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8;
+                break;
+
+        default:
+                BUG();  /* we don't expect to get here. */
+        }
+
+        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
+                clkdiv |= S3C2440_CLKDIVN_PDIVN;
+
+        /* todo - set pclk. */
+
+        /* Write the divisors first with hclk intentionally halved so that
+         * when we write clkdiv we will under-frequency instead of over. We
+         * then make a short delay and remove the hclk halving if necessary.
+         */
+
+        __raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
+        __raw_writel(clkdiv, S3C2410_CLKDIVN);
+
+        ndelay(20);
+        __raw_writel(camdiv, S3C2440_CAMDIVN);
+
+        clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
+}
+
+static int run_freq_for(unsigned long max_hclk, unsigned long fclk,
+                        int *divs,
+                        struct cpufreq_frequency_table *table,
+                        size_t table_size)
+{
+        unsigned long freq;
+        int index = 0;
+        int div;
+
+        for (div = *divs; div > 0; div = *divs++) {
+                freq = fclk / div;
+
+                if (freq > max_hclk && div != 1)
+                        continue;
+
+                freq /= 1000; /* table is in kHz */
+                index = s3c_cpufreq_addfreq(table, index, table_size, freq);
+                if (index < 0)
+                        break;
+        }
+
+        return index;
+}
+
+static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 };
+
+static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg,
+                                     struct cpufreq_frequency_table *table,
+                                     size_t table_size)
+{
+        int ret;
+
+        WARN_ON(cfg->info == NULL);
+        WARN_ON(cfg->board == NULL);
+
+        ret = run_freq_for(cfg->info->max.hclk,
+                           cfg->info->max.fclk,
+                           hclk_divs,
+                           table, table_size);
+
+        s3c_freq_dbg("%s: returning %d\n", __func__, ret);
+
+        return ret;
+}
+
+struct s3c_cpufreq_info s3c2440_cpufreq_info = {
+        .max            = {
+                .fclk   = 400000000,
+                .hclk   = 133333333,
+                .pclk   =  66666666,
+        },
+
+        .locktime_m     = 300,
+        .locktime_u     = 300,
+        .locktime_bits  = 16,
+
+        .name           = "s3c244x",
+        .calc_iotiming  = s3c2410_iotiming_calc,
+        .set_iotiming   = s3c2410_iotiming_set,
+        .get_iotiming   = s3c2410_iotiming_get,
+        .set_fvco       = s3c2410_set_fvco,
+
+        .set_refresh    = s3c2410_cpufreq_setrefresh,
+        .set_divs       = s3c2440_cpufreq_setdivs,
+        .calc_divs      = s3c2440_cpufreq_calcdivs,
+        .calc_freqtable = s3c2440_cpufreq_calctable,
+
+        .resume_clocks  = s3c244x_setup_clocks,
+
+        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
+};
+
+static int s3c2440_cpufreq_add(struct device *dev,
+                               struct subsys_interface *sif)
+{
+        xtal = s3c_cpufreq_clk_get(NULL, "xtal");
+        hclk = s3c_cpufreq_clk_get(NULL, "hclk");
+        fclk = s3c_cpufreq_clk_get(NULL, "fclk");
+        armclk = s3c_cpufreq_clk_get(NULL, "armclk");
+
+        if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) {
+                printk(KERN_ERR "%s: failed to get clocks\n", __func__);
+                return -ENOENT;
+        }
+
+        return s3c_cpufreq_register(&s3c2440_cpufreq_info);
+}
+
+static struct subsys_interface s3c2440_cpufreq_interface = {
+        .name           = "s3c2440_cpufreq",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c2440_cpufreq_add,
+};
+
+static int s3c2440_cpufreq_init(void)
+{
+        return subsys_interface_register(&s3c2440_cpufreq_interface);
+}
+
+/* arch_initcall adds the clocks we need, so use subsys_initcall. */
+subsys_initcall(s3c2440_cpufreq_init);
+
+static struct subsys_interface s3c2442_cpufreq_interface = {
+        .name           = "s3c2442_cpufreq",
+        .subsys         = &s3c2442_subsys,
+        .add_dev        = s3c2440_cpufreq_add,
+};
+
+static int s3c2442_cpufreq_init(void)
+{
+        return subsys_interface_register(&s3c2442_cpufreq_interface);
+}
+subsys_initcall(s3c2442_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/include/mach/hardware.h b/arch/arm/mach-s3c24xx/include/mach/hardware.h
index aef5631eac58..a6cc14a092fc 100644
--- a/arch/arm/mach-s3c24xx/include/mach/hardware.h
+++ b/arch/arm/mach-s3c24xx/include/mach/hardware.h
@@ -23,12 +23,6 @@ extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
 
 #endif /* CONFIG_CPU_S3C2440 */
 
-#ifdef CONFIG_CPU_S3C2412
-
-extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state);
-
-#endif /* CONFIG_CPU_S3C2412 */
-
 #endif /* __ASSEMBLY__ */
 
 #include <asm/sizes.h>
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2410.c b/arch/arm/mach-s3c24xx/pll-s3c2410.c
new file mode 100644
index 000000000000..dcf3420a3271
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/pll-s3c2410.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2006-2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@arm.linux.org.uk>
+ *
+ * S3C2410 CPU PLL tables
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+
+static struct cpufreq_frequency_table pll_vals_12MHz[] = {
+    { .frequency = 34000000,  .index = PLLVAL(82, 2, 3),   },
+    { .frequency = 45000000,  .index = PLLVAL(82, 1, 3),   },
+    { .frequency = 51000000,  .index = PLLVAL(161, 3, 3),  },
+    { .frequency = 48000000,  .index = PLLVAL(120, 2, 3),  },
+    { .frequency = 56000000,  .index = PLLVAL(142, 2, 3),  },
+    { .frequency = 68000000,  .index = PLLVAL(82, 2, 2),   },
+    { .frequency = 79000000,  .index = PLLVAL(71, 1, 2),   },
+    { .frequency = 85000000,  .index = PLLVAL(105, 2, 2),  },
+    { .frequency = 90000000,  .index = PLLVAL(112, 2, 2),  },
+    { .frequency = 101000000, .index = PLLVAL(127, 2, 2),  },
+    { .frequency = 113000000, .index = PLLVAL(105, 1, 2),  },
+    { .frequency = 118000000, .index = PLLVAL(150, 2, 2),  },
+    { .frequency = 124000000, .index = PLLVAL(116, 1, 2),  },
+    { .frequency = 135000000, .index = PLLVAL(82, 2, 1),   },
+    { .frequency = 147000000, .index = PLLVAL(90, 2, 1),   },
+    { .frequency = 152000000, .index = PLLVAL(68, 1, 1),   },
+    { .frequency = 158000000, .index = PLLVAL(71, 1, 1),   },
+    { .frequency = 170000000, .index = PLLVAL(77, 1, 1),   },
+    { .frequency = 180000000, .index = PLLVAL(82, 1, 1),   },
+    { .frequency = 186000000, .index = PLLVAL(85, 1, 1),   },
+    { .frequency = 192000000, .index = PLLVAL(88, 1, 1),   },
+    { .frequency = 203000000, .index = PLLVAL(161, 3, 1),  },
+
+    /* 2410A extras */
+
+    { .frequency = 210000000, .index = PLLVAL(132, 2, 1),  },
+    { .frequency = 226000000, .index = PLLVAL(105, 1, 1),  },
+    { .frequency = 266000000, .index = PLLVAL(125, 1, 1),  },
+    { .frequency = 268000000, .index = PLLVAL(126, 1, 1),  },
+    { .frequency = 270000000, .index = PLLVAL(127, 1, 1),  },
+};
+
+static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
+{
+        return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
+}
+
+static struct subsys_interface s3c2410_plls_interface = {
+        .name           = "s3c2410_plls",
+        .subsys         = &s3c2410_subsys,
+        .add_dev        = s3c2410_plls_add,
+};
+
+static int __init s3c2410_pll_init(void)
+{
+        return subsys_interface_register(&s3c2410_plls_interface);
+
+}
+arch_initcall(s3c2410_pll_init);
+
+static struct subsys_interface s3c2410a_plls_interface = {
+        .name           = "s3c2410a_plls",
+        .subsys         = &s3c2410a_subsys,
+        .add_dev        = s3c2410_plls_add,
+};
+
+static int __init s3c2410a_pll_init(void)
+{
+        return subsys_interface_register(&s3c2410a_plls_interface);
+}
+arch_initcall(s3c2410a_pll_init);
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
new file mode 100644
index 000000000000..673781758319
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2006-2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@arm.linux.org.uk>
+ *
+ * S3C2440/S3C2442 CPU PLL tables (12MHz Crystal)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+
+static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
+        { .frequency = 75000000,        .index = PLLVAL(0x75, 3, 3),  },        /* FVco 600.000000 */
+        { .frequency = 80000000,        .index = PLLVAL(0x98, 4, 3),  },        /* FVco 640.000000 */
+        { .frequency = 90000000,        .index = PLLVAL(0x70, 2, 3),  },        /* FVco 720.000000 */
+        { .frequency = 100000000,       .index = PLLVAL(0x5c, 1, 3),  },        /* FVco 800.000000 */
+        { .frequency = 110000000,       .index = PLLVAL(0x66, 1, 3),  },        /* FVco 880.000000 */
+        { .frequency = 120000000,       .index = PLLVAL(0x70, 1, 3),  },        /* FVco 960.000000 */
+        { .frequency = 150000000,       .index = PLLVAL(0x75, 3, 2),  },        /* FVco 600.000000 */
+        { .frequency = 160000000,       .index = PLLVAL(0x98, 4, 2),  },        /* FVco 640.000000 */
+        { .frequency = 170000000,       .index = PLLVAL(0x4d, 1, 2),  },        /* FVco 680.000000 */
+        { .frequency = 180000000,       .index = PLLVAL(0x70, 2, 2),  },        /* FVco 720.000000 */
+        { .frequency = 190000000,       .index = PLLVAL(0x57, 1, 2),  },        /* FVco 760.000000 */
+        { .frequency = 200000000,       .index = PLLVAL(0x5c, 1, 2),  },        /* FVco 800.000000 */
+        { .frequency = 210000000,       .index = PLLVAL(0x84, 2, 2),  },        /* FVco 840.000000 */
+        { .frequency = 220000000,       .index = PLLVAL(0x66, 1, 2),  },        /* FVco 880.000000 */
+        { .frequency = 230000000,       .index = PLLVAL(0x6b, 1, 2),  },        /* FVco 920.000000 */
+        { .frequency = 240000000,       .index = PLLVAL(0x70, 1, 2),  },        /* FVco 960.000000 */
+        { .frequency = 300000000,       .index = PLLVAL(0x75, 3, 1),  },        /* FVco 600.000000 */
+        { .frequency = 310000000,       .index = PLLVAL(0x93, 4, 1),  },        /* FVco 620.000000 */
+        { .frequency = 320000000,       .index = PLLVAL(0x98, 4, 1),  },        /* FVco 640.000000 */
+        { .frequency = 330000000,       .index = PLLVAL(0x66, 2, 1),  },        /* FVco 660.000000 */
+        { .frequency = 340000000,       .index = PLLVAL(0x4d, 1, 1),  },        /* FVco 680.000000 */
+        { .frequency = 350000000,       .index = PLLVAL(0xa7, 4, 1),  },        /* FVco 700.000000 */
+        { .frequency = 360000000,       .index = PLLVAL(0x70, 2, 1),  },        /* FVco 720.000000 */
+        { .frequency = 370000000,       .index = PLLVAL(0xb1, 4, 1),  },        /* FVco 740.000000 */
+        { .frequency = 380000000,       .index = PLLVAL(0x57, 1, 1),  },        /* FVco 760.000000 */
+        { .frequency = 390000000,       .index = PLLVAL(0x7a, 2, 1),  },        /* FVco 780.000000 */
+        { .frequency = 400000000,       .index = PLLVAL(0x5c, 1, 1),  },        /* FVco 800.000000 */
+};
+
+static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
+{
+        struct clk *xtal_clk;
+        unsigned long xtal;
+
+        xtal_clk = clk_get(NULL, "xtal");
+        if (IS_ERR(xtal_clk))
+                return PTR_ERR(xtal_clk);
+
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        if (xtal == 12000000) {
+                printk(KERN_INFO "Using PLL table for 12MHz crystal\n");
+                return s3c_plltab_register(s3c2440_plls_12,
+                                           ARRAY_SIZE(s3c2440_plls_12));
+        }
+
+        return 0;
+}
+
+static struct subsys_interface s3c2440_plls12_interface = {
+        .name           = "s3c2440_plls12",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c2440_plls12_add,
+};
+
+static int __init s3c2440_pll_12mhz(void)
+{
+        return subsys_interface_register(&s3c2440_plls12_interface);
+
+}
+arch_initcall(s3c2440_pll_12mhz);
+
+static struct subsys_interface s3c2442_plls12_interface = {
+        .name           = "s3c2442_plls12",
+        .subsys         = &s3c2442_subsys,
+        .add_dev        = s3c2440_plls12_add,
+};
+
+static int __init s3c2442_pll_12mhz(void)
+{
+        return subsys_interface_register(&s3c2442_plls12_interface);
+
+}
+arch_initcall(s3c2442_pll_12mhz);
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
new file mode 100644
index 000000000000..debfa106289b
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2006-2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@arm.linux.org.uk>
+ *
+ * S3C2440/S3C2442 CPU PLL tables (16.93444MHz Crystal)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+
+static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
+        { .frequency = 78019200,        .index = PLLVAL(121, 5, 3),     },      /* FVco 624.153600 */
+        { .frequency = 84067200,        .index = PLLVAL(131, 5, 3),     },      /* FVco 672.537600 */
+        { .frequency = 90115200,        .index = PLLVAL(141, 5, 3),     },      /* FVco 720.921600 */
+        { .frequency = 96163200,        .index = PLLVAL(151, 5, 3),     },      /* FVco 769.305600 */
+        { .frequency = 102135600,       .index = PLLVAL(185, 6, 3),     },      /* FVco 817.084800 */
+        { .frequency = 108259200,       .index = PLLVAL(171, 5, 3),     },      /* FVco 866.073600 */
+        { .frequency = 114307200,       .index = PLLVAL(127, 3, 3),     },      /* FVco 914.457600 */
+        { .frequency = 120234240,       .index = PLLVAL(134, 3, 3),     },      /* FVco 961.873920 */
+        { .frequency = 126161280,       .index = PLLVAL(141, 3, 3),     },      /* FVco 1009.290240 */
+        { .frequency = 132088320,       .index = PLLVAL(148, 3, 3),     },      /* FVco 1056.706560 */
+        { .frequency = 138015360,       .index = PLLVAL(155, 3, 3),     },      /* FVco 1104.122880 */
+        { .frequency = 144789120,       .index = PLLVAL(163, 3, 3),     },      /* FVco 1158.312960 */
+        { .frequency = 150100363,       .index = PLLVAL(187, 9, 2),     },      /* FVco 600.401454 */
+        { .frequency = 156038400,       .index = PLLVAL(121, 5, 2),     },      /* FVco 624.153600 */
+        { .frequency = 162086400,       .index = PLLVAL(126, 5, 2),     },      /* FVco 648.345600 */
+        { .frequency = 168134400,       .index = PLLVAL(131, 5, 2),     },      /* FVco 672.537600 */
+        { .frequency = 174048000,       .index = PLLVAL(177, 7, 2),     },      /* FVco 696.192000 */
+        { .frequency = 180230400,       .index = PLLVAL(141, 5, 2),     },      /* FVco 720.921600 */
+        { .frequency = 186278400,       .index = PLLVAL(124, 4, 2),     },      /* FVco 745.113600 */
+        { .frequency = 192326400,       .index = PLLVAL(151, 5, 2),     },      /* FVco 769.305600 */
+        { .frequency = 198132480,       .index = PLLVAL(109, 3, 2),     },      /* FVco 792.529920 */
+        { .frequency = 204271200,       .index = PLLVAL(185, 6, 2),     },      /* FVco 817.084800 */
+        { .frequency = 210268800,       .index = PLLVAL(141, 4, 2),     },      /* FVco 841.075200 */
+        { .frequency = 216518400,       .index = PLLVAL(171, 5, 2),     },      /* FVco 866.073600 */
+        { .frequency = 222264000,       .index = PLLVAL(97, 2, 2),      },      /* FVco 889.056000 */
+        { .frequency = 228614400,       .index = PLLVAL(127, 3, 2),     },      /* FVco 914.457600 */
+        { .frequency = 234259200,       .index = PLLVAL(158, 4, 2),     },      /* FVco 937.036800 */
+        { .frequency = 240468480,       .index = PLLVAL(134, 3, 2),     },      /* FVco 961.873920 */
+        { .frequency = 246960000,       .index = PLLVAL(167, 4, 2),     },      /* FVco 987.840000 */
+        { .frequency = 252322560,       .index = PLLVAL(141, 3, 2),     },      /* FVco 1009.290240 */
+        { .frequency = 258249600,       .index = PLLVAL(114, 2, 2),     },      /* FVco 1032.998400 */
+        { .frequency = 264176640,       .index = PLLVAL(148, 3, 2),     },      /* FVco 1056.706560 */
+        { .frequency = 270950400,       .index = PLLVAL(120, 2, 2),     },      /* FVco 1083.801600 */
+        { .frequency = 276030720,       .index = PLLVAL(155, 3, 2),     },      /* FVco 1104.122880 */
+        { .frequency = 282240000,       .index = PLLVAL(92, 1, 2),      },      /* FVco 1128.960000 */
+        { .frequency = 289578240,       .index = PLLVAL(163, 3, 2),     },      /* FVco 1158.312960 */
+        { .frequency = 294235200,       .index = PLLVAL(131, 2, 2),     },      /* FVco 1176.940800 */
+        { .frequency = 300200727,       .index = PLLVAL(187, 9, 1),     },      /* FVco 600.401454 */
+        { .frequency = 306358690,       .index = PLLVAL(191, 9, 1),     },      /* FVco 612.717380 */
+        { .frequency = 312076800,       .index = PLLVAL(121, 5, 1),     },      /* FVco 624.153600 */
+        { .frequency = 318366720,       .index = PLLVAL(86, 3, 1),      },      /* FVco 636.733440 */
+        { .frequency = 324172800,       .index = PLLVAL(126, 5, 1),     },      /* FVco 648.345600 */
+        { .frequency = 330220800,       .index = PLLVAL(109, 4, 1),     },      /* FVco 660.441600 */
+        { .frequency = 336268800,       .index = PLLVAL(131, 5, 1),     },      /* FVco 672.537600 */
+        { .frequency = 342074880,       .index = PLLVAL(93, 3, 1),      },      /* FVco 684.149760 */
+        { .frequency = 348096000,       .index = PLLVAL(177, 7, 1),     },      /* FVco 696.192000 */
+        { .frequency = 355622400,       .index = PLLVAL(118, 4, 1),     },      /* FVco 711.244800 */
+        { .frequency = 360460800,       .index = PLLVAL(141, 5, 1),     },      /* FVco 720.921600 */
+        { .frequency = 366206400,       .index = PLLVAL(165, 6, 1),     },      /* FVco 732.412800 */
+        { .frequency = 372556800,       .index = PLLVAL(124, 4, 1),     },      /* FVco 745.113600 */
+        { .frequency = 378201600,       .index = PLLVAL(126, 4, 1),     },      /* FVco 756.403200 */
+        { .frequency = 384652800,       .index = PLLVAL(151, 5, 1),     },      /* FVco 769.305600 */
+        { .frequency = 391608000,       .index = PLLVAL(177, 6, 1),     },      /* FVco 783.216000 */
+        { .frequency = 396264960,       .index = PLLVAL(109, 3, 1),     },      /* FVco 792.529920 */
+        { .frequency = 402192000,       .index = PLLVAL(87, 2, 1),      },      /* FVco 804.384000 */
+};
+
+static int s3c2440_plls169344_add(struct device *dev,
+                                  struct subsys_interface *sif)
+{
+        struct clk *xtal_clk;
+        unsigned long xtal;
+
+        xtal_clk = clk_get(NULL, "xtal");
+        if (IS_ERR(xtal_clk))
+                return PTR_ERR(xtal_clk);
+
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+
+        if (xtal == 169344000) {
+                printk(KERN_INFO "Using PLL table for 16.9344MHz crystal\n");
+                return s3c_plltab_register(s3c2440_plls_169344,
+                                           ARRAY_SIZE(s3c2440_plls_169344));
+        }
+
+        return 0;
+}
+
+static struct subsys_interface s3c2440_plls169344_interface = {
+        .name           = "s3c2440_plls169344",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c2440_plls169344_add,
+};
+
+static int __init s3c2440_pll_16934400(void)
+{
+        return subsys_interface_register(&s3c2440_plls169344_interface);
+}
+arch_initcall(s3c2440_pll_16934400);
+
+static struct subsys_interface s3c2442_plls169344_interface = {
+        .name           = "s3c2442_plls169344",
+        .subsys         = &s3c2442_subsys,
+        .add_dev        = s3c2440_plls169344_add,
+};
+
+static int __init s3c2442_pll_16934400(void)
+{
+        return subsys_interface_register(&s3c2442_plls169344_interface);
+}
+arch_initcall(s3c2442_pll_16934400);