Merge branch 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull locking updates from Ingo Molnar:
 "The locking tree was busier in this cycle than the usual pattern - a
  couple of major projects happened to coincide.

  The main changes are:

   - implement the atomic_fetch_{add,sub,and,or,xor}() API natively
     across all SMP architectures (Peter Zijlstra)

   - add atomic_fetch_{inc/dec}() as well, using the generic primitives
     (Davidlohr Bueso)

   - optimize various aspects of rwsems (Jason Low, Davidlohr Bueso,
     Waiman Long)

   - optimize smp_cond_load_acquire() on arm64 and implement LSE based
     atomic{,64}_fetch_{add,sub,and,andnot,or,xor}{,_relaxed,_acquire,_release}()
     on arm64 (Will Deacon)

   - introduce smp_acquire__after_ctrl_dep() and fix various barrier
     mis-uses and bugs (Peter Zijlstra)

   - after discovering ancient spin_unlock_wait() barrier bugs in its
     implementation and usage, strengthen its semantics and update/fix
     usage sites (Peter Zijlstra)

   - optimize mutex_trylock() fastpath (Peter Zijlstra)

   - ... misc fixes and cleanups"

* 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (67 commits)
  locking/atomic: Introduce inc/dec variants for the atomic_fetch_$op() API
  locking/barriers, arch/arm64: Implement LDXR+WFE based smp_cond_load_acquire()
  locking/static_keys: Fix non static symbol Sparse warning
  locking/qspinlock: Use __this_cpu_dec() instead of full-blown this_cpu_dec()
  locking/atomic, arch/tile: Fix tilepro build
  locking/atomic, arch/m68k: Remove comment
  locking/atomic, arch/arc: Fix build
  locking/Documentation: Clarify limited control-dependency scope
  locking/atomic, arch/rwsem: Employ atomic_long_fetch_add()
  locking/atomic, arch/qrwlock: Employ atomic_fetch_add_acquire()
  locking/atomic, arch/mips: Convert to _relaxed atomics
  locking/atomic, arch/alpha: Convert to _relaxed atomics
  locking/atomic: Remove the deprecated atomic_{set,clear}_mask() functions
  locking/atomic: Remove linux/atomic.h:atomic_fetch_or()
  locking/atomic: Implement atomic{,64,_long}_fetch_{add,sub,and,andnot,or,xor}{,_relaxed,_acquire,_release}()
  locking/atomic: Fix atomic64_relaxed() bits
  locking/atomic, arch/xtensa: Implement atomic_fetch_{add,sub,and,or,xor}()
  locking/atomic, arch/x86: Implement atomic{,64}_fetch_{add,sub,and,or,xor}()
  locking/atomic, arch/tile: Implement atomic{,64}_fetch_{add,sub,and,or,xor}()
  locking/atomic, arch/sparc: Implement atomic{,64}_fetch_{add,sub,and,or,xor}()
  ...

3 files changed, 92 insertions, 72 deletions

diff --git a/arch/alpha/include/asm/atomic.h b/arch/alpha/include/asm/atomic.h
index 572b228c44c7..498933a7df97 100644
--- a/arch/alpha/include/asm/atomic.h
+++ b/arch/alpha/include/asm/atomic.h
@@ -46,10 +46,9 @@ static __inline__ void atomic_##op(int i, atomic_t * v)			\
 }                                                                       \
 
 #define ATOMIC_OP_RETURN(op, asm_op)                                    \
-static inline int atomic_##op##_return(int i, atomic_t *v)              \
+static inline int atomic_##op##_return_relaxed(int i, atomic_t *v)      \
 {                                                                       \
         long temp, result;                                              \
-        smp_mb();                                                       \
         __asm__ __volatile__(                                           \
         "1:     ldl_l %0,%1\n"                                          \
         "       " #asm_op " %0,%3,%2\n"                                 \
@@ -61,7 +60,23 @@ static inline int atomic_##op##_return(int i, atomic_t *v)		\
         ".previous"                                                     \
         :"=&r" (temp), "=m" (v->counter), "=&r" (result)                \
         :"Ir" (i), "m" (v->counter) : "memory");                        \
-        smp_mb();                                                       \
+        return result;                                                  \
+}
+
+#define ATOMIC_FETCH_OP(op, asm_op)                                     \
+static inline int atomic_fetch_##op##_relaxed(int i, atomic_t *v)       \
+{                                                                       \
+        long temp, result;                                              \
+        __asm__ __volatile__(                                           \
+        "1:     ldl_l %2,%1\n"                                          \
+        "       " #asm_op " %2,%3,%0\n"                                 \
+        "       stl_c %0,%1\n"                                          \
+        "       beq %0,2f\n"                                            \
+        ".subsection 2\n"                                               \
+        "2:     br 1b\n"                                                \
+        ".previous"                                                     \
+        :"=&r" (temp), "=m" (v->counter), "=&r" (result)                \
+        :"Ir" (i), "m" (v->counter) : "memory");                        \
         return result;                                                  \
 }
 
@@ -82,10 +97,9 @@ static __inline__ void atomic64_##op(long i, atomic64_t * v)		\
 }                                                                       \
 
 #define ATOMIC64_OP_RETURN(op, asm_op)                                  \
-static __inline__ long atomic64_##op##_return(long i, atomic64_t * v)   \
+static __inline__ long atomic64_##op##_return_relaxed(long i, atomic64_t * v)   \
 {                                                                       \
         long temp, result;                                              \
-        smp_mb();                                                       \
         __asm__ __volatile__(                                           \
         "1:     ldq_l %0,%1\n"                                          \
         "       " #asm_op " %0,%3,%2\n"                                 \
@@ -97,34 +111,77 @@ static __inline__ long atomic64_##op##_return(long i, atomic64_t * v)	\
         ".previous"                                                     \
         :"=&r" (temp), "=m" (v->counter), "=&r" (result)                \
         :"Ir" (i), "m" (v->counter) : "memory");                        \
-        smp_mb();                                                       \
+        return result;                                                  \
+}
+
+#define ATOMIC64_FETCH_OP(op, asm_op)                                   \
+static __inline__ long atomic64_fetch_##op##_relaxed(long i, atomic64_t * v)    \
+{                                                                       \
+        long temp, result;                                              \
+        __asm__ __volatile__(                                           \
+        "1:     ldq_l %2,%1\n"                                          \
+        "       " #asm_op " %2,%3,%0\n"                                 \
+        "       stq_c %0,%1\n"                                          \
+        "       beq %0,2f\n"                                            \
+        ".subsection 2\n"                                               \
+        "2:     br 1b\n"                                                \
+        ".previous"                                                     \
+        :"=&r" (temp), "=m" (v->counter), "=&r" (result)                \
+        :"Ir" (i), "m" (v->counter) : "memory");                        \
         return result;                                                  \
 }
 
 #define ATOMIC_OPS(op)                                                  \
         ATOMIC_OP(op, op##l)                                            \
         ATOMIC_OP_RETURN(op, op##l)                                     \
+        ATOMIC_FETCH_OP(op, op##l)                                      \
         ATOMIC64_OP(op, op##q)                                          \
-        ATOMIC64_OP_RETURN(op, op##q)
+        ATOMIC64_OP_RETURN(op, op##q)                                   \
+        ATOMIC64_FETCH_OP(op, op##q)
 
 ATOMIC_OPS(add)
 ATOMIC_OPS(sub)
 
+#define atomic_add_return_relaxed       atomic_add_return_relaxed
+#define atomic_sub_return_relaxed       atomic_sub_return_relaxed
+#define atomic_fetch_add_relaxed        atomic_fetch_add_relaxed
+#define atomic_fetch_sub_relaxed        atomic_fetch_sub_relaxed
+
+#define atomic64_add_return_relaxed     atomic64_add_return_relaxed
+#define atomic64_sub_return_relaxed     atomic64_sub_return_relaxed
+#define atomic64_fetch_add_relaxed      atomic64_fetch_add_relaxed
+#define atomic64_fetch_sub_relaxed      atomic64_fetch_sub_relaxed
+
 #define atomic_andnot atomic_andnot
 #define atomic64_andnot atomic64_andnot
 
-ATOMIC_OP(and, and)
-ATOMIC_OP(andnot, bic)
-ATOMIC_OP(or, bis)
-ATOMIC_OP(xor, xor)
-ATOMIC64_OP(and, and)
-ATOMIC64_OP(andnot, bic)
-ATOMIC64_OP(or, bis)
-ATOMIC64_OP(xor, xor)
+#undef ATOMIC_OPS
+#define ATOMIC_OPS(op, asm)                                             \
+        ATOMIC_OP(op, asm)                                              \
+        ATOMIC_FETCH_OP(op, asm)                                        \
+        ATOMIC64_OP(op, asm)                                            \
+        ATOMIC64_FETCH_OP(op, asm)
+
+ATOMIC_OPS(and, and)
+ATOMIC_OPS(andnot, bic)
+ATOMIC_OPS(or, bis)
+ATOMIC_OPS(xor, xor)
+
+#define atomic_fetch_and_relaxed        atomic_fetch_and_relaxed
+#define atomic_fetch_andnot_relaxed     atomic_fetch_andnot_relaxed
+#define atomic_fetch_or_relaxed         atomic_fetch_or_relaxed
+#define atomic_fetch_xor_relaxed        atomic_fetch_xor_relaxed
+
+#define atomic64_fetch_and_relaxed      atomic64_fetch_and_relaxed
+#define atomic64_fetch_andnot_relaxed   atomic64_fetch_andnot_relaxed
+#define atomic64_fetch_or_relaxed       atomic64_fetch_or_relaxed
+#define atomic64_fetch_xor_relaxed      atomic64_fetch_xor_relaxed
 
 #undef ATOMIC_OPS
+#undef ATOMIC64_FETCH_OP
 #undef ATOMIC64_OP_RETURN
 #undef ATOMIC64_OP
+#undef ATOMIC_FETCH_OP
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
 
diff --git a/arch/alpha/include/asm/rwsem.h b/arch/alpha/include/asm/rwsem.h
index 0131a7058778..77873d0ad293 100644
--- a/arch/alpha/include/asm/rwsem.h
+++ b/arch/alpha/include/asm/rwsem.h
@@ -25,8 +25,8 @@ static inline void __down_read(struct rw_semaphore *sem)
 {
         long oldcount;
 #ifndef CONFIG_SMP
-        oldcount = sem->count;
-        sem->count += RWSEM_ACTIVE_READ_BIAS;
+        oldcount = sem->count.counter;
+        sem->count.counter += RWSEM_ACTIVE_READ_BIAS;
 #else
         long temp;
         __asm__ __volatile__(
@@ -52,13 +52,13 @@ static inline int __down_read_trylock(struct rw_semaphore *sem)
 {
         long old, new, res;
 
-        res = sem->count;
+        res = atomic_long_read(&sem->count);
         do {
                 new = res + RWSEM_ACTIVE_READ_BIAS;
                 if (new <= 0)
                         break;
                 old = res;
-                res = cmpxchg(&sem->count, old, new);
+                res = atomic_long_cmpxchg(&sem->count, old, new);
         } while (res != old);
         return res >= 0 ? 1 : 0;
 }
@@ -67,8 +67,8 @@ static inline long ___down_write(struct rw_semaphore *sem)
 {
         long oldcount;
 #ifndef CONFIG_SMP
-        oldcount = sem->count;
-        sem->count += RWSEM_ACTIVE_WRITE_BIAS;
+        oldcount = sem->count.counter;
+        sem->count.counter += RWSEM_ACTIVE_WRITE_BIAS;
 #else
         long temp;
         __asm__ __volatile__(
@@ -106,7 +106,7 @@ static inline int __down_write_killable(struct rw_semaphore *sem)
  */
 static inline int __down_write_trylock(struct rw_semaphore *sem)
 {
-        long ret = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
+        long ret = atomic_long_cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
                            RWSEM_ACTIVE_WRITE_BIAS);
         if (ret == RWSEM_UNLOCKED_VALUE)
                 return 1;
@@ -117,8 +117,8 @@ static inline void __up_read(struct rw_semaphore *sem)
 {
         long oldcount;
 #ifndef CONFIG_SMP
-        oldcount = sem->count;
-        sem->count -= RWSEM_ACTIVE_READ_BIAS;
+        oldcount = sem->count.counter;
+        sem->count.counter -= RWSEM_ACTIVE_READ_BIAS;
 #else
         long temp;
         __asm__ __volatile__(
@@ -142,8 +142,8 @@ static inline void __up_write(struct rw_semaphore *sem)
 {
         long count;
 #ifndef CONFIG_SMP
-        sem->count -= RWSEM_ACTIVE_WRITE_BIAS;
-        count = sem->count;
+        sem->count.counter -= RWSEM_ACTIVE_WRITE_BIAS;
+        count = sem->count.counter;
 #else
         long temp;
         __asm__ __volatile__(
@@ -171,8 +171,8 @@ static inline void __downgrade_write(struct rw_semaphore *sem)
 {
         long oldcount;
 #ifndef CONFIG_SMP
-        oldcount = sem->count;
-        sem->count -= RWSEM_WAITING_BIAS;
+        oldcount = sem->count.counter;
+        sem->count.counter -= RWSEM_WAITING_BIAS;
 #else
         long temp;
         __asm__ __volatile__(
@@ -191,47 +191,5 @@ static inline void __downgrade_write(struct rw_semaphore *sem)
                 rwsem_downgrade_wake(sem);
 }
 
-static inline void rwsem_atomic_add(long val, struct rw_semaphore *sem)
-{
-#ifndef CONFIG_SMP
-        sem->count += val;
-#else
-        long temp;
-        __asm__ __volatile__(
-        "1:     ldq_l   %0,%1\n"
-        "       addq    %0,%2,%0\n"
-        "       stq_c   %0,%1\n"
-        "       beq     %0,2f\n"
-        ".subsection 2\n"
-        "2:     br      1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (sem->count)
-        :"Ir" (val), "m" (sem->count));
-#endif
-}
-
-static inline long rwsem_atomic_update(long val, struct rw_semaphore *sem)
-{
-#ifndef CONFIG_SMP
-        sem->count += val;
-        return sem->count;
-#else
-        long ret, temp;
-        __asm__ __volatile__(
-        "1:     ldq_l   %0,%1\n"
-        "       addq    %0,%3,%2\n"
-        "       addq    %0,%3,%0\n"
-        "       stq_c   %2,%1\n"
-        "       beq     %2,2f\n"
-        ".subsection 2\n"
-        "2:     br      1b\n"
-        ".previous"
-        :"=&r" (ret), "=m" (sem->count), "=&r" (temp)
-        :"Ir" (val), "m" (sem->count));
-
-        return ret;
-#endif
-}
-
 #endif /* __KERNEL__ */
 #endif /* _ALPHA_RWSEM_H */
diff --git a/arch/alpha/include/asm/spinlock.h b/arch/alpha/include/asm/spinlock.h
index fed9c6f44c19..a40b9fc0c6c3 100644
--- a/arch/alpha/include/asm/spinlock.h
+++ b/arch/alpha/include/asm/spinlock.h
@@ -3,6 +3,8 @@
 
 #include <linux/kernel.h>
 #include <asm/current.h>
+#include <asm/barrier.h>
+#include <asm/processor.h>
 
 /*
  * Simple spin lock operations.  There are two variants, one clears IRQ's
@@ -13,8 +15,11 @@
 
 #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
 #define arch_spin_is_locked(x)  ((x)->lock != 0)
-#define arch_spin_unlock_wait(x) \
-                do { cpu_relax(); } while ((x)->lock)
+
+static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
+{
+        smp_cond_load_acquire(&lock->lock, !VAL);
+}
 
 static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
 {