diff options
author | Mike Turquette <mturquette@linaro.org> | 2014-07-31 12:32:18 -0400 |
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committer | Mike Turquette <mturquette@linaro.org> | 2014-07-31 12:32:18 -0400 |
commit | d7d3d26fa5446fc74e2c52504d827bda89b7b03e (patch) | |
tree | 209f3a0fe71af5a97ece45cee40c7e1a4f5495f3 /Documentation | |
parent | abeab450bfe823079c8a3abf5123f41a0da62392 (diff) | |
parent | f65d518942325d4bfa74b5c9d42ea5a89e4f6943 (diff) |
Merge tag 'for_3.17/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next-samsung
Samsung clock patches for 3.17
1) non-critical fixes (without need to push to stable):
d5e136a clk: samsung: Register clk provider only after registering its all clocks
305cfab clk: samsung: Make of_device_id array const
e9d5295 clk: samsung: exynos5420: Setup clocks before system suspend
f65d518 clk: samsung: trivial: Correct typo in author's name
2) Exynos CLKOUT driver:
800c979 clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy
01f7ec2 clk: samsung: exynos4: Add CLKOUT clock hierarchy
1e832e5 clk: samsung: Add driver to control CLKOUT line on Exynos SoCs
d19bb39 ARM: dts: exynos: Update PMU node with CLKOUT related data
3) Clock hierarchy extensions:
17d3f1d clk: exynos4: Add PPMU IP block source clocks.
ca5b402 clk: samsung: register exynos5420 apll/kpll configuration data
4) ARM CLKDOWN functionality enablement for Exynos4 and 3250:
42773b2 clk: samsung: exynos4: Enable ARMCLK down feature
45c5b0a clk: samsung: exynos3250: Enable ARMCLK down feature
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/arm/samsung/pmu.txt | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt index 2a4ab046a8a1..f9865e77e0b0 100644 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt | |||
@@ -12,8 +12,38 @@ Properties: | |||
12 | 12 | ||
13 | - reg : offset and length of the register set. | 13 | - reg : offset and length of the register set. |
14 | 14 | ||
15 | - #clock-cells : must be <1>, since PMU requires once cell as clock specifier. | ||
16 | The single specifier cell is used as index to list of clocks | ||
17 | provided by PMU, which is currently: | ||
18 | 0 : SoC clock output (CLKOUT pin) | ||
19 | |||
20 | - clock-names : list of clock names for particular CLKOUT mux inputs in | ||
21 | following format: | ||
22 | "clkoutN", where N is a decimal number corresponding to | ||
23 | CLKOUT mux control bits value for given input, e.g. | ||
24 | "clkout0", "clkout7", "clkout15". | ||
25 | |||
26 | - clocks : list of phandles and specifiers to all input clocks listed in | ||
27 | clock-names property. | ||
28 | |||
15 | Example : | 29 | Example : |
16 | pmu_system_controller: system-controller@10040000 { | 30 | pmu_system_controller: system-controller@10040000 { |
17 | compatible = "samsung,exynos5250-pmu", "syscon"; | 31 | compatible = "samsung,exynos5250-pmu", "syscon"; |
18 | reg = <0x10040000 0x5000>; | 32 | reg = <0x10040000 0x5000>; |
33 | #clock-cells = <1>; | ||
34 | clock-names = "clkout0", "clkout1", "clkout2", "clkout3", | ||
35 | "clkout4", "clkout8", "clkout9"; | ||
36 | clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, | ||
37 | <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, | ||
38 | <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, | ||
39 | <&clock CLK_XUSBXTI>; | ||
40 | }; | ||
41 | |||
42 | Example of clock consumer : | ||
43 | |||
44 | usb3503: usb3503@08 { | ||
45 | /* ... */ | ||
46 | clock-names = "refclk"; | ||
47 | clocks = <&pmu_system_controller 0>; | ||
48 | /* ... */ | ||
19 | }; | 49 | }; |