diff options
author | Chunfeng Yun <chunfeng.yun@mediatek.com> | 2019-08-28 04:22:13 -0400 |
---|---|---|
committer | Stephen Boyd <sboyd@kernel.org> | 2019-09-17 13:17:41 -0400 |
commit | f9e55ac22ce9246c085e1c97ddda93608ce17eaf (patch) | |
tree | 09011ba3258a423a575e06c1cfd5ae123b3d372f | |
parent | 5aa00ad3fd3338eba1ed8bbb1a142eb40f43d728 (diff) |
clk: mediatek: add pericfg clocks for MT8183
Add pericfg clocks for MT8183, it's used when support USB
remote wakeup
Cc: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lkml.kernel.org/r/1566980533-28282-2-git-send-email-chunfeng.yun@mediatek.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
-rw-r--r-- | drivers/clk/mediatek/clk-mt8183.c | 30 | ||||
-rw-r--r-- | include/dt-bindings/clock/mt8183-clk.h | 4 |
2 files changed, 34 insertions, 0 deletions
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 94bbadc0d259..7e7452e56694 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c | |||
@@ -1002,6 +1002,20 @@ static const struct mtk_gate infra_clks[] = { | |||
1002 | "msdc50_0_sel", 24), | 1002 | "msdc50_0_sel", 24), |
1003 | }; | 1003 | }; |
1004 | 1004 | ||
1005 | static const struct mtk_gate_regs peri_cg_regs = { | ||
1006 | .set_ofs = 0x20c, | ||
1007 | .clr_ofs = 0x20c, | ||
1008 | .sta_ofs = 0x20c, | ||
1009 | }; | ||
1010 | |||
1011 | #define GATE_PERI(_id, _name, _parent, _shift) \ | ||
1012 | GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \ | ||
1013 | &mtk_clk_gate_ops_no_setclr_inv) | ||
1014 | |||
1015 | static const struct mtk_gate peri_clks[] = { | ||
1016 | GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31), | ||
1017 | }; | ||
1018 | |||
1005 | static const struct mtk_gate_regs apmixed_cg_regs = { | 1019 | static const struct mtk_gate_regs apmixed_cg_regs = { |
1006 | .set_ofs = 0x20, | 1020 | .set_ofs = 0x20, |
1007 | .clr_ofs = 0x20, | 1021 | .clr_ofs = 0x20, |
@@ -1208,6 +1222,19 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev) | |||
1208 | return r; | 1222 | return r; |
1209 | } | 1223 | } |
1210 | 1224 | ||
1225 | static int clk_mt8183_peri_probe(struct platform_device *pdev) | ||
1226 | { | ||
1227 | struct clk_onecell_data *clk_data; | ||
1228 | struct device_node *node = pdev->dev.of_node; | ||
1229 | |||
1230 | clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); | ||
1231 | |||
1232 | mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), | ||
1233 | clk_data); | ||
1234 | |||
1235 | return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); | ||
1236 | } | ||
1237 | |||
1211 | static int clk_mt8183_mcu_probe(struct platform_device *pdev) | 1238 | static int clk_mt8183_mcu_probe(struct platform_device *pdev) |
1212 | { | 1239 | { |
1213 | struct clk_onecell_data *clk_data; | 1240 | struct clk_onecell_data *clk_data; |
@@ -1238,6 +1265,9 @@ static const struct of_device_id of_match_clk_mt8183[] = { | |||
1238 | .compatible = "mediatek,mt8183-infracfg", | 1265 | .compatible = "mediatek,mt8183-infracfg", |
1239 | .data = clk_mt8183_infra_probe, | 1266 | .data = clk_mt8183_infra_probe, |
1240 | }, { | 1267 | }, { |
1268 | .compatible = "mediatek,mt8183-pericfg", | ||
1269 | .data = clk_mt8183_peri_probe, | ||
1270 | }, { | ||
1241 | .compatible = "mediatek,mt8183-mcucfg", | 1271 | .compatible = "mediatek,mt8183-mcucfg", |
1242 | .data = clk_mt8183_mcu_probe, | 1272 | .data = clk_mt8183_mcu_probe, |
1243 | }, { | 1273 | }, { |
diff --git a/include/dt-bindings/clock/mt8183-clk.h b/include/dt-bindings/clock/mt8183-clk.h index 0046506eb24c..a7b470b0ec8a 100644 --- a/include/dt-bindings/clock/mt8183-clk.h +++ b/include/dt-bindings/clock/mt8183-clk.h | |||
@@ -284,6 +284,10 @@ | |||
284 | #define CLK_INFRA_FBIST2FPC 100 | 284 | #define CLK_INFRA_FBIST2FPC 100 |
285 | #define CLK_INFRA_NR_CLK 101 | 285 | #define CLK_INFRA_NR_CLK 101 |
286 | 286 | ||
287 | /* PERICFG */ | ||
288 | #define CLK_PERI_AXI 0 | ||
289 | #define CLK_PERI_NR_CLK 1 | ||
290 | |||
287 | /* MFGCFG */ | 291 | /* MFGCFG */ |
288 | #define CLK_MFG_BG3D 0 | 292 | #define CLK_MFG_BG3D 0 |
289 | #define CLK_MFG_NR_CLK 1 | 293 | #define CLK_MFG_NR_CLK 1 |