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authorGevorg Sahakyan <Gevorg.Sahakyan@synopsys.com>2018-07-26 10:00:13 -0400
committerFelipe Balbi <felipe.balbi@linux.intel.com>2018-07-30 03:39:16 -0400
commitf25c42b8d604fbca6d8d3eff2365a73bbef076d3 (patch)
tree7400ccbb88912e79db006043fb0103b7f1359bb3
parentc31d983beaf04e6754918aa1073f053b12efb700 (diff)
usb: dwc2: Modify dwc2_readl/writel functions prototype
Added hsotg argument to dwc2_readl/writel function prototype, and also instead of address pass offset of register. hsotg will contain flag field for endianness. Also customized dwc2_set_bit and dwc2_clear_bit function for dwc2_readl/writel functions. Signed-off-by: Gevorg Sahakyan <sahakyan@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat
-rw-r--r--drivers/usb/dwc2/core.c241
-rw-r--r--drivers/usb/dwc2/core.h25
-rw-r--r--drivers/usb/dwc2/core_intr.c118
-rw-r--r--drivers/usb/dwc2/debugfs.c55
-rw-r--r--drivers/usb/dwc2/gadget.c512
-rw-r--r--drivers/usb/dwc2/hcd.c459
-rw-r--r--drivers/usb/dwc2/hcd.h10
-rw-r--r--drivers/usb/dwc2/hcd_ddma.c10
-rw-r--r--drivers/usb/dwc2/hcd_intr.c96
-rw-r--r--drivers/usb/dwc2/hcd_queue.c10
-rw-r--r--drivers/usb/dwc2/params.c20
11 files changed, 776 insertions, 780 deletions
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index 1c36a6a9dd63..55d5ae2a7ec7 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -73,17 +73,17 @@ int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
73 /* Backup global regs */ 73 /* Backup global regs */
74 gr = &hsotg->gr_backup; 74 gr = &hsotg->gr_backup;
75 75
76 gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 76 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);
77 gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 77 gr->gintmsk = dwc2_readl(hsotg, GINTMSK);
78 gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 78 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);
79 gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 79 gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);
80 gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 80 gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
81 gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 81 gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
82 gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 82 gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
83 gr->pcgcctl1 = dwc2_readl(hsotg->regs + PCGCCTL1); 83 gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
84 gr->glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); 84 gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);
85 gr->gi2cctl = dwc2_readl(hsotg->regs + GI2CCTL); 85 gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);
86 gr->pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 86 gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);
87 87
88 gr->valid = true; 88 gr->valid = true;
89 return 0; 89 return 0;
@@ -111,18 +111,18 @@ int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
111 } 111 }
112 gr->valid = false; 112 gr->valid = false;
113 113
114 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 114 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
115 dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL); 115 dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);
116 dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK); 116 dwc2_writel(hsotg, gr->gintmsk, GINTMSK);
117 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); 117 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
118 dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG); 118 dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);
119 dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ); 119 dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
120 dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ); 120 dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
121 dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG); 121 dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
122 dwc2_writel(gr->pcgcctl1, hsotg->regs + PCGCCTL1); 122 dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
123 dwc2_writel(gr->glpmcfg, hsotg->regs + GLPMCFG); 123 dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
124 dwc2_writel(gr->pcgcctl, hsotg->regs + PCGCTL); 124 dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
125 dwc2_writel(gr->gi2cctl, hsotg->regs + GI2CCTL); 125 dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
126 126
127 return 0; 127 return 0;
128} 128}
@@ -141,17 +141,17 @@ int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore)
141 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) 141 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)
142 return -ENOTSUPP; 142 return -ENOTSUPP;
143 143
144 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 144 pcgcctl = dwc2_readl(hsotg, PCGCTL);
145 pcgcctl &= ~PCGCTL_STOPPCLK; 145 pcgcctl &= ~PCGCTL_STOPPCLK;
146 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 146 dwc2_writel(hsotg, pcgcctl, PCGCTL);
147 147
148 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 148 pcgcctl = dwc2_readl(hsotg, PCGCTL);
149 pcgcctl &= ~PCGCTL_PWRCLMP; 149 pcgcctl &= ~PCGCTL_PWRCLMP;
150 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 150 dwc2_writel(hsotg, pcgcctl, PCGCTL);
151 151
152 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 152 pcgcctl = dwc2_readl(hsotg, PCGCTL);
153 pcgcctl &= ~PCGCTL_RSTPDWNMODULE; 153 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
154 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 154 dwc2_writel(hsotg, pcgcctl, PCGCTL);
155 155
156 udelay(100); 156 udelay(100);
157 if (restore) { 157 if (restore) {
@@ -222,21 +222,21 @@ int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
222 * Clear any pending interrupts since dwc2 will not be able to 222 * Clear any pending interrupts since dwc2 will not be able to
223 * clear them after entering partial_power_down. 223 * clear them after entering partial_power_down.
224 */ 224 */
225 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 225 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
226 226
227 /* Put the controller in low power state */ 227 /* Put the controller in low power state */
228 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 228 pcgcctl = dwc2_readl(hsotg, PCGCTL);
229 229
230 pcgcctl |= PCGCTL_PWRCLMP; 230 pcgcctl |= PCGCTL_PWRCLMP;
231 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 231 dwc2_writel(hsotg, pcgcctl, PCGCTL);
232 ndelay(20); 232 ndelay(20);
233 233
234 pcgcctl |= PCGCTL_RSTPDWNMODULE; 234 pcgcctl |= PCGCTL_RSTPDWNMODULE;
235 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 235 dwc2_writel(hsotg, pcgcctl, PCGCTL);
236 ndelay(20); 236 ndelay(20);
237 237
238 pcgcctl |= PCGCTL_STOPPCLK; 238 pcgcctl |= PCGCTL_STOPPCLK;
239 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 239 dwc2_writel(hsotg, pcgcctl, PCGCTL);
240 240
241 return ret; 241 return ret;
242} 242}
@@ -272,39 +272,39 @@ static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
272 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK)) 272 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
273 pcgcctl |= BIT(17); 273 pcgcctl |= BIT(17);
274 } 274 }
275 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 275 dwc2_writel(hsotg, pcgcctl, PCGCTL);
276 276
277 /* Umnask global Interrupt in GAHBCFG and restore it */ 277 /* Umnask global Interrupt in GAHBCFG and restore it */
278 dwc2_writel(gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); 278 dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);
279 279
280 /* Clear all pending interupts */ 280 /* Clear all pending interupts */
281 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 281 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
282 282
283 /* Unmask restore done interrupt */ 283 /* Unmask restore done interrupt */
284 dwc2_writel(GINTSTS_RESTOREDONE, hsotg->regs + GINTMSK); 284 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK);
285 285
286 /* Restore GUSBCFG and HCFG/DCFG */ 286 /* Restore GUSBCFG and HCFG/DCFG */
287 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); 287 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
288 288
289 if (is_host) { 289 if (is_host) {
290 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 290 dwc2_writel(hsotg, hr->hcfg, HCFG);
291 if (rmode) 291 if (rmode)
292 pcgcctl |= PCGCTL_RESTOREMODE; 292 pcgcctl |= PCGCTL_RESTOREMODE;
293 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 293 dwc2_writel(hsotg, pcgcctl, PCGCTL);
294 udelay(10); 294 udelay(10);
295 295
296 pcgcctl |= PCGCTL_ESS_REG_RESTORED; 296 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
297 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 297 dwc2_writel(hsotg, pcgcctl, PCGCTL);
298 udelay(10); 298 udelay(10);
299 } else { 299 } else {
300 dwc2_writel(dr->dcfg, hsotg->regs + DCFG); 300 dwc2_writel(hsotg, dr->dcfg, DCFG);
301 if (!rmode) 301 if (!rmode)
302 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE; 302 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
303 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 303 dwc2_writel(hsotg, pcgcctl, PCGCTL);
304 udelay(10); 304 udelay(10);
305 305
306 pcgcctl |= PCGCTL_ESS_REG_RESTORED; 306 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
307 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 307 dwc2_writel(hsotg, pcgcctl, PCGCTL);
308 udelay(10); 308 udelay(10);
309 } 309 }
310} 310}
@@ -322,42 +322,42 @@ void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
322 u32 gpwrdn; 322 u32 gpwrdn;
323 323
324 /* Switch-on voltage to the core */ 324 /* Switch-on voltage to the core */
325 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 325 gpwrdn = dwc2_readl(hsotg, GPWRDN);
326 gpwrdn &= ~GPWRDN_PWRDNSWTCH; 326 gpwrdn &= ~GPWRDN_PWRDNSWTCH;
327 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 327 dwc2_writel(hsotg, gpwrdn, GPWRDN);
328 udelay(10); 328 udelay(10);
329 329
330 /* Reset core */ 330 /* Reset core */
331 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 331 gpwrdn = dwc2_readl(hsotg, GPWRDN);
332 gpwrdn &= ~GPWRDN_PWRDNRSTN; 332 gpwrdn &= ~GPWRDN_PWRDNRSTN;
333 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 333 dwc2_writel(hsotg, gpwrdn, GPWRDN);
334 udelay(10); 334 udelay(10);
335 335
336 /* Enable restore from PMU */ 336 /* Enable restore from PMU */
337 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 337 gpwrdn = dwc2_readl(hsotg, GPWRDN);
338 gpwrdn |= GPWRDN_RESTORE; 338 gpwrdn |= GPWRDN_RESTORE;
339 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 339 dwc2_writel(hsotg, gpwrdn, GPWRDN);
340 udelay(10); 340 udelay(10);
341 341
342 /* Disable Power Down Clamp */ 342 /* Disable Power Down Clamp */
343 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 343 gpwrdn = dwc2_readl(hsotg, GPWRDN);
344 gpwrdn &= ~GPWRDN_PWRDNCLMP; 344 gpwrdn &= ~GPWRDN_PWRDNCLMP;
345 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 345 dwc2_writel(hsotg, gpwrdn, GPWRDN);
346 udelay(50); 346 udelay(50);
347 347
348 if (!is_host && rem_wakeup) 348 if (!is_host && rem_wakeup)
349 udelay(70); 349 udelay(70);
350 350
351 /* Deassert reset core */ 351 /* Deassert reset core */
352 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 352 gpwrdn = dwc2_readl(hsotg, GPWRDN);
353 gpwrdn |= GPWRDN_PWRDNRSTN; 353 gpwrdn |= GPWRDN_PWRDNRSTN;
354 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 354 dwc2_writel(hsotg, gpwrdn, GPWRDN);
355 udelay(10); 355 udelay(10);
356 356
357 /* Disable PMU interrupt */ 357 /* Disable PMU interrupt */
358 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 358 gpwrdn = dwc2_readl(hsotg, GPWRDN);
359 gpwrdn &= ~GPWRDN_PMUINTSEL; 359 gpwrdn &= ~GPWRDN_PMUINTSEL;
360 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 360 dwc2_writel(hsotg, gpwrdn, GPWRDN);
361 udelay(10); 361 udelay(10);
362 362
363 /* Set Restore Essential Regs bit in PCGCCTL register */ 363 /* Set Restore Essential Regs bit in PCGCCTL register */
@@ -431,7 +431,7 @@ static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
431 return false; 431 return false;
432 432
433 /* Check if core configuration includes the IDDIG filter. */ 433 /* Check if core configuration includes the IDDIG filter. */
434 ghwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 434 ghwcfg4 = dwc2_readl(hsotg, GHWCFG4);
435 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN)) 435 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
436 return false; 436 return false;
437 437
@@ -439,9 +439,9 @@ static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
439 * Check if the IDDIG debounce filter is bypassed. Available 439 * Check if the IDDIG debounce filter is bypassed. Available
440 * in core version >= 3.10a. 440 * in core version >= 3.10a.
441 */ 441 */
442 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID); 442 gsnpsid = dwc2_readl(hsotg, GSNPSID);
443 if (gsnpsid >= DWC2_CORE_REV_3_10a) { 443 if (gsnpsid >= DWC2_CORE_REV_3_10a) {
444 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 444 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
445 445
446 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS) 446 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
447 return false; 447 return false;
@@ -510,8 +510,8 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
510 * reset and account for this delay after the reset. 510 * reset and account for this delay after the reset.
511 */ 511 */
512 if (dwc2_iddig_filter_enabled(hsotg)) { 512 if (dwc2_iddig_filter_enabled(hsotg)) {
513 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 513 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
514 u32 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 514 u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
515 515
516 if (!(gotgctl & GOTGCTL_CONID_B) || 516 if (!(gotgctl & GOTGCTL_CONID_B) ||
517 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) { 517 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
@@ -520,9 +520,9 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
520 } 520 }
521 521
522 /* Core Soft Reset */ 522 /* Core Soft Reset */
523 greset = dwc2_readl(hsotg->regs + GRSTCTL); 523 greset = dwc2_readl(hsotg, GRSTCTL);
524 greset |= GRSTCTL_CSFTRST; 524 greset |= GRSTCTL_CSFTRST;
525 dwc2_writel(greset, hsotg->regs + GRSTCTL); 525 dwc2_writel(hsotg, greset, GRSTCTL);
526 526
527 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 50)) { 527 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 50)) {
528 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL GRSTCTL_CSFTRST\n", 528 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL GRSTCTL_CSFTRST\n",
@@ -594,14 +594,14 @@ void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
594 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST)) 594 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
595 return; 595 return;
596 596
597 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 597 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
598 598
599 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE; 599 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
600 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE; 600 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
601 601
602 gusbcfg &= ~clear; 602 gusbcfg &= ~clear;
603 gusbcfg |= set; 603 gusbcfg |= set;
604 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); 604 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
605 605
606 dwc2_wait_for_mode(hsotg, host); 606 dwc2_wait_for_mode(hsotg, host);
607 return; 607 return;
@@ -627,10 +627,10 @@ static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
627 627
628 dev_dbg(hsotg->dev, "Clearing force mode bits\n"); 628 dev_dbg(hsotg->dev, "Clearing force mode bits\n");
629 629
630 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 630 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
631 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; 631 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
632 gusbcfg &= ~GUSBCFG_FORCEDEVMODE; 632 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
633 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); 633 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
634 634
635 if (dwc2_iddig_filter_enabled(hsotg)) 635 if (dwc2_iddig_filter_enabled(hsotg))
636 msleep(100); 636 msleep(100);
@@ -670,11 +670,11 @@ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
670void dwc2_enable_acg(struct dwc2_hsotg *hsotg) 670void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
671{ 671{
672 if (hsotg->params.acg_enable) { 672 if (hsotg->params.acg_enable) {
673 u32 pcgcctl1 = dwc2_readl(hsotg->regs + PCGCCTL1); 673 u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
674 674
675 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n"); 675 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
676 pcgcctl1 |= PCGCCTL1_GATEEN; 676 pcgcctl1 |= PCGCCTL1_GATEEN;
677 dwc2_writel(pcgcctl1, hsotg->regs + PCGCCTL1); 677 dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);
678 } 678 }
679} 679}
680 680
@@ -695,56 +695,57 @@ void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
695 dev_dbg(hsotg->dev, "Host Global Registers\n"); 695 dev_dbg(hsotg->dev, "Host Global Registers\n");
696 addr = hsotg->regs + HCFG; 696 addr = hsotg->regs + HCFG;
697 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", 697 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
698 (unsigned long)addr, dwc2_readl(addr)); 698 (unsigned long)addr, dwc2_readl(hsotg, HCFG));
699 addr = hsotg->regs + HFIR; 699 addr = hsotg->regs + HFIR;
700 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", 700 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
701 (unsigned long)addr, dwc2_readl(addr)); 701 (unsigned long)addr, dwc2_readl(hsotg, HFIR));
702 addr = hsotg->regs + HFNUM; 702 addr = hsotg->regs + HFNUM;
703 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", 703 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
704 (unsigned long)addr, dwc2_readl(addr)); 704 (unsigned long)addr, dwc2_readl(hsotg, HFNUM));
705 addr = hsotg->regs + HPTXSTS; 705 addr = hsotg->regs + HPTXSTS;
706 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", 706 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
707 (unsigned long)addr, dwc2_readl(addr)); 707 (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS));
708 addr = hsotg->regs + HAINT; 708 addr = hsotg->regs + HAINT;
709 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", 709 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
710 (unsigned long)addr, dwc2_readl(addr)); 710 (unsigned long)addr, dwc2_readl(hsotg, HAINT));
711 addr = hsotg->regs + HAINTMSK; 711 addr = hsotg->regs + HAINTMSK;
712 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", 712 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
713 (unsigned long)addr, dwc2_readl(addr)); 713 (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK));
714 if (hsotg->params.dma_desc_enable) { 714 if (hsotg->params.dma_desc_enable) {
715 addr = hsotg->regs + HFLBADDR; 715 addr = hsotg->regs + HFLBADDR;
716 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", 716 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
717 (unsigned long)addr, dwc2_readl(addr)); 717 (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR));
718 } 718 }
719 719
720 addr = hsotg->regs + HPRT0; 720 addr = hsotg->regs + HPRT0;
721 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", 721 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
722 (unsigned long)addr, dwc2_readl(addr)); 722 (unsigned long)addr, dwc2_readl(hsotg, HPRT0));
723 723
724 for (i = 0; i < hsotg->params.host_channels; i++) { 724 for (i = 0; i < hsotg->params.host_channels; i++) {
725 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); 725 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
726 addr = hsotg->regs + HCCHAR(i); 726 addr = hsotg->regs + HCCHAR(i);
727 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", 727 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
728 (unsigned long)addr, dwc2_readl(addr)); 728 (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i)));
729 addr = hsotg->regs + HCSPLT(i); 729 addr = hsotg->regs + HCSPLT(i);
730 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", 730 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
731 (unsigned long)addr, dwc2_readl(addr)); 731 (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i)));
732 addr = hsotg->regs + HCINT(i); 732 addr = hsotg->regs + HCINT(i);
733 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", 733 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
734 (unsigned long)addr, dwc2_readl(addr)); 734 (unsigned long)addr, dwc2_readl(hsotg, HCINT(i)));
735 addr = hsotg->regs + HCINTMSK(i); 735 addr = hsotg->regs + HCINTMSK(i);
736 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", 736 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
737 (unsigned long)addr, dwc2_readl(addr)); 737 (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i)));
738 addr = hsotg->regs + HCTSIZ(i); 738 addr = hsotg->regs + HCTSIZ(i);
739 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", 739 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
740 (unsigned long)addr, dwc2_readl(addr)); 740 (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i)));
741 addr = hsotg->regs + HCDMA(i); 741 addr = hsotg->regs + HCDMA(i);
742 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", 742 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
743 (unsigned long)addr, dwc2_readl(addr)); 743 (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i)));
744 if (hsotg->params.dma_desc_enable) { 744 if (hsotg->params.dma_desc_enable) {
745 addr = hsotg->regs + HCDMAB(i); 745 addr = hsotg->regs + HCDMAB(i);
746 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", 746 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
747 (unsigned long)addr, dwc2_readl(addr)); 747 (unsigned long)addr, dwc2_readl(hsotg,
748 HCDMAB(i)));
748 } 749 }
749 } 750 }
750#endif 751#endif
@@ -766,80 +767,80 @@ void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
766 dev_dbg(hsotg->dev, "Core Global Registers\n"); 767 dev_dbg(hsotg->dev, "Core Global Registers\n");
767 addr = hsotg->regs + GOTGCTL; 768 addr = hsotg->regs + GOTGCTL;
768 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", 769 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
769 (unsigned long)addr, dwc2_readl(addr)); 770 (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL));
770 addr = hsotg->regs + GOTGINT; 771 addr = hsotg->regs + GOTGINT;
771 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", 772 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
772 (unsigned long)addr, dwc2_readl(addr)); 773 (unsigned long)addr, dwc2_readl(hsotg, GOTGINT));
773 addr = hsotg->regs + GAHBCFG; 774 addr = hsotg->regs + GAHBCFG;
774 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", 775 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
775 (unsigned long)addr, dwc2_readl(addr)); 776 (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG));
776 addr = hsotg->regs + GUSBCFG; 777 addr = hsotg->regs + GUSBCFG;
777 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", 778 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
778 (unsigned long)addr, dwc2_readl(addr)); 779 (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG));
779 addr = hsotg->regs + GRSTCTL; 780 addr = hsotg->regs + GRSTCTL;
780 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", 781 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
781 (unsigned long)addr, dwc2_readl(addr)); 782 (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL));
782 addr = hsotg->regs + GINTSTS; 783 addr = hsotg->regs + GINTSTS;
783 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", 784 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
784 (unsigned long)addr, dwc2_readl(addr)); 785 (unsigned long)addr, dwc2_readl(hsotg, GINTSTS));
785 addr = hsotg->regs + GINTMSK; 786 addr = hsotg->regs + GINTMSK;
786 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", 787 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
787 (unsigned long)addr, dwc2_readl(addr)); 788 (unsigned long)addr, dwc2_readl(hsotg, GINTMSK));
788 addr = hsotg->regs + GRXSTSR; 789 addr = hsotg->regs + GRXSTSR;
789 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", 790 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
790 (unsigned long)addr, dwc2_readl(addr)); 791 (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR));
791 addr = hsotg->regs + GRXFSIZ; 792 addr = hsotg->regs + GRXFSIZ;
792 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", 793 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
793 (unsigned long)addr, dwc2_readl(addr)); 794 (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ));
794 addr = hsotg->regs + GNPTXFSIZ; 795 addr = hsotg->regs + GNPTXFSIZ;
795 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", 796 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
796 (unsigned long)addr, dwc2_readl(addr)); 797 (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ));
797 addr = hsotg->regs + GNPTXSTS; 798 addr = hsotg->regs + GNPTXSTS;
798 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", 799 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
799 (unsigned long)addr, dwc2_readl(addr)); 800 (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS));
800 addr = hsotg->regs + GI2CCTL; 801 addr = hsotg->regs + GI2CCTL;
801 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", 802 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
802 (unsigned long)addr, dwc2_readl(addr)); 803 (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL));
803 addr = hsotg->regs + GPVNDCTL; 804 addr = hsotg->regs + GPVNDCTL;
804 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", 805 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
805 (unsigned long)addr, dwc2_readl(addr)); 806 (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));
806 addr = hsotg->regs + GGPIO; 807 addr = hsotg->regs + GGPIO;
807 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", 808 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
808 (unsigned long)addr, dwc2_readl(addr)); 809 (unsigned long)addr, dwc2_readl(hsotg, GGPIO));
809 addr = hsotg->regs + GUID; 810 addr = hsotg->regs + GUID;
810 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", 811 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
811 (unsigned long)addr, dwc2_readl(addr)); 812 (unsigned long)addr, dwc2_readl(hsotg, GUID));
812 addr = hsotg->regs + GSNPSID; 813 addr = hsotg->regs + GSNPSID;
813 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", 814 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
814 (unsigned long)addr, dwc2_readl(addr)); 815 (unsigned long)addr, dwc2_readl(hsotg, GSNPSID));
815 addr = hsotg->regs + GHWCFG1; 816 addr = hsotg->regs + GHWCFG1;
816 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", 817 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
817 (unsigned long)addr, dwc2_readl(addr)); 818 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1));
818 addr = hsotg->regs + GHWCFG2; 819 addr = hsotg->regs + GHWCFG2;
819 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", 820 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
820 (unsigned long)addr, dwc2_readl(addr)); 821 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2));
821 addr = hsotg->regs + GHWCFG3; 822 addr = hsotg->regs + GHWCFG3;
822 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", 823 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
823 (unsigned long)addr, dwc2_readl(addr)); 824 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3));
824 addr = hsotg->regs + GHWCFG4; 825 addr = hsotg->regs + GHWCFG4;
825 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", 826 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
826 (unsigned long)addr, dwc2_readl(addr)); 827 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4));
827 addr = hsotg->regs + GLPMCFG; 828 addr = hsotg->regs + GLPMCFG;
828 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", 829 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
829 (unsigned long)addr, dwc2_readl(addr)); 830 (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG));
830 addr = hsotg->regs + GPWRDN; 831 addr = hsotg->regs + GPWRDN;
831 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", 832 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
832 (unsigned long)addr, dwc2_readl(addr)); 833 (unsigned long)addr, dwc2_readl(hsotg, GPWRDN));
833 addr = hsotg->regs + GDFIFOCFG; 834 addr = hsotg->regs + GDFIFOCFG;
834 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", 835 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
835 (unsigned long)addr, dwc2_readl(addr)); 836 (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG));
836 addr = hsotg->regs + HPTXFSIZ; 837 addr = hsotg->regs + HPTXFSIZ;
837 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", 838 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
838 (unsigned long)addr, dwc2_readl(addr)); 839 (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));
839 840
840 addr = hsotg->regs + PCGCTL; 841 addr = hsotg->regs + PCGCTL;
841 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", 842 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
842 (unsigned long)addr, dwc2_readl(addr)); 843 (unsigned long)addr, dwc2_readl(hsotg, PCGCTL));
843#endif 844#endif
844} 845}
845 846
@@ -862,7 +863,7 @@ void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
862 863
863 greset = GRSTCTL_TXFFLSH; 864 greset = GRSTCTL_TXFFLSH;
864 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; 865 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
865 dwc2_writel(greset, hsotg->regs + GRSTCTL); 866 dwc2_writel(hsotg, greset, GRSTCTL);
866 867
867 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000)) 868 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))
868 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n", 869 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
@@ -889,7 +890,7 @@ void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
889 __func__); 890 __func__);
890 891
891 greset = GRSTCTL_RXFFLSH; 892 greset = GRSTCTL_RXFFLSH;
892 dwc2_writel(greset, hsotg->regs + GRSTCTL); 893 dwc2_writel(hsotg, greset, GRSTCTL);
893 894
894 /* Wait for RxFIFO flush done */ 895 /* Wait for RxFIFO flush done */
895 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000)) 896 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
@@ -902,7 +903,7 @@ void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
902 903
903bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) 904bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
904{ 905{
905 if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff) 906 if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)
906 return false; 907 return false;
907 else 908 else
908 return true; 909 return true;
@@ -916,10 +917,10 @@ bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
916 */ 917 */
917void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) 918void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
918{ 919{
919 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 920 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
920 921
921 ahbcfg |= GAHBCFG_GLBL_INTR_EN; 922 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
922 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 923 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
923} 924}
924 925
925/** 926/**
@@ -930,16 +931,16 @@ void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
930 */ 931 */
931void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) 932void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
932{ 933{
933 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 934 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
934 935
935 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 936 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
936 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 937 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
937} 938}
938 939
939/* Returns the controller's GHWCFG2.OTG_MODE. */ 940/* Returns the controller's GHWCFG2.OTG_MODE. */
940unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg) 941unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
941{ 942{
942 u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 943 u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);
943 944
944 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >> 945 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
945 GHWCFG2_OP_MODE_SHIFT; 946 GHWCFG2_OP_MODE_SHIFT;
@@ -988,7 +989,7 @@ int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
988 u32 i; 989 u32 i;
989 990
990 for (i = 0; i < timeout; i++) { 991 for (i = 0; i < timeout; i++) {
991 if (dwc2_readl(hsotg->regs + offset) & mask) 992 if (dwc2_readl(hsotg, offset) & mask)
992 return 0; 993 return 0;
993 udelay(1); 994 udelay(1);
994 } 995 }
@@ -1011,7 +1012,7 @@ int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
1011 u32 i; 1012 u32 i;
1012 1013
1013 for (i = 0; i < timeout; i++) { 1014 for (i = 0; i < timeout; i++) {
1014 if (!(dwc2_readl(hsotg->regs + offset) & mask)) 1015 if (!(dwc2_readl(hsotg, offset) & mask))
1015 return 0; 1016 return 0;
1016 udelay(1); 1017 udelay(1);
1017 } 1018 }
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 8a9272a2c82c..bca8463f00b0 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -1172,9 +1172,9 @@ struct dwc2_hsotg {
1172 * writes. This set of operations was added specifically for MIPS and 1172 * writes. This set of operations was added specifically for MIPS and
1173 * should only be used there. 1173 * should only be used there.
1174 */ 1174 */
1175static inline u32 dwc2_readl(const void __iomem *addr) 1175static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
1176{ 1176{
1177 u32 value = __raw_readl(addr); 1177 u32 value = __raw_readl(hsotg->regs + offset);
1178 1178
1179 /* In order to preserve endianness __raw_* operation is used. Therefore 1179 /* In order to preserve endianness __raw_* operation is used. Therefore
1180 * a barrier is needed to ensure IO access is not re-ordered across 1180 * a barrier is needed to ensure IO access is not re-ordered across
@@ -1184,9 +1184,9 @@ static inline u32 dwc2_readl(const void __iomem *addr)
1184 return value; 1184 return value;
1185} 1185}
1186 1186
1187static inline void dwc2_writel(u32 value, void __iomem *addr) 1187static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
1188{ 1188{
1189 __raw_writel(value, addr); 1189 __raw_writel(value, hsotg->regs + offset);
1190 1190
1191 /* 1191 /*
1192 * In order to preserve endianness __raw_* operation is used. Therefore 1192 * In order to preserve endianness __raw_* operation is used. Therefore
@@ -1195,22 +1195,23 @@ static inline void dwc2_writel(u32 value, void __iomem *addr)
1195 */ 1195 */
1196 mb(); 1196 mb();
1197#ifdef DWC2_LOG_WRITES 1197#ifdef DWC2_LOG_WRITES
1198 pr_info("INFO:: wrote %08x to %p\n", value, addr); 1198 pr_info("INFO:: wrote %08x to %p\n", value, hsotg->regs + offset);
1199#endif 1199#endif
1200} 1200}
1201#else 1201#else
1202
1202/* Normal architectures just use readl/write */ 1203/* Normal architectures just use readl/write */
1203static inline u32 dwc2_readl(const void __iomem *addr) 1204static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
1204{ 1205{
1205 return readl(addr); 1206 return readl(hsotg->regs + offset);
1206} 1207}
1207 1208
1208static inline void dwc2_writel(u32 value, void __iomem *addr) 1209static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
1209{ 1210{
1210 writel(value, addr); 1211 writel(value, hsotg->regs + offset);
1211 1212
1212#ifdef DWC2_LOG_WRITES 1213#ifdef DWC2_LOG_WRITES
1213 pr_info("info:: wrote %08x to %p\n", value, addr); 1214 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
1214#endif 1215#endif
1215} 1216}
1216#endif 1217#endif
@@ -1320,12 +1321,12 @@ bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1320 */ 1321 */
1321static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1322static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1322{ 1323{
1323 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1324 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1324} 1325}
1325 1326
1326static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1327static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1327{ 1328{
1328 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1329 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1329} 1330}
1330 1331
1331/* 1332/*
diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
index cc90b58b6b3c..19ae2595f1c3 100644
--- a/drivers/usb/dwc2/core_intr.c
+++ b/drivers/usb/dwc2/core_intr.c
@@ -81,11 +81,11 @@ static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
81 */ 81 */
82static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) 82static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
83{ 83{
84 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 84 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
85 85
86 if (hprt0 & HPRT0_ENACHG) { 86 if (hprt0 & HPRT0_ENACHG) {
87 hprt0 &= ~HPRT0_ENA; 87 hprt0 &= ~HPRT0_ENA;
88 dwc2_writel(hprt0, hsotg->regs + HPRT0); 88 dwc2_writel(hsotg, hprt0, HPRT0);
89 } 89 }
90} 90}
91 91
@@ -97,7 +97,7 @@ static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
97static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg) 97static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
98{ 98{
99 /* Clear interrupt */ 99 /* Clear interrupt */
100 dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); 100 dwc2_writel(hsotg, GINTSTS_MODEMIS, GINTSTS);
101 101
102 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n", 102 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
103 dwc2_is_host_mode(hsotg) ? "Host" : "Device"); 103 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
@@ -115,8 +115,8 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
115 u32 gotgctl; 115 u32 gotgctl;
116 u32 gintmsk; 116 u32 gintmsk;
117 117
118 gotgint = dwc2_readl(hsotg->regs + GOTGINT); 118 gotgint = dwc2_readl(hsotg, GOTGINT);
119 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 119 gotgctl = dwc2_readl(hsotg, GOTGCTL);
120 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, 120 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
121 dwc2_op_state_str(hsotg)); 121 dwc2_op_state_str(hsotg));
122 122
@@ -124,7 +124,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
124 dev_dbg(hsotg->dev, 124 dev_dbg(hsotg->dev,
125 " ++OTG Interrupt: Session End Detected++ (%s)\n", 125 " ++OTG Interrupt: Session End Detected++ (%s)\n",
126 dwc2_op_state_str(hsotg)); 126 dwc2_op_state_str(hsotg));
127 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 127 gotgctl = dwc2_readl(hsotg, GOTGCTL);
128 128
129 if (dwc2_is_device_mode(hsotg)) 129 if (dwc2_is_device_mode(hsotg))
130 dwc2_hsotg_disconnect(hsotg); 130 dwc2_hsotg_disconnect(hsotg);
@@ -150,24 +150,24 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
150 hsotg->lx_state = DWC2_L0; 150 hsotg->lx_state = DWC2_L0;
151 } 151 }
152 152
153 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 153 gotgctl = dwc2_readl(hsotg, GOTGCTL);
154 gotgctl &= ~GOTGCTL_DEVHNPEN; 154 gotgctl &= ~GOTGCTL_DEVHNPEN;
155 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 155 dwc2_writel(hsotg, gotgctl, GOTGCTL);
156 } 156 }
157 157
158 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) { 158 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
159 dev_dbg(hsotg->dev, 159 dev_dbg(hsotg->dev,
160 " ++OTG Interrupt: Session Request Success Status Change++\n"); 160 " ++OTG Interrupt: Session Request Success Status Change++\n");
161 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 161 gotgctl = dwc2_readl(hsotg, GOTGCTL);
162 if (gotgctl & GOTGCTL_SESREQSCS) { 162 if (gotgctl & GOTGCTL_SESREQSCS) {
163 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS && 163 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
164 hsotg->params.i2c_enable) { 164 hsotg->params.i2c_enable) {
165 hsotg->srp_success = 1; 165 hsotg->srp_success = 1;
166 } else { 166 } else {
167 /* Clear Session Request */ 167 /* Clear Session Request */
168 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 168 gotgctl = dwc2_readl(hsotg, GOTGCTL);
169 gotgctl &= ~GOTGCTL_SESREQ; 169 gotgctl &= ~GOTGCTL_SESREQ;
170 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 170 dwc2_writel(hsotg, gotgctl, GOTGCTL);
171 } 171 }
172 } 172 }
173 } 173 }
@@ -177,7 +177,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
177 * Print statements during the HNP interrupt handling 177 * Print statements during the HNP interrupt handling
178 * can cause it to fail 178 * can cause it to fail
179 */ 179 */
180 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 180 gotgctl = dwc2_readl(hsotg, GOTGCTL);
181 /* 181 /*
182 * WA for 3.00a- HW is not setting cur_mode, even sometimes 182 * WA for 3.00a- HW is not setting cur_mode, even sometimes
183 * this does not help 183 * this does not help
@@ -197,9 +197,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
197 * interrupt does not get handled and Linux 197 * interrupt does not get handled and Linux
198 * complains loudly. 198 * complains loudly.
199 */ 199 */
200 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 200 gintmsk = dwc2_readl(hsotg, GINTMSK);
201 gintmsk &= ~GINTSTS_SOF; 201 gintmsk &= ~GINTSTS_SOF;
202 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 202 dwc2_writel(hsotg, gintmsk, GINTMSK);
203 203
204 /* 204 /*
205 * Call callback function with spin lock 205 * Call callback function with spin lock
@@ -213,9 +213,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
213 hsotg->op_state = OTG_STATE_B_HOST; 213 hsotg->op_state = OTG_STATE_B_HOST;
214 } 214 }
215 } else { 215 } else {
216 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 216 gotgctl = dwc2_readl(hsotg, GOTGCTL);
217 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN); 217 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
218 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 218 dwc2_writel(hsotg, gotgctl, GOTGCTL);
219 dev_dbg(hsotg->dev, "HNP Failed\n"); 219 dev_dbg(hsotg->dev, "HNP Failed\n");
220 dev_err(hsotg->dev, 220 dev_err(hsotg->dev,
221 "Device Not Connected/Responding\n"); 221 "Device Not Connected/Responding\n");
@@ -241,9 +241,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
241 hsotg->op_state = OTG_STATE_A_PERIPHERAL; 241 hsotg->op_state = OTG_STATE_A_PERIPHERAL;
242 } else { 242 } else {
243 /* Need to disable SOF interrupt immediately */ 243 /* Need to disable SOF interrupt immediately */
244 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 244 gintmsk = dwc2_readl(hsotg, GINTMSK);
245 gintmsk &= ~GINTSTS_SOF; 245 gintmsk &= ~GINTSTS_SOF;
246 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 246 dwc2_writel(hsotg, gintmsk, GINTMSK);
247 spin_unlock(&hsotg->lock); 247 spin_unlock(&hsotg->lock);
248 dwc2_hcd_start(hsotg); 248 dwc2_hcd_start(hsotg);
249 spin_lock(&hsotg->lock); 249 spin_lock(&hsotg->lock);
@@ -258,7 +258,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
258 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n"); 258 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
259 259
260 /* Clear GOTGINT */ 260 /* Clear GOTGINT */
261 dwc2_writel(gotgint, hsotg->regs + GOTGINT); 261 dwc2_writel(hsotg, gotgint, GOTGINT);
262} 262}
263 263
264/** 264/**
@@ -276,12 +276,12 @@ static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
276 u32 gintmsk; 276 u32 gintmsk;
277 277
278 /* Clear interrupt */ 278 /* Clear interrupt */
279 dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); 279 dwc2_writel(hsotg, GINTSTS_CONIDSTSCHNG, GINTSTS);
280 280
281 /* Need to disable SOF interrupt immediately */ 281 /* Need to disable SOF interrupt immediately */
282 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 282 gintmsk = dwc2_readl(hsotg, GINTMSK);
283 gintmsk &= ~GINTSTS_SOF; 283 gintmsk &= ~GINTSTS_SOF;
284 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 284 dwc2_writel(hsotg, gintmsk, GINTMSK);
285 285
286 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", 286 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
287 dwc2_is_host_mode(hsotg) ? "Host" : "Device"); 287 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
@@ -314,7 +314,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
314 int ret; 314 int ret;
315 315
316 /* Clear interrupt */ 316 /* Clear interrupt */
317 dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); 317 dwc2_writel(hsotg, GINTSTS_SESSREQINT, GINTSTS);
318 318
319 dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n", 319 dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
320 hsotg->lx_state); 320 hsotg->lx_state);
@@ -351,15 +351,15 @@ static void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg)
351 return; 351 return;
352 } 352 }
353 353
354 glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); 354 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
355 if (dwc2_is_device_mode(hsotg)) { 355 if (dwc2_is_device_mode(hsotg)) {
356 dev_dbg(hsotg->dev, "Exit from L1 state\n"); 356 dev_dbg(hsotg->dev, "Exit from L1 state\n");
357 glpmcfg &= ~GLPMCFG_ENBLSLPM; 357 glpmcfg &= ~GLPMCFG_ENBLSLPM;
358 glpmcfg &= ~GLPMCFG_HIRD_THRES_EN; 358 glpmcfg &= ~GLPMCFG_HIRD_THRES_EN;
359 dwc2_writel(glpmcfg, hsotg->regs + GLPMCFG); 359 dwc2_writel(hsotg, glpmcfg, GLPMCFG);
360 360
361 do { 361 do {
362 glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); 362 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
363 363
364 if (!(glpmcfg & (GLPMCFG_COREL1RES_MASK | 364 if (!(glpmcfg & (GLPMCFG_COREL1RES_MASK |
365 GLPMCFG_L1RESUMEOK | GLPMCFG_SLPSTS))) 365 GLPMCFG_L1RESUMEOK | GLPMCFG_SLPSTS)))
@@ -398,7 +398,7 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
398 int ret; 398 int ret;
399 399
400 /* Clear interrupt */ 400 /* Clear interrupt */
401 dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); 401 dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS);
402 402
403 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n"); 403 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
404 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state); 404 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
@@ -410,13 +410,13 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
410 410
411 if (dwc2_is_device_mode(hsotg)) { 411 if (dwc2_is_device_mode(hsotg)) {
412 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", 412 dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
413 dwc2_readl(hsotg->regs + DSTS)); 413 dwc2_readl(hsotg, DSTS));
414 if (hsotg->lx_state == DWC2_L2) { 414 if (hsotg->lx_state == DWC2_L2) {
415 u32 dctl = dwc2_readl(hsotg->regs + DCTL); 415 u32 dctl = dwc2_readl(hsotg, DCTL);
416 416
417 /* Clear Remote Wakeup Signaling */ 417 /* Clear Remote Wakeup Signaling */
418 dctl &= ~DCTL_RMTWKUPSIG; 418 dctl &= ~DCTL_RMTWKUPSIG;
419 dwc2_writel(dctl, hsotg->regs + DCTL); 419 dwc2_writel(hsotg, dctl, DCTL);
420 ret = dwc2_exit_partial_power_down(hsotg, true); 420 ret = dwc2_exit_partial_power_down(hsotg, true);
421 if (ret && (ret != -ENOTSUPP)) 421 if (ret && (ret != -ENOTSUPP))
422 dev_err(hsotg->dev, "exit power_down failed\n"); 422 dev_err(hsotg->dev, "exit power_down failed\n");
@@ -430,11 +430,11 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
430 return; 430 return;
431 431
432 if (hsotg->lx_state != DWC2_L1) { 432 if (hsotg->lx_state != DWC2_L1) {
433 u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 433 u32 pcgcctl = dwc2_readl(hsotg, PCGCTL);
434 434
435 /* Restart the Phy Clock */ 435 /* Restart the Phy Clock */
436 pcgcctl &= ~PCGCTL_STOPPCLK; 436 pcgcctl &= ~PCGCTL_STOPPCLK;
437 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 437 dwc2_writel(hsotg, pcgcctl, PCGCTL);
438 mod_timer(&hsotg->wkp_timer, 438 mod_timer(&hsotg->wkp_timer,
439 jiffies + msecs_to_jiffies(71)); 439 jiffies + msecs_to_jiffies(71));
440 } else { 440 } else {
@@ -450,7 +450,7 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
450 */ 450 */
451static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg) 451static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
452{ 452{
453 dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS); 453 dwc2_writel(hsotg, GINTSTS_DISCONNINT, GINTSTS);
454 454
455 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n", 455 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
456 dwc2_is_host_mode(hsotg) ? "Host" : "Device", 456 dwc2_is_host_mode(hsotg) ? "Host" : "Device",
@@ -474,7 +474,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
474 int ret; 474 int ret;
475 475
476 /* Clear interrupt */ 476 /* Clear interrupt */
477 dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); 477 dwc2_writel(hsotg, GINTSTS_USBSUSP, GINTSTS);
478 478
479 dev_dbg(hsotg->dev, "USB SUSPEND\n"); 479 dev_dbg(hsotg->dev, "USB SUSPEND\n");
480 480
@@ -483,7 +483,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
483 * Check the Device status register to determine if the Suspend 483 * Check the Device status register to determine if the Suspend
484 * state is active 484 * state is active
485 */ 485 */
486 dsts = dwc2_readl(hsotg->regs + DSTS); 486 dsts = dwc2_readl(hsotg, DSTS);
487 dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts); 487 dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts);
488 dev_dbg(hsotg->dev, 488 dev_dbg(hsotg->dev,
489 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n", 489 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n",
@@ -563,9 +563,9 @@ static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
563 u32 enslpm; 563 u32 enslpm;
564 564
565 /* Clear interrupt */ 565 /* Clear interrupt */
566 dwc2_writel(GINTSTS_LPMTRANRCVD, hsotg->regs + GINTSTS); 566 dwc2_writel(hsotg, GINTSTS_LPMTRANRCVD, GINTSTS);
567 567
568 glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); 568 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
569 569
570 if (!(glpmcfg & GLPMCFG_LPMCAP)) { 570 if (!(glpmcfg & GLPMCFG_LPMCAP)) {
571 dev_err(hsotg->dev, "Unexpected LPM interrupt\n"); 571 dev_err(hsotg->dev, "Unexpected LPM interrupt\n");
@@ -588,16 +588,16 @@ static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
588 } else { 588 } else {
589 dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n"); 589 dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n");
590 590
591 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 591 pcgcctl = dwc2_readl(hsotg, PCGCTL);
592 pcgcctl |= PCGCTL_ENBL_SLEEP_GATING; 592 pcgcctl |= PCGCTL_ENBL_SLEEP_GATING;
593 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 593 dwc2_writel(hsotg, pcgcctl, PCGCTL);
594 } 594 }
595 /** 595 /**
596 * Examine prt_sleep_sts after TL1TokenTetry period max (10 us) 596 * Examine prt_sleep_sts after TL1TokenTetry period max (10 us)
597 */ 597 */
598 udelay(10); 598 udelay(10);
599 599
600 glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); 600 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
601 601
602 if (glpmcfg & GLPMCFG_SLPSTS) { 602 if (glpmcfg & GLPMCFG_SLPSTS) {
603 /* Save the current state */ 603 /* Save the current state */
@@ -627,9 +627,9 @@ static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
627 u32 gahbcfg; 627 u32 gahbcfg;
628 u32 gintmsk_common = GINTMSK_COMMON; 628 u32 gintmsk_common = GINTMSK_COMMON;
629 629
630 gintsts = dwc2_readl(hsotg->regs + GINTSTS); 630 gintsts = dwc2_readl(hsotg, GINTSTS);
631 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 631 gintmsk = dwc2_readl(hsotg, GINTMSK);
632 gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 632 gahbcfg = dwc2_readl(hsotg, GAHBCFG);
633 633
634 /* If any common interrupts set */ 634 /* If any common interrupts set */
635 if (gintsts & gintmsk_common) 635 if (gintsts & gintmsk_common)
@@ -653,9 +653,9 @@ static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
653 u32 gpwrdn; 653 u32 gpwrdn;
654 int linestate; 654 int linestate;
655 655
656 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 656 gpwrdn = dwc2_readl(hsotg, GPWRDN);
657 /* clear all interrupt */ 657 /* clear all interrupt */
658 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 658 dwc2_writel(hsotg, gpwrdn, GPWRDN);
659 linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT; 659 linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT;
660 dev_dbg(hsotg->dev, 660 dev_dbg(hsotg->dev,
661 "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__, 661 "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__,
@@ -668,38 +668,38 @@ static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
668 dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__); 668 dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__);
669 669
670 /* Switch-on voltage to the core */ 670 /* Switch-on voltage to the core */
671 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); 671 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
672 gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH; 672 gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH;
673 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); 673 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
674 udelay(10); 674 udelay(10);
675 675
676 /* Reset core */ 676 /* Reset core */
677 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); 677 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
678 gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN; 678 gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN;
679 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); 679 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
680 udelay(10); 680 udelay(10);
681 681
682 /* Disable Power Down Clamp */ 682 /* Disable Power Down Clamp */
683 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); 683 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
684 gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP; 684 gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP;
685 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); 685 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
686 udelay(10); 686 udelay(10);
687 687
688 /* Deassert reset core */ 688 /* Deassert reset core */
689 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); 689 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
690 gpwrdn_tmp |= GPWRDN_PWRDNRSTN; 690 gpwrdn_tmp |= GPWRDN_PWRDNRSTN;
691 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); 691 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
692 udelay(10); 692 udelay(10);
693 693
694 /* Disable PMU interrupt */ 694 /* Disable PMU interrupt */
695 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); 695 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
696 gpwrdn_tmp &= ~GPWRDN_PMUINTSEL; 696 gpwrdn_tmp &= ~GPWRDN_PMUINTSEL;
697 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); 697 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
698 698
699 /* De-assert Wakeup Logic */ 699 /* De-assert Wakeup Logic */
700 gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); 700 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
701 gpwrdn_tmp &= ~GPWRDN_PMUACTV; 701 gpwrdn_tmp &= ~GPWRDN_PMUACTV;
702 dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); 702 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
703 703
704 hsotg->hibernated = 0; 704 hsotg->hibernated = 0;
705 705
@@ -780,10 +780,10 @@ irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
780 780
781 /* Reading current frame number value in device or host modes. */ 781 /* Reading current frame number value in device or host modes. */
782 if (dwc2_is_device_mode(hsotg)) 782 if (dwc2_is_device_mode(hsotg))
783 hsotg->frame_number = (dwc2_readl(hsotg->regs + DSTS) 783 hsotg->frame_number = (dwc2_readl(hsotg, DSTS)
784 & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT; 784 & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT;
785 else 785 else
786 hsotg->frame_number = (dwc2_readl(hsotg->regs + HFNUM) 786 hsotg->frame_number = (dwc2_readl(hsotg, HFNUM)
787 & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 787 & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
788 788
789 gintsts = dwc2_read_common_intr(hsotg); 789 gintsts = dwc2_read_common_intr(hsotg);
diff --git a/drivers/usb/dwc2/debugfs.c b/drivers/usb/dwc2/debugfs.c
index d0bdb7997557..22d015b0424f 100644
--- a/drivers/usb/dwc2/debugfs.c
+++ b/drivers/usb/dwc2/debugfs.c
@@ -69,7 +69,7 @@ static int testmode_show(struct seq_file *s, void *unused)
69 int dctl; 69 int dctl;
70 70
71 spin_lock_irqsave(&hsotg->lock, flags); 71 spin_lock_irqsave(&hsotg->lock, flags);
72 dctl = dwc2_readl(hsotg->regs + DCTL); 72 dctl = dwc2_readl(hsotg, DCTL);
73 dctl &= DCTL_TSTCTL_MASK; 73 dctl &= DCTL_TSTCTL_MASK;
74 dctl >>= DCTL_TSTCTL_SHIFT; 74 dctl >>= DCTL_TSTCTL_SHIFT;
75 spin_unlock_irqrestore(&hsotg->lock, flags); 75 spin_unlock_irqrestore(&hsotg->lock, flags);
@@ -126,42 +126,41 @@ static const struct file_operations testmode_fops = {
126static int state_show(struct seq_file *seq, void *v) 126static int state_show(struct seq_file *seq, void *v)
127{ 127{
128 struct dwc2_hsotg *hsotg = seq->private; 128 struct dwc2_hsotg *hsotg = seq->private;
129 void __iomem *regs = hsotg->regs;
130 int idx; 129 int idx;
131 130
132 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", 131 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
133 dwc2_readl(regs + DCFG), 132 dwc2_readl(hsotg, DCFG),
134 dwc2_readl(regs + DCTL), 133 dwc2_readl(hsotg, DCTL),
135 dwc2_readl(regs + DSTS)); 134 dwc2_readl(hsotg, DSTS));
136 135
137 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", 136 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
138 dwc2_readl(regs + DIEPMSK), dwc2_readl(regs + DOEPMSK)); 137 dwc2_readl(hsotg, DIEPMSK), dwc2_readl(hsotg, DOEPMSK));
139 138
140 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", 139 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
141 dwc2_readl(regs + GINTMSK), 140 dwc2_readl(hsotg, GINTMSK),
142 dwc2_readl(regs + GINTSTS)); 141 dwc2_readl(hsotg, GINTSTS));
143 142
144 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", 143 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
145 dwc2_readl(regs + DAINTMSK), 144 dwc2_readl(hsotg, DAINTMSK),
146 dwc2_readl(regs + DAINT)); 145 dwc2_readl(hsotg, DAINT));
147 146
148 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", 147 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
149 dwc2_readl(regs + GNPTXSTS), 148 dwc2_readl(hsotg, GNPTXSTS),
150 dwc2_readl(regs + GRXSTSR)); 149 dwc2_readl(hsotg, GRXSTSR));
151 150
152 seq_puts(seq, "\nEndpoint status:\n"); 151 seq_puts(seq, "\nEndpoint status:\n");
153 152
154 for (idx = 0; idx < hsotg->num_of_eps; idx++) { 153 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
155 u32 in, out; 154 u32 in, out;
156 155
157 in = dwc2_readl(regs + DIEPCTL(idx)); 156 in = dwc2_readl(hsotg, DIEPCTL(idx));
158 out = dwc2_readl(regs + DOEPCTL(idx)); 157 out = dwc2_readl(hsotg, DOEPCTL(idx));
159 158
160 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", 159 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
161 idx, in, out); 160 idx, in, out);
162 161
163 in = dwc2_readl(regs + DIEPTSIZ(idx)); 162 in = dwc2_readl(hsotg, DIEPTSIZ(idx));
164 out = dwc2_readl(regs + DOEPTSIZ(idx)); 163 out = dwc2_readl(hsotg, DOEPTSIZ(idx));
165 164
166 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", 165 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
167 in, out); 166 in, out);
@@ -184,14 +183,13 @@ DEFINE_SHOW_ATTRIBUTE(state);
184static int fifo_show(struct seq_file *seq, void *v) 183static int fifo_show(struct seq_file *seq, void *v)
185{ 184{
186 struct dwc2_hsotg *hsotg = seq->private; 185 struct dwc2_hsotg *hsotg = seq->private;
187 void __iomem *regs = hsotg->regs;
188 u32 val; 186 u32 val;
189 int idx; 187 int idx;
190 188
191 seq_puts(seq, "Non-periodic FIFOs:\n"); 189 seq_puts(seq, "Non-periodic FIFOs:\n");
192 seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(regs + GRXFSIZ)); 190 seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(hsotg, GRXFSIZ));
193 191
194 val = dwc2_readl(regs + GNPTXFSIZ); 192 val = dwc2_readl(hsotg, GNPTXFSIZ);
195 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", 193 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
196 val >> FIFOSIZE_DEPTH_SHIFT, 194 val >> FIFOSIZE_DEPTH_SHIFT,
197 val & FIFOSIZE_STARTADDR_MASK); 195 val & FIFOSIZE_STARTADDR_MASK);
@@ -199,7 +197,7 @@ static int fifo_show(struct seq_file *seq, void *v)
199 seq_puts(seq, "\nPeriodic TXFIFOs:\n"); 197 seq_puts(seq, "\nPeriodic TXFIFOs:\n");
200 198
201 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 199 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
202 val = dwc2_readl(regs + DPTXFSIZN(idx)); 200 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
203 201
204 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, 202 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
205 val >> FIFOSIZE_DEPTH_SHIFT, 203 val >> FIFOSIZE_DEPTH_SHIFT,
@@ -228,7 +226,6 @@ static int ep_show(struct seq_file *seq, void *v)
228 struct dwc2_hsotg_ep *ep = seq->private; 226 struct dwc2_hsotg_ep *ep = seq->private;
229 struct dwc2_hsotg *hsotg = ep->parent; 227 struct dwc2_hsotg *hsotg = ep->parent;
230 struct dwc2_hsotg_req *req; 228 struct dwc2_hsotg_req *req;
231 void __iomem *regs = hsotg->regs;
232 int index = ep->index; 229 int index = ep->index;
233 int show_limit = 15; 230 int show_limit = 15;
234 unsigned long flags; 231 unsigned long flags;
@@ -239,20 +236,20 @@ static int ep_show(struct seq_file *seq, void *v)
239 /* first show the register state */ 236 /* first show the register state */
240 237
241 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", 238 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
242 dwc2_readl(regs + DIEPCTL(index)), 239 dwc2_readl(hsotg, DIEPCTL(index)),
243 dwc2_readl(regs + DOEPCTL(index))); 240 dwc2_readl(hsotg, DOEPCTL(index)));
244 241
245 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", 242 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
246 dwc2_readl(regs + DIEPDMA(index)), 243 dwc2_readl(hsotg, DIEPDMA(index)),
247 dwc2_readl(regs + DOEPDMA(index))); 244 dwc2_readl(hsotg, DOEPDMA(index)));
248 245
249 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", 246 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
250 dwc2_readl(regs + DIEPINT(index)), 247 dwc2_readl(hsotg, DIEPINT(index)),
251 dwc2_readl(regs + DOEPINT(index))); 248 dwc2_readl(hsotg, DOEPINT(index)));
252 249
253 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", 250 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
254 dwc2_readl(regs + DIEPTSIZ(index)), 251 dwc2_readl(hsotg, DIEPTSIZ(index)),
255 dwc2_readl(regs + DOEPTSIZ(index))); 252 dwc2_readl(hsotg, DOEPTSIZ(index)));
256 253
257 seq_puts(seq, "\n"); 254 seq_puts(seq, "\n");
258 seq_printf(seq, "mps %d\n", ep->ep.maxpacket); 255 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index a0f82cca2d9a..50f94f277433 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -47,14 +47,14 @@ static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
47 return container_of(gadget, struct dwc2_hsotg, gadget); 47 return container_of(gadget, struct dwc2_hsotg, gadget);
48} 48}
49 49
50static inline void dwc2_set_bit(void __iomem *ptr, u32 val) 50static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
51{ 51{
52 dwc2_writel(dwc2_readl(ptr) | val, ptr); 52 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
53} 53}
54 54
55static inline void dwc2_clear_bit(void __iomem *ptr, u32 val) 55static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
56{ 56{
57 dwc2_writel(dwc2_readl(ptr) & ~val, ptr); 57 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
58} 58}
59 59
60static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, 60static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
@@ -129,14 +129,14 @@ static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
129 */ 129 */
130static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) 130static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
131{ 131{
132 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); 132 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
133 u32 new_gsintmsk; 133 u32 new_gsintmsk;
134 134
135 new_gsintmsk = gsintmsk | ints; 135 new_gsintmsk = gsintmsk | ints;
136 136
137 if (new_gsintmsk != gsintmsk) { 137 if (new_gsintmsk != gsintmsk) {
138 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); 138 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
139 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); 139 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
140 } 140 }
141} 141}
142 142
@@ -147,13 +147,13 @@ static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
147 */ 147 */
148static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) 148static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
149{ 149{
150 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); 150 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
151 u32 new_gsintmsk; 151 u32 new_gsintmsk;
152 152
153 new_gsintmsk = gsintmsk & ~ints; 153 new_gsintmsk = gsintmsk & ~ints;
154 154
155 if (new_gsintmsk != gsintmsk) 155 if (new_gsintmsk != gsintmsk)
156 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); 156 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
157} 157}
158 158
159/** 159/**
@@ -178,12 +178,12 @@ static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
178 bit <<= 16; 178 bit <<= 16;
179 179
180 local_irq_save(flags); 180 local_irq_save(flags);
181 daint = dwc2_readl(hsotg->regs + DAINTMSK); 181 daint = dwc2_readl(hsotg, DAINTMSK);
182 if (en) 182 if (en)
183 daint |= bit; 183 daint |= bit;
184 else 184 else
185 daint &= ~bit; 185 daint &= ~bit;
186 dwc2_writel(daint, hsotg->regs + DAINTMSK); 186 dwc2_writel(hsotg, daint, DAINTMSK);
187 local_irq_restore(flags); 187 local_irq_restore(flags);
188} 188}
189 189
@@ -266,10 +266,11 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
266 hsotg->fifo_map = 0; 266 hsotg->fifo_map = 0;
267 267
268 /* set RX/NPTX FIFO sizes */ 268 /* set RX/NPTX FIFO sizes */
269 dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ); 269 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
270 dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) | 270 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
271 FIFOSIZE_STARTADDR_SHIFT) |
271 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), 272 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
272 hsotg->regs + GNPTXFSIZ); 273 GNPTXFSIZ);
273 274
274 /* 275 /*
275 * arange all the rest of the TX FIFOs, as some versions of this 276 * arange all the rest of the TX FIFOs, as some versions of this
@@ -295,25 +296,25 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
295 "insufficient fifo memory"); 296 "insufficient fifo memory");
296 addr += txfsz[ep]; 297 addr += txfsz[ep];
297 298
298 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); 299 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
299 val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep)); 300 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
300 } 301 }
301 302
302 dwc2_writel(hsotg->hw_params.total_fifo_size | 303 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
303 addr << GDFIFOCFG_EPINFOBASE_SHIFT, 304 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
304 hsotg->regs + GDFIFOCFG); 305 GDFIFOCFG);
305 /* 306 /*
306 * according to p428 of the design guide, we need to ensure that 307 * according to p428 of the design guide, we need to ensure that
307 * all fifos are flushed before continuing 308 * all fifos are flushed before continuing
308 */ 309 */
309 310
310 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | 311 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
311 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); 312 GRSTCTL_RXFFLSH, GRSTCTL);
312 313
313 /* wait until the fifos are both flushed */ 314 /* wait until the fifos are both flushed */
314 timeout = 100; 315 timeout = 100;
315 while (1) { 316 while (1) {
316 val = dwc2_readl(hsotg->regs + GRSTCTL); 317 val = dwc2_readl(hsotg, GRSTCTL);
317 318
318 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) 319 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
319 break; 320 break;
@@ -451,7 +452,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
451 struct dwc2_hsotg_req *hs_req) 452 struct dwc2_hsotg_req *hs_req)
452{ 453{
453 bool periodic = is_ep_periodic(hs_ep); 454 bool periodic = is_ep_periodic(hs_ep);
454 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); 455 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
455 int buf_pos = hs_req->req.actual; 456 int buf_pos = hs_req->req.actual;
456 int to_write = hs_ep->size_loaded; 457 int to_write = hs_ep->size_loaded;
457 void *data; 458 void *data;
@@ -466,7 +467,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
466 return 0; 467 return 0;
467 468
468 if (periodic && !hsotg->dedicated_fifos) { 469 if (periodic && !hsotg->dedicated_fifos) {
469 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); 470 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
470 int size_left; 471 int size_left;
471 int size_done; 472 int size_done;
472 473
@@ -507,8 +508,8 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
507 return -ENOSPC; 508 return -ENOSPC;
508 } 509 }
509 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { 510 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
510 can_write = dwc2_readl(hsotg->regs + 511 can_write = dwc2_readl(hsotg,
511 DTXFSTS(hs_ep->fifo_index)); 512 DTXFSTS(hs_ep->fifo_index));
512 513
513 can_write &= 0xffff; 514 can_write &= 0xffff;
514 can_write *= 4; 515 can_write *= 4;
@@ -652,7 +653,7 @@ static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
652{ 653{
653 u32 dsts; 654 u32 dsts;
654 655
655 dsts = dwc2_readl(hsotg->regs + DSTS); 656 dsts = dwc2_readl(hsotg, DSTS);
656 dsts &= DSTS_SOFFN_MASK; 657 dsts &= DSTS_SOFFN_MASK;
657 dsts >>= DSTS_SOFFN_SHIFT; 658 dsts >>= DSTS_SOFFN_SHIFT;
658 659
@@ -915,11 +916,11 @@ static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
915 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); 916 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
916 917
917 /* write descriptor chain address to control register */ 918 /* write descriptor chain address to control register */
918 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); 919 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
919 920
920 ctrl = dwc2_readl(hsotg->regs + depctl); 921 ctrl = dwc2_readl(hsotg, depctl);
921 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; 922 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
922 dwc2_writel(ctrl, hsotg->regs + depctl); 923 dwc2_writel(hsotg, ctrl, depctl);
923} 924}
924 925
925/** 926/**
@@ -967,11 +968,11 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
967 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); 968 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
968 969
969 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", 970 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
970 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, 971 __func__, dwc2_readl(hsotg, epctrl_reg), index,
971 hs_ep->dir_in ? "in" : "out"); 972 hs_ep->dir_in ? "in" : "out");
972 973
973 /* If endpoint is stalled, we will restart request later */ 974 /* If endpoint is stalled, we will restart request later */
974 ctrl = dwc2_readl(hsotg->regs + epctrl_reg); 975 ctrl = dwc2_readl(hsotg, epctrl_reg);
975 976
976 if (index && ctrl & DXEPCTL_STALL) { 977 if (index && ctrl & DXEPCTL_STALL) {
977 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); 978 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
@@ -1064,13 +1065,13 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1064 length); 1065 length);
1065 1066
1066 /* write descriptor chain address to control register */ 1067 /* write descriptor chain address to control register */
1067 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); 1068 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1068 1069
1069 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", 1070 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1070 __func__, (u32)hs_ep->desc_list_dma, dma_reg); 1071 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1071 } else { 1072 } else {
1072 /* write size / packets */ 1073 /* write size / packets */
1073 dwc2_writel(epsize, hsotg->regs + epsize_reg); 1074 dwc2_writel(hsotg, epsize, epsize_reg);
1074 1075
1075 if (using_dma(hsotg) && !continuing && (length != 0)) { 1076 if (using_dma(hsotg) && !continuing && (length != 0)) {
1076 /* 1077 /*
@@ -1078,7 +1079,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1078 * already synced by dwc2_hsotg_ep_queue(). 1079 * already synced by dwc2_hsotg_ep_queue().
1079 */ 1080 */
1080 1081
1081 dwc2_writel(ureq->dma, hsotg->regs + dma_reg); 1082 dwc2_writel(hsotg, ureq->dma, dma_reg);
1082 1083
1083 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", 1084 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1084 __func__, &ureq->dma, dma_reg); 1085 __func__, &ureq->dma, dma_reg);
@@ -1104,7 +1105,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1104 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ 1105 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1105 1106
1106 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); 1107 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1107 dwc2_writel(ctrl, hsotg->regs + epctrl_reg); 1108 dwc2_writel(hsotg, ctrl, epctrl_reg);
1108 1109
1109 /* 1110 /*
1110 * set these, it seems that DMA support increments past the end 1111 * set these, it seems that DMA support increments past the end
@@ -1127,13 +1128,13 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1127 */ 1128 */
1128 1129
1129 /* check ep is enabled */ 1130 /* check ep is enabled */
1130 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) 1131 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1131 dev_dbg(hsotg->dev, 1132 dev_dbg(hsotg->dev,
1132 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", 1133 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1133 index, dwc2_readl(hsotg->regs + epctrl_reg)); 1134 index, dwc2_readl(hsotg, epctrl_reg));
1134 1135
1135 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", 1136 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1136 __func__, dwc2_readl(hsotg->regs + epctrl_reg)); 1137 __func__, dwc2_readl(hsotg, epctrl_reg));
1137 1138
1138 /* enable ep interrupts */ 1139 /* enable ep interrupts */
1139 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); 1140 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
@@ -1466,7 +1467,7 @@ static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1466 */ 1467 */
1467int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) 1468int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1468{ 1469{
1469 int dctl = dwc2_readl(hsotg->regs + DCTL); 1470 int dctl = dwc2_readl(hsotg, DCTL);
1470 1471
1471 dctl &= ~DCTL_TSTCTL_MASK; 1472 dctl &= ~DCTL_TSTCTL_MASK;
1472 switch (testmode) { 1473 switch (testmode) {
@@ -1480,7 +1481,7 @@ int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1480 default: 1481 default:
1481 return -EINVAL; 1482 return -EINVAL;
1482 } 1483 }
1483 dwc2_writel(dctl, hsotg->regs + DCTL); 1484 dwc2_writel(hsotg, dctl, DCTL);
1484 return 0; 1485 return 0;
1485} 1486}
1486 1487
@@ -1634,9 +1635,9 @@ static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1634 } else { 1635 } else {
1635 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", 1636 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1636 __func__); 1637 __func__);
1637 mask = dwc2_readl(hsotg->regs + epmsk_reg); 1638 mask = dwc2_readl(hsotg, epmsk_reg);
1638 mask |= DOEPMSK_OUTTKNEPDISMSK; 1639 mask |= DOEPMSK_OUTTKNEPDISMSK;
1639 dwc2_writel(mask, hsotg->regs + epmsk_reg); 1640 dwc2_writel(hsotg, mask, epmsk_reg);
1640 } 1641 }
1641} 1642}
1642 1643
@@ -1773,14 +1774,14 @@ static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1773 * taken effect, so no need to clear later. 1774 * taken effect, so no need to clear later.
1774 */ 1775 */
1775 1776
1776 ctrl = dwc2_readl(hsotg->regs + reg); 1777 ctrl = dwc2_readl(hsotg, reg);
1777 ctrl |= DXEPCTL_STALL; 1778 ctrl |= DXEPCTL_STALL;
1778 ctrl |= DXEPCTL_CNAK; 1779 ctrl |= DXEPCTL_CNAK;
1779 dwc2_writel(ctrl, hsotg->regs + reg); 1780 dwc2_writel(hsotg, ctrl, reg);
1780 1781
1781 dev_dbg(hsotg->dev, 1782 dev_dbg(hsotg->dev,
1782 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", 1783 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1783 ctrl, reg, dwc2_readl(hsotg->regs + reg)); 1784 ctrl, reg, dwc2_readl(hsotg, reg));
1784 1785
1785 /* 1786 /*
1786 * complete won't be called, so we enqueue 1787 * complete won't be called, so we enqueue
@@ -1825,11 +1826,11 @@ static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1825 switch (ctrl->bRequest) { 1826 switch (ctrl->bRequest) {
1826 case USB_REQ_SET_ADDRESS: 1827 case USB_REQ_SET_ADDRESS:
1827 hsotg->connected = 1; 1828 hsotg->connected = 1;
1828 dcfg = dwc2_readl(hsotg->regs + DCFG); 1829 dcfg = dwc2_readl(hsotg, DCFG);
1829 dcfg &= ~DCFG_DEVADDR_MASK; 1830 dcfg &= ~DCFG_DEVADDR_MASK;
1830 dcfg |= (le16_to_cpu(ctrl->wValue) << 1831 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1831 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; 1832 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1832 dwc2_writel(dcfg, hsotg->regs + DCFG); 1833 dwc2_writel(hsotg, dcfg, DCFG);
1833 1834
1834 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); 1835 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1835 1836
@@ -1955,16 +1956,16 @@ static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1955 1956
1956 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); 1957 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
1957 } else { 1958 } else {
1958 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | 1959 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1959 DXEPTSIZ_XFERSIZE(0), hsotg->regs + 1960 DXEPTSIZ_XFERSIZE(0),
1960 epsiz_reg); 1961 epsiz_reg);
1961 } 1962 }
1962 1963
1963 ctrl = dwc2_readl(hsotg->regs + epctl_reg); 1964 ctrl = dwc2_readl(hsotg, epctl_reg);
1964 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ 1965 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1965 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ 1966 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1966 ctrl |= DXEPCTL_USBACTEP; 1967 ctrl |= DXEPCTL_USBACTEP;
1967 dwc2_writel(ctrl, hsotg->regs + epctl_reg); 1968 dwc2_writel(hsotg, ctrl, epctl_reg);
1968} 1969}
1969 1970
1970/** 1971/**
@@ -2124,13 +2125,12 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2124{ 2125{
2125 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; 2126 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2126 struct dwc2_hsotg_req *hs_req = hs_ep->req; 2127 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2127 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
2128 int to_read; 2128 int to_read;
2129 int max_req; 2129 int max_req;
2130 int read_ptr; 2130 int read_ptr;
2131 2131
2132 if (!hs_req) { 2132 if (!hs_req) {
2133 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); 2133 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2134 int ptr; 2134 int ptr;
2135 2135
2136 dev_dbg(hsotg->dev, 2136 dev_dbg(hsotg->dev,
@@ -2139,7 +2139,7 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2139 2139
2140 /* dump the data from the FIFO, we've nothing we can do */ 2140 /* dump the data from the FIFO, we've nothing we can do */
2141 for (ptr = 0; ptr < size; ptr += 4) 2141 for (ptr = 0; ptr < size; ptr += 4)
2142 (void)dwc2_readl(fifo); 2142 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2143 2143
2144 return; 2144 return;
2145 } 2145 }
@@ -2169,7 +2169,8 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2169 * note, we might over-write the buffer end by 3 bytes depending on 2169 * note, we might over-write the buffer end by 3 bytes depending on
2170 * alignment of the data. 2170 * alignment of the data.
2171 */ 2171 */
2172 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); 2172 ioread32_rep(hsotg->regs + EPFIFO(ep_idx),
2173 hs_req->req.buf + read_ptr, to_read);
2173} 2174}
2174 2175
2175/** 2176/**
@@ -2198,12 +2199,12 @@ static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2198{ 2199{
2199 u32 ctrl; 2200 u32 ctrl;
2200 2201
2201 ctrl = dwc2_readl(hsotg->regs + epctl_reg); 2202 ctrl = dwc2_readl(hsotg, epctl_reg);
2202 if (ctrl & DXEPCTL_EOFRNUM) 2203 if (ctrl & DXEPCTL_EOFRNUM)
2203 ctrl |= DXEPCTL_SETEVENFR; 2204 ctrl |= DXEPCTL_SETEVENFR;
2204 else 2205 else
2205 ctrl |= DXEPCTL_SETODDFR; 2206 ctrl |= DXEPCTL_SETODDFR;
2206 dwc2_writel(ctrl, hsotg->regs + epctl_reg); 2207 dwc2_writel(hsotg, ctrl, epctl_reg);
2207} 2208}
2208 2209
2209/* 2210/*
@@ -2247,7 +2248,7 @@ static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2247 */ 2248 */
2248static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) 2249static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2249{ 2250{
2250 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); 2251 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2251 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; 2252 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2252 struct dwc2_hsotg_req *hs_req = hs_ep->req; 2253 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2253 struct usb_request *req = &hs_req->req; 2254 struct usb_request *req = &hs_req->req;
@@ -2343,7 +2344,7 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2343 */ 2344 */
2344static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) 2345static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2345{ 2346{
2346 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); 2347 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2347 u32 epnum, status, size; 2348 u32 epnum, status, size;
2348 2349
2349 WARN_ON(using_dma(hsotg)); 2350 WARN_ON(using_dma(hsotg));
@@ -2374,7 +2375,7 @@ static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2374 dev_dbg(hsotg->dev, 2375 dev_dbg(hsotg->dev,
2375 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", 2376 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2376 dwc2_hsotg_read_frameno(hsotg), 2377 dwc2_hsotg_read_frameno(hsotg),
2377 dwc2_readl(hsotg->regs + DOEPCTL(0))); 2378 dwc2_readl(hsotg, DOEPCTL(0)));
2378 /* 2379 /*
2379 * Call dwc2_hsotg_handle_outdone here if it was not called from 2380 * Call dwc2_hsotg_handle_outdone here if it was not called from
2380 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't 2381 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
@@ -2392,7 +2393,7 @@ static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2392 dev_dbg(hsotg->dev, 2393 dev_dbg(hsotg->dev,
2393 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", 2394 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2394 dwc2_hsotg_read_frameno(hsotg), 2395 dwc2_hsotg_read_frameno(hsotg),
2395 dwc2_readl(hsotg->regs + DOEPCTL(0))); 2396 dwc2_readl(hsotg, DOEPCTL(0)));
2396 2397
2397 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); 2398 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2398 2399
@@ -2446,7 +2447,6 @@ static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2446 unsigned int mc, unsigned int dir_in) 2447 unsigned int mc, unsigned int dir_in)
2447{ 2448{
2448 struct dwc2_hsotg_ep *hs_ep; 2449 struct dwc2_hsotg_ep *hs_ep;
2449 void __iomem *regs = hsotg->regs;
2450 u32 reg; 2450 u32 reg;
2451 2451
2452 hs_ep = index_to_ep(hsotg, ep, dir_in); 2452 hs_ep = index_to_ep(hsotg, ep, dir_in);
@@ -2472,15 +2472,15 @@ static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2472 } 2472 }
2473 2473
2474 if (dir_in) { 2474 if (dir_in) {
2475 reg = dwc2_readl(regs + DIEPCTL(ep)); 2475 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2476 reg &= ~DXEPCTL_MPS_MASK; 2476 reg &= ~DXEPCTL_MPS_MASK;
2477 reg |= mps; 2477 reg |= mps;
2478 dwc2_writel(reg, regs + DIEPCTL(ep)); 2478 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2479 } else { 2479 } else {
2480 reg = dwc2_readl(regs + DOEPCTL(ep)); 2480 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2481 reg &= ~DXEPCTL_MPS_MASK; 2481 reg &= ~DXEPCTL_MPS_MASK;
2482 reg |= mps; 2482 reg |= mps;
2483 dwc2_writel(reg, regs + DOEPCTL(ep)); 2483 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2484 } 2484 }
2485 2485
2486 return; 2486 return;
@@ -2496,8 +2496,8 @@ bad_mps:
2496 */ 2496 */
2497static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) 2497static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2498{ 2498{
2499 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, 2499 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2500 hsotg->regs + GRSTCTL); 2500 GRSTCTL);
2501 2501
2502 /* wait until the fifo is flushed */ 2502 /* wait until the fifo is flushed */
2503 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100)) 2503 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
@@ -2550,7 +2550,7 @@ static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2550 struct dwc2_hsotg_ep *hs_ep) 2550 struct dwc2_hsotg_ep *hs_ep)
2551{ 2551{
2552 struct dwc2_hsotg_req *hs_req = hs_ep->req; 2552 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2553 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); 2553 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2554 int size_left, size_done; 2554 int size_left, size_done;
2555 2555
2556 if (!hs_req) { 2556 if (!hs_req) {
@@ -2654,12 +2654,12 @@ static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2654 u32 mask; 2654 u32 mask;
2655 u32 diepempmsk; 2655 u32 diepempmsk;
2656 2656
2657 mask = dwc2_readl(hsotg->regs + epmsk_reg); 2657 mask = dwc2_readl(hsotg, epmsk_reg);
2658 diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK); 2658 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2659 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; 2659 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2660 mask |= DXEPINT_SETUP_RCVD; 2660 mask |= DXEPINT_SETUP_RCVD;
2661 2661
2662 ints = dwc2_readl(hsotg->regs + epint_reg); 2662 ints = dwc2_readl(hsotg, epint_reg);
2663 ints &= mask; 2663 ints &= mask;
2664 return ints; 2664 return ints;
2665} 2665}
@@ -2684,12 +2684,12 @@ static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2684 unsigned char idx = hs_ep->index; 2684 unsigned char idx = hs_ep->index;
2685 int dir_in = hs_ep->dir_in; 2685 int dir_in = hs_ep->dir_in;
2686 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); 2686 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2687 int dctl = dwc2_readl(hsotg->regs + DCTL); 2687 int dctl = dwc2_readl(hsotg, DCTL);
2688 2688
2689 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); 2689 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2690 2690
2691 if (dir_in) { 2691 if (dir_in) {
2692 int epctl = dwc2_readl(hsotg->regs + epctl_reg); 2692 int epctl = dwc2_readl(hsotg, epctl_reg);
2693 2693
2694 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); 2694 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2695 2695
@@ -2699,17 +2699,17 @@ static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2699 } 2699 }
2700 2700
2701 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { 2701 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2702 int dctl = dwc2_readl(hsotg->regs + DCTL); 2702 int dctl = dwc2_readl(hsotg, DCTL);
2703 2703
2704 dctl |= DCTL_CGNPINNAK; 2704 dctl |= DCTL_CGNPINNAK;
2705 dwc2_writel(dctl, hsotg->regs + DCTL); 2705 dwc2_writel(hsotg, dctl, DCTL);
2706 } 2706 }
2707 return; 2707 return;
2708 } 2708 }
2709 2709
2710 if (dctl & DCTL_GOUTNAKSTS) { 2710 if (dctl & DCTL_GOUTNAKSTS) {
2711 dctl |= DCTL_CGOUTNAK; 2711 dctl |= DCTL_CGOUTNAK;
2712 dwc2_writel(dctl, hsotg->regs + DCTL); 2712 dwc2_writel(hsotg, dctl, DCTL);
2713 } 2713 }
2714 2714
2715 if (!hs_ep->isochronous) 2715 if (!hs_ep->isochronous)
@@ -2775,23 +2775,23 @@ static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2775 u32 dsts; 2775 u32 dsts;
2776 u32 ctrl; 2776 u32 ctrl;
2777 2777
2778 dsts = dwc2_readl(hsotg->regs + DSTS); 2778 dsts = dwc2_readl(hsotg, DSTS);
2779 ep->target_frame = dwc2_hsotg_read_frameno(hsotg); 2779 ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2780 dwc2_gadget_incr_frame_num(ep); 2780 dwc2_gadget_incr_frame_num(ep);
2781 2781
2782 ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index)); 2782 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2783 if (ep->target_frame & 0x1) 2783 if (ep->target_frame & 0x1)
2784 ctrl |= DXEPCTL_SETODDFR; 2784 ctrl |= DXEPCTL_SETODDFR;
2785 else 2785 else
2786 ctrl |= DXEPCTL_SETEVENFR; 2786 ctrl |= DXEPCTL_SETEVENFR;
2787 2787
2788 dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index)); 2788 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2789 } 2789 }
2790 2790
2791 dwc2_gadget_start_next_request(ep); 2791 dwc2_gadget_start_next_request(ep);
2792 doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); 2792 doepmsk = dwc2_readl(hsotg, DOEPMSK);
2793 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; 2793 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2794 dwc2_writel(doepmsk, hsotg->regs + DOEPMSK); 2794 dwc2_writel(hsotg, doepmsk, DOEPMSK);
2795} 2795}
2796 2796
2797/** 2797/**
@@ -2829,14 +2829,14 @@ static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2829 2829
2830 hs_ep->target_frame = tmp; 2830 hs_ep->target_frame = tmp;
2831 if (hs_ep->interval > 1) { 2831 if (hs_ep->interval > 1) {
2832 u32 ctrl = dwc2_readl(hsotg->regs + 2832 u32 ctrl = dwc2_readl(hsotg,
2833 DIEPCTL(hs_ep->index)); 2833 DIEPCTL(hs_ep->index));
2834 if (hs_ep->target_frame & 0x1) 2834 if (hs_ep->target_frame & 0x1)
2835 ctrl |= DXEPCTL_SETODDFR; 2835 ctrl |= DXEPCTL_SETODDFR;
2836 else 2836 else
2837 ctrl |= DXEPCTL_SETEVENFR; 2837 ctrl |= DXEPCTL_SETEVENFR;
2838 2838
2839 dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index)); 2839 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2840 } 2840 }
2841 2841
2842 dwc2_hsotg_complete_request(hsotg, hs_ep, 2842 dwc2_hsotg_complete_request(hsotg, hs_ep,
@@ -2866,10 +2866,10 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2866 u32 ctrl; 2866 u32 ctrl;
2867 2867
2868 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); 2868 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2869 ctrl = dwc2_readl(hsotg->regs + epctl_reg); 2869 ctrl = dwc2_readl(hsotg, epctl_reg);
2870 2870
2871 /* Clear endpoint interrupts */ 2871 /* Clear endpoint interrupts */
2872 dwc2_writel(ints, hsotg->regs + epint_reg); 2872 dwc2_writel(hsotg, ints, epint_reg);
2873 2873
2874 if (!hs_ep) { 2874 if (!hs_ep) {
2875 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", 2875 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
@@ -2897,8 +2897,8 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2897 if (ints & DXEPINT_XFERCOMPL) { 2897 if (ints & DXEPINT_XFERCOMPL) {
2898 dev_dbg(hsotg->dev, 2898 dev_dbg(hsotg->dev,
2899 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", 2899 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2900 __func__, dwc2_readl(hsotg->regs + epctl_reg), 2900 __func__, dwc2_readl(hsotg, epctl_reg),
2901 dwc2_readl(hsotg->regs + epsiz_reg)); 2901 dwc2_readl(hsotg, epsiz_reg));
2902 2902
2903 /* In DDMA handle isochronous requests separately */ 2903 /* In DDMA handle isochronous requests separately */
2904 if (using_desc_dma(hsotg) && hs_ep->isochronous) { 2904 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
@@ -3016,7 +3016,7 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3016 */ 3016 */
3017static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) 3017static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3018{ 3018{
3019 u32 dsts = dwc2_readl(hsotg->regs + DSTS); 3019 u32 dsts = dwc2_readl(hsotg, DSTS);
3020 int ep0_mps = 0, ep_mps = 8; 3020 int ep0_mps = 0, ep_mps = 8;
3021 3021
3022 /* 3022 /*
@@ -3087,8 +3087,8 @@ static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3087 dwc2_hsotg_enqueue_setup(hsotg); 3087 dwc2_hsotg_enqueue_setup(hsotg);
3088 3088
3089 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 3089 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3090 dwc2_readl(hsotg->regs + DIEPCTL0), 3090 dwc2_readl(hsotg, DIEPCTL0),
3091 dwc2_readl(hsotg->regs + DOEPCTL0)); 3091 dwc2_readl(hsotg, DOEPCTL0));
3092} 3092}
3093 3093
3094/** 3094/**
@@ -3115,7 +3115,7 @@ static void kill_all_requests(struct dwc2_hsotg *hsotg,
3115 3115
3116 if (!hsotg->dedicated_fifos) 3116 if (!hsotg->dedicated_fifos)
3117 return; 3117 return;
3118 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4; 3118 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3119 if (size < ep->fifo_size) 3119 if (size < ep->fifo_size)
3120 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); 3120 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3121} 3121}
@@ -3216,7 +3216,7 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3216 */ 3216 */
3217 3217
3218 /* keep other bits untouched (so e.g. forced modes are not lost) */ 3218 /* keep other bits untouched (so e.g. forced modes are not lost) */
3219 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 3219 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3220 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | 3220 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3221 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); 3221 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
3222 3222
@@ -3231,12 +3231,12 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3231 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | 3231 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3232 (val << GUSBCFG_USBTRDTIM_SHIFT); 3232 (val << GUSBCFG_USBTRDTIM_SHIFT);
3233 } 3233 }
3234 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 3234 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3235 3235
3236 dwc2_hsotg_init_fifo(hsotg); 3236 dwc2_hsotg_init_fifo(hsotg);
3237 3237
3238 if (!is_usb_reset) 3238 if (!is_usb_reset)
3239 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); 3239 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3240 3240
3241 dcfg |= DCFG_EPMISCNT(1); 3241 dcfg |= DCFG_EPMISCNT(1);
3242 3242
@@ -3257,13 +3257,13 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3257 if (hsotg->params.ipg_isoc_en) 3257 if (hsotg->params.ipg_isoc_en)
3258 dcfg |= DCFG_IPG_ISOC_SUPPORDED; 3258 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3259 3259
3260 dwc2_writel(dcfg, hsotg->regs + DCFG); 3260 dwc2_writel(hsotg, dcfg, DCFG);
3261 3261
3262 /* Clear any pending OTG interrupts */ 3262 /* Clear any pending OTG interrupts */
3263 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); 3263 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3264 3264
3265 /* Clear any pending interrupts */ 3265 /* Clear any pending interrupts */
3266 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 3266 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3267 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | 3267 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3268 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | 3268 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3269 GINTSTS_USBRST | GINTSTS_RESETDET | 3269 GINTSTS_USBRST | GINTSTS_RESETDET |
@@ -3277,22 +3277,22 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3277 if (!hsotg->params.external_id_pin_ctl) 3277 if (!hsotg->params.external_id_pin_ctl)
3278 intmsk |= GINTSTS_CONIDSTSCHNG; 3278 intmsk |= GINTSTS_CONIDSTSCHNG;
3279 3279
3280 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 3280 dwc2_writel(hsotg, intmsk, GINTMSK);
3281 3281
3282 if (using_dma(hsotg)) { 3282 if (using_dma(hsotg)) {
3283 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | 3283 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3284 hsotg->params.ahbcfg, 3284 hsotg->params.ahbcfg,
3285 hsotg->regs + GAHBCFG); 3285 GAHBCFG);
3286 3286
3287 /* Set DDMA mode support in the core if needed */ 3287 /* Set DDMA mode support in the core if needed */
3288 if (using_desc_dma(hsotg)) 3288 if (using_desc_dma(hsotg))
3289 dwc2_set_bit(hsotg->regs + DCFG, DCFG_DESCDMA_EN); 3289 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3290 3290
3291 } else { 3291 } else {
3292 dwc2_writel(((hsotg->dedicated_fifos) ? 3292 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3293 (GAHBCFG_NP_TXF_EMP_LVL | 3293 (GAHBCFG_NP_TXF_EMP_LVL |
3294 GAHBCFG_P_TXF_EMP_LVL) : 0) | 3294 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3295 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); 3295 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3296 } 3296 }
3297 3297
3298 /* 3298 /*
@@ -3301,33 +3301,33 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3301 * interrupts. 3301 * interrupts.
3302 */ 3302 */
3303 3303
3304 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? 3304 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3305 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | 3305 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3306 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | 3306 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3307 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, 3307 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3308 hsotg->regs + DIEPMSK); 3308 DIEPMSK);
3309 3309
3310 /* 3310 /*
3311 * don't need XferCompl, we get that from RXFIFO in slave mode. In 3311 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3312 * DMA mode we may need this and StsPhseRcvd. 3312 * DMA mode we may need this and StsPhseRcvd.
3313 */ 3313 */
3314 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | 3314 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3315 DOEPMSK_STSPHSERCVDMSK) : 0) | 3315 DOEPMSK_STSPHSERCVDMSK) : 0) |
3316 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | 3316 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3317 DOEPMSK_SETUPMSK, 3317 DOEPMSK_SETUPMSK,
3318 hsotg->regs + DOEPMSK); 3318 DOEPMSK);
3319 3319
3320 /* Enable BNA interrupt for DDMA */ 3320 /* Enable BNA interrupt for DDMA */
3321 if (using_desc_dma(hsotg)) { 3321 if (using_desc_dma(hsotg)) {
3322 dwc2_set_bit(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK); 3322 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3323 dwc2_set_bit(hsotg->regs + DIEPMSK, DIEPMSK_BNAININTRMSK); 3323 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3324 } 3324 }
3325 3325
3326 dwc2_writel(0, hsotg->regs + DAINTMSK); 3326 dwc2_writel(hsotg, 0, DAINTMSK);
3327 3327
3328 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 3328 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3329 dwc2_readl(hsotg->regs + DIEPCTL0), 3329 dwc2_readl(hsotg, DIEPCTL0),
3330 dwc2_readl(hsotg->regs + DOEPCTL0)); 3330 dwc2_readl(hsotg, DOEPCTL0));
3331 3331
3332 /* enable in and out endpoint interrupts */ 3332 /* enable in and out endpoint interrupts */
3333 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); 3333 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
@@ -3345,12 +3345,12 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3345 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); 3345 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3346 3346
3347 if (!is_usb_reset) { 3347 if (!is_usb_reset) {
3348 dwc2_set_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); 3348 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3349 udelay(10); /* see openiboot */ 3349 udelay(10); /* see openiboot */
3350 dwc2_clear_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); 3350 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3351 } 3351 }
3352 3352
3353 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); 3353 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3354 3354
3355 /* 3355 /*
3356 * DxEPCTL_USBActEp says RO in manual, but seems to be set by 3356 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
@@ -3358,23 +3358,23 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3358 */ 3358 */
3359 3359
3360 /* set to read 1 8byte packet */ 3360 /* set to read 1 8byte packet */
3361 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | 3361 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3362 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); 3362 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3363 3363
3364 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | 3364 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3365 DXEPCTL_CNAK | DXEPCTL_EPENA | 3365 DXEPCTL_CNAK | DXEPCTL_EPENA |
3366 DXEPCTL_USBACTEP, 3366 DXEPCTL_USBACTEP,
3367 hsotg->regs + DOEPCTL0); 3367 DOEPCTL0);
3368 3368
3369 /* enable, but don't activate EP0in */ 3369 /* enable, but don't activate EP0in */
3370 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | 3370 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3371 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); 3371 DXEPCTL_USBACTEP, DIEPCTL0);
3372 3372
3373 /* clear global NAKs */ 3373 /* clear global NAKs */
3374 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; 3374 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3375 if (!is_usb_reset) 3375 if (!is_usb_reset)
3376 val |= DCTL_SFTDISCON; 3376 val |= DCTL_SFTDISCON;
3377 dwc2_set_bit(hsotg->regs + DCTL, val); 3377 dwc2_set_bit(hsotg, DCTL, val);
3378 3378
3379 /* configure the core to support LPM */ 3379 /* configure the core to support LPM */
3380 dwc2_gadget_init_lpm(hsotg); 3380 dwc2_gadget_init_lpm(hsotg);
@@ -3387,20 +3387,20 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3387 dwc2_hsotg_enqueue_setup(hsotg); 3387 dwc2_hsotg_enqueue_setup(hsotg);
3388 3388
3389 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 3389 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3390 dwc2_readl(hsotg->regs + DIEPCTL0), 3390 dwc2_readl(hsotg, DIEPCTL0),
3391 dwc2_readl(hsotg->regs + DOEPCTL0)); 3391 dwc2_readl(hsotg, DOEPCTL0));
3392} 3392}
3393 3393
3394static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) 3394static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3395{ 3395{
3396 /* set the soft-disconnect bit */ 3396 /* set the soft-disconnect bit */
3397 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); 3397 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3398} 3398}
3399 3399
3400void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) 3400void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3401{ 3401{
3402 /* remove the soft-disconnect and let's go */ 3402 /* remove the soft-disconnect and let's go */
3403 dwc2_clear_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); 3403 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3404} 3404}
3405 3405
3406/** 3406/**
@@ -3425,7 +3425,7 @@ static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3425 3425
3426 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); 3426 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3427 3427
3428 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 3428 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3429 3429
3430 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 3430 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3431 hs_ep = hsotg->eps_in[idx]; 3431 hs_ep = hsotg->eps_in[idx];
@@ -3433,17 +3433,17 @@ static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3433 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk)) 3433 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk))
3434 continue; 3434 continue;
3435 3435
3436 epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx)); 3436 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3437 if ((epctrl & DXEPCTL_EPENA) && 3437 if ((epctrl & DXEPCTL_EPENA) &&
3438 dwc2_gadget_target_frame_elapsed(hs_ep)) { 3438 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3439 epctrl |= DXEPCTL_SNAK; 3439 epctrl |= DXEPCTL_SNAK;
3440 epctrl |= DXEPCTL_EPDIS; 3440 epctrl |= DXEPCTL_EPDIS;
3441 dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx)); 3441 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3442 } 3442 }
3443 } 3443 }
3444 3444
3445 /* Clear interrupt */ 3445 /* Clear interrupt */
3446 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS); 3446 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3447} 3447}
3448 3448
3449/** 3449/**
@@ -3470,7 +3470,7 @@ static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3470 3470
3471 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); 3471 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3472 3472
3473 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 3473 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3474 daintmsk >>= DAINT_OUTEP_SHIFT; 3474 daintmsk >>= DAINT_OUTEP_SHIFT;
3475 3475
3476 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 3476 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
@@ -3479,24 +3479,24 @@ static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3479 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk)) 3479 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk))
3480 continue; 3480 continue;
3481 3481
3482 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); 3482 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3483 if ((epctrl & DXEPCTL_EPENA) && 3483 if ((epctrl & DXEPCTL_EPENA) &&
3484 dwc2_gadget_target_frame_elapsed(hs_ep)) { 3484 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3485 /* Unmask GOUTNAKEFF interrupt */ 3485 /* Unmask GOUTNAKEFF interrupt */
3486 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3486 gintmsk = dwc2_readl(hsotg, GINTMSK);
3487 gintmsk |= GINTSTS_GOUTNAKEFF; 3487 gintmsk |= GINTSTS_GOUTNAKEFF;
3488 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3488 dwc2_writel(hsotg, gintmsk, GINTMSK);
3489 3489
3490 gintsts = dwc2_readl(hsotg->regs + GINTSTS); 3490 gintsts = dwc2_readl(hsotg, GINTSTS);
3491 if (!(gintsts & GINTSTS_GOUTNAKEFF)) { 3491 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3492 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK); 3492 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3493 break; 3493 break;
3494 } 3494 }
3495 } 3495 }
3496 } 3496 }
3497 3497
3498 /* Clear interrupt */ 3498 /* Clear interrupt */
3499 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS); 3499 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3500} 3500}
3501 3501
3502/** 3502/**
@@ -3516,8 +3516,8 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3516 3516
3517 spin_lock(&hsotg->lock); 3517 spin_lock(&hsotg->lock);
3518irq_retry: 3518irq_retry:
3519 gintsts = dwc2_readl(hsotg->regs + GINTSTS); 3519 gintsts = dwc2_readl(hsotg, GINTSTS);
3520 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3520 gintmsk = dwc2_readl(hsotg, GINTMSK);
3521 3521
3522 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", 3522 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3523 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); 3523 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
@@ -3527,7 +3527,7 @@ irq_retry:
3527 if (gintsts & GINTSTS_RESETDET) { 3527 if (gintsts & GINTSTS_RESETDET) {
3528 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); 3528 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3529 3529
3530 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); 3530 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3531 3531
3532 /* This event must be used only if controller is suspended */ 3532 /* This event must be used only if controller is suspended */
3533 if (hsotg->lx_state == DWC2_L2) { 3533 if (hsotg->lx_state == DWC2_L2) {
@@ -3537,34 +3537,34 @@ irq_retry:
3537 } 3537 }
3538 3538
3539 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { 3539 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3540 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); 3540 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3541 u32 connected = hsotg->connected; 3541 u32 connected = hsotg->connected;
3542 3542
3543 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); 3543 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3544 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", 3544 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3545 dwc2_readl(hsotg->regs + GNPTXSTS)); 3545 dwc2_readl(hsotg, GNPTXSTS));
3546 3546
3547 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); 3547 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3548 3548
3549 /* Report disconnection if it is not already done. */ 3549 /* Report disconnection if it is not already done. */
3550 dwc2_hsotg_disconnect(hsotg); 3550 dwc2_hsotg_disconnect(hsotg);
3551 3551
3552 /* Reset device address to zero */ 3552 /* Reset device address to zero */
3553 dwc2_clear_bit(hsotg->regs + DCFG, DCFG_DEVADDR_MASK); 3553 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3554 3554
3555 if (usb_status & GOTGCTL_BSESVLD && connected) 3555 if (usb_status & GOTGCTL_BSESVLD && connected)
3556 dwc2_hsotg_core_init_disconnected(hsotg, true); 3556 dwc2_hsotg_core_init_disconnected(hsotg, true);
3557 } 3557 }
3558 3558
3559 if (gintsts & GINTSTS_ENUMDONE) { 3559 if (gintsts & GINTSTS_ENUMDONE) {
3560 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); 3560 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3561 3561
3562 dwc2_hsotg_irq_enumdone(hsotg); 3562 dwc2_hsotg_irq_enumdone(hsotg);
3563 } 3563 }
3564 3564
3565 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { 3565 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3566 u32 daint = dwc2_readl(hsotg->regs + DAINT); 3566 u32 daint = dwc2_readl(hsotg, DAINT);
3567 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 3567 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3568 u32 daint_out, daint_in; 3568 u32 daint_out, daint_in;
3569 int ep; 3569 int ep;
3570 3570
@@ -3623,7 +3623,7 @@ irq_retry:
3623 3623
3624 if (gintsts & GINTSTS_ERLYSUSP) { 3624 if (gintsts & GINTSTS_ERLYSUSP) {
3625 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); 3625 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3626 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); 3626 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3627 } 3627 }
3628 3628
3629 /* 3629 /*
@@ -3639,12 +3639,12 @@ irq_retry:
3639 u32 daintmsk; 3639 u32 daintmsk;
3640 struct dwc2_hsotg_ep *hs_ep; 3640 struct dwc2_hsotg_ep *hs_ep;
3641 3641
3642 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 3642 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3643 daintmsk >>= DAINT_OUTEP_SHIFT; 3643 daintmsk >>= DAINT_OUTEP_SHIFT;
3644 /* Mask this interrupt */ 3644 /* Mask this interrupt */
3645 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3645 gintmsk = dwc2_readl(hsotg, GINTMSK);
3646 gintmsk &= ~GINTSTS_GOUTNAKEFF; 3646 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3647 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3647 dwc2_writel(hsotg, gintmsk, GINTMSK);
3648 3648
3649 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); 3649 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3650 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 3650 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
@@ -3653,12 +3653,12 @@ irq_retry:
3653 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk)) 3653 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk))
3654 continue; 3654 continue;
3655 3655
3656 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); 3656 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3657 3657
3658 if (epctrl & DXEPCTL_EPENA) { 3658 if (epctrl & DXEPCTL_EPENA) {
3659 epctrl |= DXEPCTL_SNAK; 3659 epctrl |= DXEPCTL_SNAK;
3660 epctrl |= DXEPCTL_EPDIS; 3660 epctrl |= DXEPCTL_EPDIS;
3661 dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx)); 3661 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3662 } 3662 }
3663 } 3663 }
3664 3664
@@ -3668,7 +3668,7 @@ irq_retry:
3668 if (gintsts & GINTSTS_GINNAKEFF) { 3668 if (gintsts & GINTSTS_GINNAKEFF) {
3669 dev_info(hsotg->dev, "GINNakEff triggered\n"); 3669 dev_info(hsotg->dev, "GINNakEff triggered\n");
3670 3670
3671 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK); 3671 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3672 3672
3673 dwc2_hsotg_dump(hsotg); 3673 dwc2_hsotg_dump(hsotg);
3674 } 3674 }
@@ -3708,7 +3708,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3708 3708
3709 if (hs_ep->dir_in) { 3709 if (hs_ep->dir_in) {
3710 if (hsotg->dedicated_fifos || hs_ep->periodic) { 3710 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3711 dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); 3711 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3712 /* Wait for Nak effect */ 3712 /* Wait for Nak effect */
3713 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, 3713 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3714 DXEPINT_INEPNAKEFF, 100)) 3714 DXEPINT_INEPNAKEFF, 100))
@@ -3716,7 +3716,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3716 "%s: timeout DIEPINT.NAKEFF\n", 3716 "%s: timeout DIEPINT.NAKEFF\n",
3717 __func__); 3717 __func__);
3718 } else { 3718 } else {
3719 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGNPINNAK); 3719 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3720 /* Wait for Nak effect */ 3720 /* Wait for Nak effect */
3721 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, 3721 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3722 GINTSTS_GINNAKEFF, 100)) 3722 GINTSTS_GINNAKEFF, 100))
@@ -3725,8 +3725,8 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3725 __func__); 3725 __func__);
3726 } 3726 }
3727 } else { 3727 } else {
3728 if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF)) 3728 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3729 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK); 3729 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3730 3730
3731 /* Wait for global nak to take effect */ 3731 /* Wait for global nak to take effect */
3732 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, 3732 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
@@ -3736,7 +3736,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3736 } 3736 }
3737 3737
3738 /* Disable ep */ 3738 /* Disable ep */
3739 dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); 3739 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3740 3740
3741 /* Wait for ep to be disabled */ 3741 /* Wait for ep to be disabled */
3742 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) 3742 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
@@ -3744,7 +3744,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3744 "%s: timeout DOEPCTL.EPDisable\n", __func__); 3744 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3745 3745
3746 /* Clear EPDISBLD interrupt */ 3746 /* Clear EPDISBLD interrupt */
3747 dwc2_set_bit(hsotg->regs + epint_reg, DXEPINT_EPDISBLD); 3747 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3748 3748
3749 if (hs_ep->dir_in) { 3749 if (hs_ep->dir_in) {
3750 unsigned short fifo_index; 3750 unsigned short fifo_index;
@@ -3759,11 +3759,11 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3759 3759
3760 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ 3760 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3761 if (!hsotg->dedicated_fifos && !hs_ep->periodic) 3761 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3762 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK); 3762 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3763 3763
3764 } else { 3764 } else {
3765 /* Remove global NAKs */ 3765 /* Remove global NAKs */
3766 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGOUTNAK); 3766 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3767 } 3767 }
3768} 3768}
3769 3769
@@ -3831,7 +3831,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3831 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ 3831 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3832 3832
3833 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); 3833 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3834 epctrl = dwc2_readl(hsotg->regs + epctrl_reg); 3834 epctrl = dwc2_readl(hsotg, epctrl_reg);
3835 3835
3836 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", 3836 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3837 __func__, epctrl, epctrl_reg); 3837 __func__, epctrl, epctrl_reg);
@@ -3879,13 +3879,13 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3879 hs_ep->compl_desc = 0; 3879 hs_ep->compl_desc = 0;
3880 if (dir_in) { 3880 if (dir_in) {
3881 hs_ep->periodic = 1; 3881 hs_ep->periodic = 1;
3882 mask = dwc2_readl(hsotg->regs + DIEPMSK); 3882 mask = dwc2_readl(hsotg, DIEPMSK);
3883 mask |= DIEPMSK_NAKMSK; 3883 mask |= DIEPMSK_NAKMSK;
3884 dwc2_writel(mask, hsotg->regs + DIEPMSK); 3884 dwc2_writel(hsotg, mask, DIEPMSK);
3885 } else { 3885 } else {
3886 mask = dwc2_readl(hsotg->regs + DOEPMSK); 3886 mask = dwc2_readl(hsotg, DOEPMSK);
3887 mask |= DOEPMSK_OUTTKNEPDISMSK; 3887 mask |= DOEPMSK_OUTTKNEPDISMSK;
3888 dwc2_writel(mask, hsotg->regs + DOEPMSK); 3888 dwc2_writel(hsotg, mask, DOEPMSK);
3889 } 3889 }
3890 break; 3890 break;
3891 3891
@@ -3920,7 +3920,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3920 for (i = 1; i < hsotg->num_of_eps; ++i) { 3920 for (i = 1; i < hsotg->num_of_eps; ++i) {
3921 if (hsotg->fifo_map & (1 << i)) 3921 if (hsotg->fifo_map & (1 << i))
3922 continue; 3922 continue;
3923 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); 3923 val = dwc2_readl(hsotg, DPTXFSIZN(i));
3924 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; 3924 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
3925 if (val < size) 3925 if (val < size)
3926 continue; 3926 continue;
@@ -3958,7 +3958,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3958 * to 4.00a (including both). Also for FS_IOT_1.00a 3958 * to 4.00a (including both). Also for FS_IOT_1.00a
3959 * and HS_IOT_1.00a. 3959 * and HS_IOT_1.00a.
3960 */ 3960 */
3961 u32 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID); 3961 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
3962 3962
3963 if ((gsnpsid >= DWC2_CORE_REV_2_72a && 3963 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
3964 gsnpsid <= DWC2_CORE_REV_4_00a) || 3964 gsnpsid <= DWC2_CORE_REV_4_00a) ||
@@ -3970,9 +3970,9 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3970 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", 3970 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
3971 __func__, epctrl); 3971 __func__, epctrl);
3972 3972
3973 dwc2_writel(epctrl, hsotg->regs + epctrl_reg); 3973 dwc2_writel(hsotg, epctrl, epctrl_reg);
3974 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", 3974 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
3975 __func__, dwc2_readl(hsotg->regs + epctrl_reg)); 3975 __func__, dwc2_readl(hsotg, epctrl_reg));
3976 3976
3977 /* enable the endpoint interrupt */ 3977 /* enable the endpoint interrupt */
3978 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); 3978 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
@@ -4021,7 +4021,7 @@ static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4021 4021
4022 spin_lock_irqsave(&hsotg->lock, flags); 4022 spin_lock_irqsave(&hsotg->lock, flags);
4023 4023
4024 ctrl = dwc2_readl(hsotg->regs + epctrl_reg); 4024 ctrl = dwc2_readl(hsotg, epctrl_reg);
4025 4025
4026 if (ctrl & DXEPCTL_EPENA) 4026 if (ctrl & DXEPCTL_EPENA)
4027 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); 4027 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
@@ -4031,7 +4031,7 @@ static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4031 ctrl |= DXEPCTL_SNAK; 4031 ctrl |= DXEPCTL_SNAK;
4032 4032
4033 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); 4033 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4034 dwc2_writel(ctrl, hsotg->regs + epctrl_reg); 4034 dwc2_writel(hsotg, ctrl, epctrl_reg);
4035 4035
4036 /* disable endpoint interrupts */ 4036 /* disable endpoint interrupts */
4037 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); 4037 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
@@ -4138,7 +4138,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4138 4138
4139 if (hs_ep->dir_in) { 4139 if (hs_ep->dir_in) {
4140 epreg = DIEPCTL(index); 4140 epreg = DIEPCTL(index);
4141 epctl = dwc2_readl(hs->regs + epreg); 4141 epctl = dwc2_readl(hs, epreg);
4142 4142
4143 if (value) { 4143 if (value) {
4144 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; 4144 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
@@ -4151,10 +4151,10 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4151 xfertype == DXEPCTL_EPTYPE_INTERRUPT) 4151 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4152 epctl |= DXEPCTL_SETD0PID; 4152 epctl |= DXEPCTL_SETD0PID;
4153 } 4153 }
4154 dwc2_writel(epctl, hs->regs + epreg); 4154 dwc2_writel(hs, epctl, epreg);
4155 } else { 4155 } else {
4156 epreg = DOEPCTL(index); 4156 epreg = DOEPCTL(index);
4157 epctl = dwc2_readl(hs->regs + epreg); 4157 epctl = dwc2_readl(hs, epreg);
4158 4158
4159 if (value) { 4159 if (value) {
4160 epctl |= DXEPCTL_STALL; 4160 epctl |= DXEPCTL_STALL;
@@ -4165,7 +4165,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4165 xfertype == DXEPCTL_EPTYPE_INTERRUPT) 4165 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4166 epctl |= DXEPCTL_SETD0PID; 4166 epctl |= DXEPCTL_SETD0PID;
4167 } 4167 }
4168 dwc2_writel(epctl, hs->regs + epreg); 4168 dwc2_writel(hs, epctl, epreg);
4169 } 4169 }
4170 4170
4171 hs_ep->halted = value; 4171 hs_ep->halted = value;
@@ -4213,29 +4213,29 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4213 u32 usbcfg; 4213 u32 usbcfg;
4214 /* unmask subset of endpoint interrupts */ 4214 /* unmask subset of endpoint interrupts */
4215 4215
4216 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | 4216 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4217 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, 4217 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4218 hsotg->regs + DIEPMSK); 4218 DIEPMSK);
4219 4219
4220 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | 4220 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4221 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, 4221 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4222 hsotg->regs + DOEPMSK); 4222 DOEPMSK);
4223 4223
4224 dwc2_writel(0, hsotg->regs + DAINTMSK); 4224 dwc2_writel(hsotg, 0, DAINTMSK);
4225 4225
4226 /* Be in disconnected state until gadget is registered */ 4226 /* Be in disconnected state until gadget is registered */
4227 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); 4227 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4228 4228
4229 /* setup fifos */ 4229 /* setup fifos */
4230 4230
4231 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", 4231 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4232 dwc2_readl(hsotg->regs + GRXFSIZ), 4232 dwc2_readl(hsotg, GRXFSIZ),
4233 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 4233 dwc2_readl(hsotg, GNPTXFSIZ));
4234 4234
4235 dwc2_hsotg_init_fifo(hsotg); 4235 dwc2_hsotg_init_fifo(hsotg);
4236 4236
4237 /* keep other bits untouched (so e.g. forced modes are not lost) */ 4237 /* keep other bits untouched (so e.g. forced modes are not lost) */
4238 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 4238 usbcfg = dwc2_readl(hsotg, GUSBCFG);
4239 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | 4239 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
4240 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); 4240 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
4241 4241
@@ -4243,10 +4243,10 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4243 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; 4243 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
4244 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | 4244 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
4245 (trdtim << GUSBCFG_USBTRDTIM_SHIFT); 4245 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
4246 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 4246 dwc2_writel(hsotg, usbcfg, GUSBCFG);
4247 4247
4248 if (using_dma(hsotg)) 4248 if (using_dma(hsotg))
4249 dwc2_set_bit(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); 4249 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4250} 4250}
4251 4251
4252/** 4252/**
@@ -4536,9 +4536,9 @@ static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4536 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); 4536 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4537 4537
4538 if (dir_in) 4538 if (dir_in)
4539 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); 4539 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4540 else 4540 else
4541 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); 4541 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4542 } 4542 }
4543} 4543}
4544 4544
@@ -4607,24 +4607,23 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4607{ 4607{
4608#ifdef DEBUG 4608#ifdef DEBUG
4609 struct device *dev = hsotg->dev; 4609 struct device *dev = hsotg->dev;
4610 void __iomem *regs = hsotg->regs;
4611 u32 val; 4610 u32 val;
4612 int idx; 4611 int idx;
4613 4612
4614 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", 4613 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4615 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), 4614 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4616 dwc2_readl(regs + DIEPMSK)); 4615 dwc2_readl(hsotg, DIEPMSK));
4617 4616
4618 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", 4617 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4619 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); 4618 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4620 4619
4621 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", 4620 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4622 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); 4621 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4623 4622
4624 /* show periodic fifo settings */ 4623 /* show periodic fifo settings */
4625 4624
4626 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 4625 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4627 val = dwc2_readl(regs + DPTXFSIZN(idx)); 4626 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4628 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, 4627 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4629 val >> FIFOSIZE_DEPTH_SHIFT, 4628 val >> FIFOSIZE_DEPTH_SHIFT,
4630 val & FIFOSIZE_STARTADDR_MASK); 4629 val & FIFOSIZE_STARTADDR_MASK);
@@ -4633,20 +4632,20 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4633 for (idx = 0; idx < hsotg->num_of_eps; idx++) { 4632 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4634 dev_info(dev, 4633 dev_info(dev,
4635 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, 4634 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4636 dwc2_readl(regs + DIEPCTL(idx)), 4635 dwc2_readl(hsotg, DIEPCTL(idx)),
4637 dwc2_readl(regs + DIEPTSIZ(idx)), 4636 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4638 dwc2_readl(regs + DIEPDMA(idx))); 4637 dwc2_readl(hsotg, DIEPDMA(idx)));
4639 4638
4640 val = dwc2_readl(regs + DOEPCTL(idx)); 4639 val = dwc2_readl(hsotg, DOEPCTL(idx));
4641 dev_info(dev, 4640 dev_info(dev,
4642 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", 4641 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4643 idx, dwc2_readl(regs + DOEPCTL(idx)), 4642 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4644 dwc2_readl(regs + DOEPTSIZ(idx)), 4643 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4645 dwc2_readl(regs + DOEPDMA(idx))); 4644 dwc2_readl(hsotg, DOEPDMA(idx)));
4646 } 4645 }
4647 4646
4648 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", 4647 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4649 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); 4648 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4650#endif 4649#endif
4651} 4650}
4652 4651
@@ -4835,15 +4834,15 @@ int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4835 /* Backup dev regs */ 4834 /* Backup dev regs */
4836 dr = &hsotg->dr_backup; 4835 dr = &hsotg->dr_backup;
4837 4836
4838 dr->dcfg = dwc2_readl(hsotg->regs + DCFG); 4837 dr->dcfg = dwc2_readl(hsotg, DCFG);
4839 dr->dctl = dwc2_readl(hsotg->regs + DCTL); 4838 dr->dctl = dwc2_readl(hsotg, DCTL);
4840 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 4839 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
4841 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); 4840 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
4842 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); 4841 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
4843 4842
4844 for (i = 0; i < hsotg->num_of_eps; i++) { 4843 for (i = 0; i < hsotg->num_of_eps; i++) {
4845 /* Backup IN EPs */ 4844 /* Backup IN EPs */
4846 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); 4845 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
4847 4846
4848 /* Ensure DATA PID is correctly configured */ 4847 /* Ensure DATA PID is correctly configured */
4849 if (dr->diepctl[i] & DXEPCTL_DPID) 4848 if (dr->diepctl[i] & DXEPCTL_DPID)
@@ -4851,11 +4850,11 @@ int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4851 else 4850 else
4852 dr->diepctl[i] |= DXEPCTL_SETD0PID; 4851 dr->diepctl[i] |= DXEPCTL_SETD0PID;
4853 4852
4854 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); 4853 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
4855 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); 4854 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
4856 4855
4857 /* Backup OUT EPs */ 4856 /* Backup OUT EPs */
4858 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); 4857 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
4859 4858
4860 /* Ensure DATA PID is correctly configured */ 4859 /* Ensure DATA PID is correctly configured */
4861 if (dr->doepctl[i] & DXEPCTL_DPID) 4860 if (dr->doepctl[i] & DXEPCTL_DPID)
@@ -4863,9 +4862,9 @@ int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4863 else 4862 else
4864 dr->doepctl[i] |= DXEPCTL_SETD0PID; 4863 dr->doepctl[i] |= DXEPCTL_SETD0PID;
4865 4864
4866 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); 4865 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
4867 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); 4866 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
4868 dr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); 4867 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
4869 } 4868 }
4870 dr->valid = true; 4869 dr->valid = true;
4871 return 0; 4870 return 0;
@@ -4898,17 +4897,17 @@ int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
4898 dr->valid = false; 4897 dr->valid = false;
4899 4898
4900 if (!remote_wakeup) 4899 if (!remote_wakeup)
4901 dwc2_writel(dr->dctl, hsotg->regs + DCTL); 4900 dwc2_writel(hsotg, dr->dctl, DCTL);
4902 4901
4903 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); 4902 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
4904 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); 4903 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
4905 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); 4904 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
4906 4905
4907 for (i = 0; i < hsotg->num_of_eps; i++) { 4906 for (i = 0; i < hsotg->num_of_eps; i++) {
4908 /* Restore IN EPs */ 4907 /* Restore IN EPs */
4909 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); 4908 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
4910 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); 4909 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
4911 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); 4910 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
4912 /** WA for enabled EPx's IN in DDMA mode. On entering to 4911 /** WA for enabled EPx's IN in DDMA mode. On entering to
4913 * hibernation wrong value read and saved from DIEPDMAx, 4912 * hibernation wrong value read and saved from DIEPDMAx,
4914 * as result BNA interrupt asserted on hibernation exit 4913 * as result BNA interrupt asserted on hibernation exit
@@ -4917,10 +4916,10 @@ int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
4917 if (hsotg->params.g_dma_desc && 4916 if (hsotg->params.g_dma_desc &&
4918 (dr->diepctl[i] & DXEPCTL_EPENA)) 4917 (dr->diepctl[i] & DXEPCTL_EPENA))
4919 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma; 4918 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
4920 dwc2_writel(dr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i)); 4919 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
4921 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); 4920 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
4922 /* Restore OUT EPs */ 4921 /* Restore OUT EPs */
4923 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); 4922 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
4924 /* WA for enabled EPx's OUT in DDMA mode. On entering to 4923 /* WA for enabled EPx's OUT in DDMA mode. On entering to
4925 * hibernation wrong value read and saved from DOEPDMAx, 4924 * hibernation wrong value read and saved from DOEPDMAx,
4926 * as result BNA interrupt asserted on hibernation exit 4925 * as result BNA interrupt asserted on hibernation exit
@@ -4929,8 +4928,8 @@ int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
4929 if (hsotg->params.g_dma_desc && 4928 if (hsotg->params.g_dma_desc &&
4930 (dr->doepctl[i] & DXEPCTL_EPENA)) 4929 (dr->doepctl[i] & DXEPCTL_EPENA))
4931 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma; 4930 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
4932 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); 4931 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
4933 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); 4932 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
4934 } 4933 }
4935 4934
4936 return 0; 4935 return 0;
@@ -4954,9 +4953,8 @@ void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
4954 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; 4953 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
4955 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; 4954 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
4956 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; 4955 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
4957 dwc2_writel(val, hsotg->regs + GLPMCFG); 4956 dwc2_writel(hsotg, val, GLPMCFG);
4958 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg->regs 4957 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
4959 + GLPMCFG));
4960} 4958}
4961 4959
4962/** 4960/**
@@ -4989,40 +4987,40 @@ int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
4989 4987
4990 gpwrdn = GPWRDN_PWRDNRSTN; 4988 gpwrdn = GPWRDN_PWRDNRSTN;
4991 gpwrdn |= GPWRDN_PMUACTV; 4989 gpwrdn |= GPWRDN_PMUACTV;
4992 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 4990 dwc2_writel(hsotg, gpwrdn, GPWRDN);
4993 udelay(10); 4991 udelay(10);
4994 4992
4995 /* Set flag to indicate that we are in hibernation */ 4993 /* Set flag to indicate that we are in hibernation */
4996 hsotg->hibernated = 1; 4994 hsotg->hibernated = 1;
4997 4995
4998 /* Enable interrupts from wake up logic */ 4996 /* Enable interrupts from wake up logic */
4999 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 4997 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5000 gpwrdn |= GPWRDN_PMUINTSEL; 4998 gpwrdn |= GPWRDN_PMUINTSEL;
5001 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 4999 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5002 udelay(10); 5000 udelay(10);
5003 5001
5004 /* Unmask device mode interrupts in GPWRDN */ 5002 /* Unmask device mode interrupts in GPWRDN */
5005 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5003 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5006 gpwrdn |= GPWRDN_RST_DET_MSK; 5004 gpwrdn |= GPWRDN_RST_DET_MSK;
5007 gpwrdn |= GPWRDN_LNSTSCHG_MSK; 5005 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5008 gpwrdn |= GPWRDN_STS_CHGINT_MSK; 5006 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5009 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5007 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5010 udelay(10); 5008 udelay(10);
5011 5009
5012 /* Enable Power Down Clamp */ 5010 /* Enable Power Down Clamp */
5013 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5011 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5014 gpwrdn |= GPWRDN_PWRDNCLMP; 5012 gpwrdn |= GPWRDN_PWRDNCLMP;
5015 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5013 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5016 udelay(10); 5014 udelay(10);
5017 5015
5018 /* Switch off VDD */ 5016 /* Switch off VDD */
5019 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5017 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5020 gpwrdn |= GPWRDN_PWRDNSWTCH; 5018 gpwrdn |= GPWRDN_PWRDNSWTCH;
5021 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5019 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5022 udelay(10); 5020 udelay(10);
5023 5021
5024 /* Save gpwrdn register for further usage if stschng interrupt */ 5022 /* Save gpwrdn register for further usage if stschng interrupt */
5025 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5023 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5026 dev_dbg(hsotg->dev, "Hibernation completed\n"); 5024 dev_dbg(hsotg->dev, "Hibernation completed\n");
5027 5025
5028 return ret; 5026 return ret;
@@ -5064,46 +5062,46 @@ int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5064 5062
5065 if (!reset) { 5063 if (!reset) {
5066 /* Clear all pending interupts */ 5064 /* Clear all pending interupts */
5067 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 5065 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5068 } 5066 }
5069 5067
5070 /* De-assert Restore */ 5068 /* De-assert Restore */
5071 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5069 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5072 gpwrdn &= ~GPWRDN_RESTORE; 5070 gpwrdn &= ~GPWRDN_RESTORE;
5073 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5071 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5074 udelay(10); 5072 udelay(10);
5075 5073
5076 if (!rem_wakeup) { 5074 if (!rem_wakeup) {
5077 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 5075 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5078 pcgcctl &= ~PCGCTL_RSTPDWNMODULE; 5076 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5079 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 5077 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5080 } 5078 }
5081 5079
5082 /* Restore GUSBCFG, DCFG and DCTL */ 5080 /* Restore GUSBCFG, DCFG and DCTL */
5083 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); 5081 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5084 dwc2_writel(dr->dcfg, hsotg->regs + DCFG); 5082 dwc2_writel(hsotg, dr->dcfg, DCFG);
5085 dwc2_writel(dr->dctl, hsotg->regs + DCTL); 5083 dwc2_writel(hsotg, dr->dctl, DCTL);
5086 5084
5087 /* De-assert Wakeup Logic */ 5085 /* De-assert Wakeup Logic */
5088 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5086 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5089 gpwrdn &= ~GPWRDN_PMUACTV; 5087 gpwrdn &= ~GPWRDN_PMUACTV;
5090 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5088 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5091 5089
5092 if (rem_wakeup) { 5090 if (rem_wakeup) {
5093 udelay(10); 5091 udelay(10);
5094 /* Start Remote Wakeup Signaling */ 5092 /* Start Remote Wakeup Signaling */
5095 dwc2_writel(dr->dctl | DCTL_RMTWKUPSIG, hsotg->regs + DCTL); 5093 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5096 } else { 5094 } else {
5097 udelay(50); 5095 udelay(50);
5098 /* Set Device programming done bit */ 5096 /* Set Device programming done bit */
5099 dctl = dwc2_readl(hsotg->regs + DCTL); 5097 dctl = dwc2_readl(hsotg, DCTL);
5100 dctl |= DCTL_PWRONPRGDONE; 5098 dctl |= DCTL_PWRONPRGDONE;
5101 dwc2_writel(dctl, hsotg->regs + DCTL); 5099 dwc2_writel(hsotg, dctl, DCTL);
5102 } 5100 }
5103 /* Wait for interrupts which must be cleared */ 5101 /* Wait for interrupts which must be cleared */
5104 mdelay(2); 5102 mdelay(2);
5105 /* Clear all pending interupts */ 5103 /* Clear all pending interupts */
5106 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 5104 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5107 5105
5108 /* Restore global registers */ 5106 /* Restore global registers */
5109 ret = dwc2_restore_global_registers(hsotg); 5107 ret = dwc2_restore_global_registers(hsotg);
@@ -5123,9 +5121,9 @@ int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5123 5121
5124 if (rem_wakeup) { 5122 if (rem_wakeup) {
5125 mdelay(10); 5123 mdelay(10);
5126 dctl = dwc2_readl(hsotg->regs + DCTL); 5124 dctl = dwc2_readl(hsotg, DCTL);
5127 dctl &= ~DCTL_RMTWKUPSIG; 5125 dctl &= ~DCTL_RMTWKUPSIG;
5128 dwc2_writel(dctl, hsotg->regs + DCTL); 5126 dwc2_writel(hsotg, dctl, DCTL);
5129 } 5127 }
5130 5128
5131 hsotg->hibernated = 0; 5129 hsotg->hibernated = 0;
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index b1104be3429c..72f4f0fb614d 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -75,10 +75,10 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
75 u32 intmsk; 75 u32 intmsk;
76 76
77 /* Clear any pending OTG Interrupts */ 77 /* Clear any pending OTG Interrupts */
78 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); 78 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
79 79
80 /* Clear any pending interrupts */ 80 /* Clear any pending interrupts */
81 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 81 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
82 82
83 /* Enable the interrupts in the GINTMSK */ 83 /* Enable the interrupts in the GINTMSK */
84 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 84 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
@@ -94,7 +94,7 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
94 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm) 94 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
95 intmsk |= GINTSTS_LPMTRANRCVD; 95 intmsk |= GINTSTS_LPMTRANRCVD;
96 96
97 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 97 dwc2_writel(hsotg, intmsk, GINTMSK);
98} 98}
99 99
100/* 100/*
@@ -117,10 +117,10 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
117 } 117 }
118 118
119 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 119 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
120 hcfg = dwc2_readl(hsotg->regs + HCFG); 120 hcfg = dwc2_readl(hsotg, HCFG);
121 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 121 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
122 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 122 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
123 dwc2_writel(hcfg, hsotg->regs + HCFG); 123 dwc2_writel(hsotg, hcfg, HCFG);
124} 124}
125 125
126static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 126static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
@@ -135,10 +135,10 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
135 if (select_phy) { 135 if (select_phy) {
136 dev_dbg(hsotg->dev, "FS PHY selected\n"); 136 dev_dbg(hsotg->dev, "FS PHY selected\n");
137 137
138 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 138 usbcfg = dwc2_readl(hsotg, GUSBCFG);
139 if (!(usbcfg & GUSBCFG_PHYSEL)) { 139 if (!(usbcfg & GUSBCFG_PHYSEL)) {
140 usbcfg |= GUSBCFG_PHYSEL; 140 usbcfg |= GUSBCFG_PHYSEL;
141 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 141 dwc2_writel(hsotg, usbcfg, GUSBCFG);
142 142
143 /* Reset after a PHY select */ 143 /* Reset after a PHY select */
144 retval = dwc2_core_reset(hsotg, false); 144 retval = dwc2_core_reset(hsotg, false);
@@ -151,7 +151,7 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
151 } 151 }
152 152
153 if (hsotg->params.activate_stm_fs_transceiver) { 153 if (hsotg->params.activate_stm_fs_transceiver) {
154 ggpio = dwc2_readl(hsotg->regs + GGPIO); 154 ggpio = dwc2_readl(hsotg, GGPIO);
155 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) { 155 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
156 dev_dbg(hsotg->dev, "Activating transceiver\n"); 156 dev_dbg(hsotg->dev, "Activating transceiver\n");
157 /* 157 /*
@@ -159,7 +159,7 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
159 * core configuration register. 159 * core configuration register.
160 */ 160 */
161 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN; 161 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
162 dwc2_writel(ggpio, hsotg->regs + GGPIO); 162 dwc2_writel(hsotg, ggpio, GGPIO);
163 } 163 }
164 } 164 }
165 } 165 }
@@ -176,18 +176,18 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
176 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 176 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
177 177
178 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 178 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
179 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 179 usbcfg = dwc2_readl(hsotg, GUSBCFG);
180 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 180 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
181 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 181 dwc2_writel(hsotg, usbcfg, GUSBCFG);
182 182
183 /* Program GI2CCTL.I2CEn */ 183 /* Program GI2CCTL.I2CEn */
184 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); 184 i2cctl = dwc2_readl(hsotg, GI2CCTL);
185 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 185 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
186 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 186 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
187 i2cctl &= ~GI2CCTL_I2CEN; 187 i2cctl &= ~GI2CCTL_I2CEN;
188 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 188 dwc2_writel(hsotg, i2cctl, GI2CCTL);
189 i2cctl |= GI2CCTL_I2CEN; 189 i2cctl |= GI2CCTL_I2CEN;
190 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 190 dwc2_writel(hsotg, i2cctl, GI2CCTL);
191 } 191 }
192 192
193 return retval; 193 return retval;
@@ -201,7 +201,7 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
201 if (!select_phy) 201 if (!select_phy)
202 return 0; 202 return 0;
203 203
204 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 204 usbcfg = dwc2_readl(hsotg, GUSBCFG);
205 usbcfg_old = usbcfg; 205 usbcfg_old = usbcfg;
206 206
207 /* 207 /*
@@ -236,7 +236,7 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
236 } 236 }
237 237
238 if (usbcfg != usbcfg_old) { 238 if (usbcfg != usbcfg_old) {
239 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 239 dwc2_writel(hsotg, usbcfg, GUSBCFG);
240 240
241 /* Reset after setting the PHY parameters */ 241 /* Reset after setting the PHY parameters */
242 retval = dwc2_core_reset(hsotg, false); 242 retval = dwc2_core_reset(hsotg, false);
@@ -273,15 +273,15 @@ static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
273 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 273 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
274 hsotg->params.ulpi_fs_ls) { 274 hsotg->params.ulpi_fs_ls) {
275 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 275 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
276 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 276 usbcfg = dwc2_readl(hsotg, GUSBCFG);
277 usbcfg |= GUSBCFG_ULPI_FS_LS; 277 usbcfg |= GUSBCFG_ULPI_FS_LS;
278 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 278 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
279 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 279 dwc2_writel(hsotg, usbcfg, GUSBCFG);
280 } else { 280 } else {
281 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 281 usbcfg = dwc2_readl(hsotg, GUSBCFG);
282 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 282 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
283 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 283 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
284 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 284 dwc2_writel(hsotg, usbcfg, GUSBCFG);
285 } 285 }
286 286
287 return retval; 287 return retval;
@@ -289,7 +289,7 @@ static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
289 289
290static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 290static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
291{ 291{
292 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 292 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
293 293
294 switch (hsotg->hw_params.arch) { 294 switch (hsotg->hw_params.arch) {
295 case GHWCFG2_EXT_DMA_ARCH: 295 case GHWCFG2_EXT_DMA_ARCH:
@@ -316,7 +316,7 @@ static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
316 else 316 else
317 hsotg->params.dma_desc_enable = false; 317 hsotg->params.dma_desc_enable = false;
318 318
319 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 319 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
320 320
321 return 0; 321 return 0;
322} 322}
@@ -325,7 +325,7 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
325{ 325{
326 u32 usbcfg; 326 u32 usbcfg;
327 327
328 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 328 usbcfg = dwc2_readl(hsotg, GUSBCFG);
329 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 329 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
330 330
331 switch (hsotg->hw_params.op_mode) { 331 switch (hsotg->hw_params.op_mode) {
@@ -353,7 +353,7 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
353 break; 353 break;
354 } 354 }
355 355
356 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 356 dwc2_writel(hsotg, usbcfg, GUSBCFG);
357} 357}
358 358
359static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg) 359static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
@@ -390,16 +390,16 @@ static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
390 dev_dbg(hsotg->dev, "%s()\n", __func__); 390 dev_dbg(hsotg->dev, "%s()\n", __func__);
391 391
392 /* Disable all interrupts */ 392 /* Disable all interrupts */
393 dwc2_writel(0, hsotg->regs + GINTMSK); 393 dwc2_writel(hsotg, 0, GINTMSK);
394 dwc2_writel(0, hsotg->regs + HAINTMSK); 394 dwc2_writel(hsotg, 0, HAINTMSK);
395 395
396 /* Enable the common interrupts */ 396 /* Enable the common interrupts */
397 dwc2_enable_common_interrupts(hsotg); 397 dwc2_enable_common_interrupts(hsotg);
398 398
399 /* Enable host mode interrupts without disturbing common interrupts */ 399 /* Enable host mode interrupts without disturbing common interrupts */
400 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 400 intmsk = dwc2_readl(hsotg, GINTMSK);
401 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 401 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
402 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 402 dwc2_writel(hsotg, intmsk, GINTMSK);
403} 403}
404 404
405/** 405/**
@@ -409,12 +409,12 @@ static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
409 */ 409 */
410static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 410static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
411{ 411{
412 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 412 u32 intmsk = dwc2_readl(hsotg, GINTMSK);
413 413
414 /* Disable host mode interrupts without disturbing common interrupts */ 414 /* Disable host mode interrupts without disturbing common interrupts */
415 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 415 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
416 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); 416 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
417 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 417 dwc2_writel(hsotg, intmsk, GINTMSK);
418} 418}
419 419
420/* 420/*
@@ -494,37 +494,37 @@ static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
494 dwc2_calculate_dynamic_fifo(hsotg); 494 dwc2_calculate_dynamic_fifo(hsotg);
495 495
496 /* Rx FIFO */ 496 /* Rx FIFO */
497 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 497 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
498 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 498 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
499 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 499 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
500 grxfsiz |= params->host_rx_fifo_size << 500 grxfsiz |= params->host_rx_fifo_size <<
501 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 501 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
502 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); 502 dwc2_writel(hsotg, grxfsiz, GRXFSIZ);
503 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", 503 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
504 dwc2_readl(hsotg->regs + GRXFSIZ)); 504 dwc2_readl(hsotg, GRXFSIZ));
505 505
506 /* Non-periodic Tx FIFO */ 506 /* Non-periodic Tx FIFO */
507 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 507 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
508 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 508 dwc2_readl(hsotg, GNPTXFSIZ));
509 nptxfsiz = params->host_nperio_tx_fifo_size << 509 nptxfsiz = params->host_nperio_tx_fifo_size <<
510 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 510 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
511 nptxfsiz |= params->host_rx_fifo_size << 511 nptxfsiz |= params->host_rx_fifo_size <<
512 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 512 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
513 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); 513 dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ);
514 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 514 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
515 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 515 dwc2_readl(hsotg, GNPTXFSIZ));
516 516
517 /* Periodic Tx FIFO */ 517 /* Periodic Tx FIFO */
518 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 518 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
519 dwc2_readl(hsotg->regs + HPTXFSIZ)); 519 dwc2_readl(hsotg, HPTXFSIZ));
520 hptxfsiz = params->host_perio_tx_fifo_size << 520 hptxfsiz = params->host_perio_tx_fifo_size <<
521 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 521 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
522 hptxfsiz |= (params->host_rx_fifo_size + 522 hptxfsiz |= (params->host_rx_fifo_size +
523 params->host_nperio_tx_fifo_size) << 523 params->host_nperio_tx_fifo_size) <<
524 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 524 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
525 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); 525 dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ);
526 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 526 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
527 dwc2_readl(hsotg->regs + HPTXFSIZ)); 527 dwc2_readl(hsotg, HPTXFSIZ));
528 528
529 if (hsotg->params.en_multiple_tx_fifo && 529 if (hsotg->params.en_multiple_tx_fifo &&
530 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) { 530 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
@@ -533,14 +533,14 @@ static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
533 * Global DFIFOCFG calculation for Host mode - 533 * Global DFIFOCFG calculation for Host mode -
534 * include RxFIFO, NPTXFIFO and HPTXFIFO 534 * include RxFIFO, NPTXFIFO and HPTXFIFO
535 */ 535 */
536 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 536 dfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
537 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 537 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
538 dfifocfg |= (params->host_rx_fifo_size + 538 dfifocfg |= (params->host_rx_fifo_size +
539 params->host_nperio_tx_fifo_size + 539 params->host_nperio_tx_fifo_size +
540 params->host_perio_tx_fifo_size) << 540 params->host_perio_tx_fifo_size) <<
541 GDFIFOCFG_EPINFOBASE_SHIFT & 541 GDFIFOCFG_EPINFOBASE_SHIFT &
542 GDFIFOCFG_EPINFOBASE_MASK; 542 GDFIFOCFG_EPINFOBASE_MASK;
543 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); 543 dwc2_writel(hsotg, dfifocfg, GDFIFOCFG);
544 } 544 }
545} 545}
546 546
@@ -560,8 +560,8 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
560 u32 hprt0; 560 u32 hprt0;
561 int clock = 60; /* default value */ 561 int clock = 60; /* default value */
562 562
563 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 563 usbcfg = dwc2_readl(hsotg, GUSBCFG);
564 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 564 hprt0 = dwc2_readl(hsotg, HPRT0);
565 565
566 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 566 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
567 !(usbcfg & GUSBCFG_PHYIF16)) 567 !(usbcfg & GUSBCFG_PHYIF16))
@@ -603,7 +603,6 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
603 */ 603 */
604void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 604void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
605{ 605{
606 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
607 u32 *data_buf = (u32 *)dest; 606 u32 *data_buf = (u32 *)dest;
608 int word_count = (bytes + 3) / 4; 607 int word_count = (bytes + 3) / 4;
609 int i; 608 int i;
@@ -617,7 +616,7 @@ void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
617 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 616 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
618 617
619 for (i = 0; i < word_count; i++, data_buf++) 618 for (i = 0; i < word_count; i++, data_buf++)
620 *data_buf = dwc2_readl(fifo); 619 *data_buf = dwc2_readl(hsotg, HCFIFO(0));
621} 620}
622 621
623/** 622/**
@@ -646,10 +645,10 @@ static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
646 if (!chan) 645 if (!chan)
647 return; 646 return;
648 647
649 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 648 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
650 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 649 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
651 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); 650 hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num));
652 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); 651 hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num));
653 652
654 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 653 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
655 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 654 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
@@ -797,7 +796,7 @@ static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
797 break; 796 break;
798 } 797 }
799 798
800 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 799 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
801 if (dbg_hc(chan)) 800 if (dbg_hc(chan))
802 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 801 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
803} 802}
@@ -834,7 +833,7 @@ static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
834 } 833 }
835 } 834 }
836 835
837 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 836 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
838 if (dbg_hc(chan)) 837 if (dbg_hc(chan))
839 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 838 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
840} 839}
@@ -855,16 +854,16 @@ static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
855 } 854 }
856 855
857 /* Enable the top level host channel interrupt */ 856 /* Enable the top level host channel interrupt */
858 intmsk = dwc2_readl(hsotg->regs + HAINTMSK); 857 intmsk = dwc2_readl(hsotg, HAINTMSK);
859 intmsk |= 1 << chan->hc_num; 858 intmsk |= 1 << chan->hc_num;
860 dwc2_writel(intmsk, hsotg->regs + HAINTMSK); 859 dwc2_writel(hsotg, intmsk, HAINTMSK);
861 if (dbg_hc(chan)) 860 if (dbg_hc(chan))
862 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 861 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
863 862
864 /* Make sure host channel interrupts are enabled */ 863 /* Make sure host channel interrupts are enabled */
865 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 864 intmsk = dwc2_readl(hsotg, GINTMSK);
866 intmsk |= GINTSTS_HCHINT; 865 intmsk |= GINTSTS_HCHINT;
867 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 866 dwc2_writel(hsotg, intmsk, GINTMSK);
868 if (dbg_hc(chan)) 867 if (dbg_hc(chan))
869 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 868 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
870} 869}
@@ -893,7 +892,7 @@ static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
893 /* Clear old interrupt conditions for this host channel */ 892 /* Clear old interrupt conditions for this host channel */
894 hcintmsk = 0xffffffff; 893 hcintmsk = 0xffffffff;
895 hcintmsk &= ~HCINTMSK_RESERVED14_31; 894 hcintmsk &= ~HCINTMSK_RESERVED14_31;
896 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); 895 dwc2_writel(hsotg, hcintmsk, HCINT(hc_num));
897 896
898 /* Enable channel interrupts required for this transfer */ 897 /* Enable channel interrupts required for this transfer */
899 dwc2_hc_enable_ints(hsotg, chan); 898 dwc2_hc_enable_ints(hsotg, chan);
@@ -910,7 +909,7 @@ static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
910 hcchar |= HCCHAR_LSPDDEV; 909 hcchar |= HCCHAR_LSPDDEV;
911 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 910 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
912 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 911 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
913 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); 912 dwc2_writel(hsotg, hcchar, HCCHAR(hc_num));
914 if (dbg_hc(chan)) { 913 if (dbg_hc(chan)) {
915 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 914 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
916 hc_num, hcchar); 915 hc_num, hcchar);
@@ -964,7 +963,7 @@ static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
964 } 963 }
965 } 964 }
966 965
967 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); 966 dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num));
968} 967}
969 968
970/** 969/**
@@ -1034,14 +1033,14 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1034 u32 hcintmsk = HCINTMSK_CHHLTD; 1033 u32 hcintmsk = HCINTMSK_CHHLTD;
1035 1034
1036 dev_vdbg(hsotg->dev, "dequeue/error\n"); 1035 dev_vdbg(hsotg->dev, "dequeue/error\n");
1037 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 1036 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
1038 1037
1039 /* 1038 /*
1040 * Make sure no other interrupts besides halt are currently 1039 * Make sure no other interrupts besides halt are currently
1041 * pending. Handling another interrupt could cause a crash due 1040 * pending. Handling another interrupt could cause a crash due
1042 * to the QTD and QH state. 1041 * to the QTD and QH state.
1043 */ 1042 */
1044 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1043 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num));
1045 1044
1046 /* 1045 /*
1047 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 1046 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
@@ -1050,7 +1049,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1050 */ 1049 */
1051 chan->halt_status = halt_status; 1050 chan->halt_status = halt_status;
1052 1051
1053 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1052 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1054 if (!(hcchar & HCCHAR_CHENA)) { 1053 if (!(hcchar & HCCHAR_CHENA)) {
1055 /* 1054 /*
1056 * The channel is either already halted or it hasn't 1055 * The channel is either already halted or it hasn't
@@ -1078,7 +1077,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1078 return; 1077 return;
1079 } 1078 }
1080 1079
1081 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1080 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1082 1081
1083 /* No need to set the bit in DDMA for disabling the channel */ 1082 /* No need to set the bit in DDMA for disabling the channel */
1084 /* TODO check it everywhere channel is disabled */ 1083 /* TODO check it everywhere channel is disabled */
@@ -1101,7 +1100,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1101 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1100 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1102 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 1101 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1103 dev_vdbg(hsotg->dev, "control/bulk\n"); 1102 dev_vdbg(hsotg->dev, "control/bulk\n");
1104 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); 1103 nptxsts = dwc2_readl(hsotg, GNPTXSTS);
1105 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 1104 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1106 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1105 dev_vdbg(hsotg->dev, "Disabling channel\n");
1107 hcchar &= ~HCCHAR_CHENA; 1106 hcchar &= ~HCCHAR_CHENA;
@@ -1109,7 +1108,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1109 } else { 1108 } else {
1110 if (dbg_perio()) 1109 if (dbg_perio())
1111 dev_vdbg(hsotg->dev, "isoc/intr\n"); 1110 dev_vdbg(hsotg->dev, "isoc/intr\n");
1112 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); 1111 hptxsts = dwc2_readl(hsotg, HPTXSTS);
1113 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 1112 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1114 hsotg->queuing_high_bandwidth) { 1113 hsotg->queuing_high_bandwidth) {
1115 if (dbg_perio()) 1114 if (dbg_perio())
@@ -1122,7 +1121,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1122 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1121 dev_vdbg(hsotg->dev, "DMA enabled\n");
1123 } 1122 }
1124 1123
1125 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1124 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1126 chan->halt_status = halt_status; 1125 chan->halt_status = halt_status;
1127 1126
1128 if (hcchar & HCCHAR_CHENA) { 1127 if (hcchar & HCCHAR_CHENA) {
@@ -1171,10 +1170,10 @@ void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1171 * Clear channel interrupt enables and any unhandled channel interrupt 1170 * Clear channel interrupt enables and any unhandled channel interrupt
1172 * conditions 1171 * conditions
1173 */ 1172 */
1174 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); 1173 dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num));
1175 hcintmsk = 0xffffffff; 1174 hcintmsk = 0xffffffff;
1176 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1175 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1177 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1176 dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num));
1178} 1177}
1179 1178
1180/** 1179/**
@@ -1228,7 +1227,7 @@ static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1228 !chan->do_split) ? chan->speed : USB_SPEED_HIGH; 1227 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1229 1228
1230 /* See how many bytes are in the periodic FIFO right now */ 1229 /* See how many bytes are in the periodic FIFO right now */
1231 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) & 1230 fifo_space = (dwc2_readl(hsotg, HPTXSTS) &
1232 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT; 1231 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1233 bytes_in_fifo = sizeof(u32) * 1232 bytes_in_fifo = sizeof(u32) *
1234 (hsotg->params.host_perio_tx_fifo_size - 1233 (hsotg->params.host_perio_tx_fifo_size -
@@ -1348,13 +1347,13 @@ static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1348 if (((unsigned long)data_buf & 0x3) == 0) { 1347 if (((unsigned long)data_buf & 0x3) == 0) {
1349 /* xfer_buf is DWORD aligned */ 1348 /* xfer_buf is DWORD aligned */
1350 for (i = 0; i < dword_count; i++, data_buf++) 1349 for (i = 0; i < dword_count; i++, data_buf++)
1351 dwc2_writel(*data_buf, data_fifo); 1350 dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num));
1352 } else { 1351 } else {
1353 /* xfer_buf is not DWORD aligned */ 1352 /* xfer_buf is not DWORD aligned */
1354 for (i = 0; i < dword_count; i++, data_buf++) { 1353 for (i = 0; i < dword_count; i++, data_buf++) {
1355 u32 data = data_buf[0] | data_buf[1] << 8 | 1354 u32 data = data_buf[0] | data_buf[1] << 8 |
1356 data_buf[2] << 16 | data_buf[3] << 24; 1355 data_buf[2] << 16 | data_buf[3] << 24;
1357 dwc2_writel(data, data_fifo); 1356 dwc2_writel(hsotg, data, HCFIFO(chan->hc_num));
1358 } 1357 }
1359 } 1358 }
1360 1359
@@ -1383,12 +1382,12 @@ static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1383 1382
1384 hctsiz = TSIZ_DOPNG; 1383 hctsiz = TSIZ_DOPNG;
1385 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 1384 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1386 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1385 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1387 1386
1388 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1387 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1389 hcchar |= HCCHAR_CHENA; 1388 hcchar |= HCCHAR_CHENA;
1390 hcchar &= ~HCCHAR_CHDIS; 1389 hcchar &= ~HCCHAR_CHDIS;
1391 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1390 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1392} 1391}
1393 1392
1394/** 1393/**
@@ -1548,7 +1547,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1548 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1547 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1549 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1548 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1550 TSIZ_SC_MC_PID_MASK; 1549 TSIZ_SC_MC_PID_MASK;
1551 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1550 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1552 if (dbg_hc(chan)) { 1551 if (dbg_hc(chan)) {
1553 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1552 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1554 hctsiz, chan->hc_num); 1553 hctsiz, chan->hc_num);
@@ -1576,7 +1575,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1576 } else { 1575 } else {
1577 dma_addr = chan->xfer_dma; 1576 dma_addr = chan->xfer_dma;
1578 } 1577 }
1579 dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num)); 1578 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num));
1580 1579
1581 if (dbg_hc(chan)) 1580 if (dbg_hc(chan))
1582 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", 1581 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
@@ -1585,13 +1584,13 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1585 1584
1586 /* Start the split */ 1585 /* Start the split */
1587 if (chan->do_split) { 1586 if (chan->do_split) {
1588 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 1587 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
1589 1588
1590 hcsplt |= HCSPLT_SPLTENA; 1589 hcsplt |= HCSPLT_SPLTENA;
1591 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); 1590 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num));
1592 } 1591 }
1593 1592
1594 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1593 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1595 hcchar &= ~HCCHAR_MULTICNT_MASK; 1594 hcchar &= ~HCCHAR_MULTICNT_MASK;
1596 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; 1595 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1597 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1596 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
@@ -1610,7 +1609,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1610 (hcchar & HCCHAR_MULTICNT_MASK) >> 1609 (hcchar & HCCHAR_MULTICNT_MASK) >>
1611 HCCHAR_MULTICNT_SHIFT); 1610 HCCHAR_MULTICNT_SHIFT);
1612 1611
1613 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1612 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1614 if (dbg_hc(chan)) 1613 if (dbg_hc(chan))
1615 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1614 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1616 chan->hc_num); 1615 chan->hc_num);
@@ -1668,18 +1667,18 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1668 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 1667 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1669 } 1668 }
1670 1669
1671 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1670 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1672 1671
1673 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, 1672 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1674 chan->desc_list_sz, DMA_TO_DEVICE); 1673 chan->desc_list_sz, DMA_TO_DEVICE);
1675 1674
1676 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num)); 1675 dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num));
1677 1676
1678 if (dbg_hc(chan)) 1677 if (dbg_hc(chan))
1679 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", 1678 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1680 &chan->desc_list_addr, chan->hc_num); 1679 &chan->desc_list_addr, chan->hc_num);
1681 1680
1682 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1681 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1683 hcchar &= ~HCCHAR_MULTICNT_MASK; 1682 hcchar &= ~HCCHAR_MULTICNT_MASK;
1684 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1683 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1685 HCCHAR_MULTICNT_MASK; 1684 HCCHAR_MULTICNT_MASK;
@@ -1698,7 +1697,7 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1698 (hcchar & HCCHAR_MULTICNT_MASK) >> 1697 (hcchar & HCCHAR_MULTICNT_MASK) >>
1699 HCCHAR_MULTICNT_SHIFT); 1698 HCCHAR_MULTICNT_SHIFT);
1700 1699
1701 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1700 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1702 if (dbg_hc(chan)) 1701 if (dbg_hc(chan))
1703 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1702 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1704 chan->hc_num); 1703 chan->hc_num);
@@ -1755,7 +1754,7 @@ static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1755 * transfer completes, the extra requests for the channel will 1754 * transfer completes, the extra requests for the channel will
1756 * be flushed. 1755 * be flushed.
1757 */ 1756 */
1758 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1757 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1759 1758
1760 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1759 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1761 hcchar |= HCCHAR_CHENA; 1760 hcchar |= HCCHAR_CHENA;
@@ -1763,7 +1762,7 @@ static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1763 if (dbg_hc(chan)) 1762 if (dbg_hc(chan))
1764 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 1763 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1765 hcchar); 1764 hcchar);
1766 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1765 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1767 chan->requests++; 1766 chan->requests++;
1768 return 1; 1767 return 1;
1769 } 1768 }
@@ -1773,7 +1772,7 @@ static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1773 if (chan->xfer_count < chan->xfer_len) { 1772 if (chan->xfer_count < chan->xfer_len) {
1774 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1773 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1775 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1774 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1776 u32 hcchar = dwc2_readl(hsotg->regs + 1775 u32 hcchar = dwc2_readl(hsotg,
1777 HCCHAR(chan->hc_num)); 1776 HCCHAR(chan->hc_num));
1778 1777
1779 dwc2_hc_set_even_odd_frame(hsotg, chan, 1778 dwc2_hc_set_even_odd_frame(hsotg, chan,
@@ -1887,7 +1886,7 @@ void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1887 */ 1886 */
1888 hprt0 = dwc2_read_hprt0(hsotg); 1887 hprt0 = dwc2_read_hprt0(hsotg);
1889 hprt0 |= HPRT0_RST; 1888 hprt0 |= HPRT0_RST;
1890 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1889 dwc2_writel(hsotg, hprt0, HPRT0);
1891 } 1890 }
1892 1891
1893 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 1892 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
@@ -1908,11 +1907,11 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1908 channel = hsotg->hc_ptr_array[i]; 1907 channel = hsotg->hc_ptr_array[i];
1909 if (!list_empty(&channel->hc_list_entry)) 1908 if (!list_empty(&channel->hc_list_entry))
1910 continue; 1909 continue;
1911 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1910 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1912 if (hcchar & HCCHAR_CHENA) { 1911 if (hcchar & HCCHAR_CHENA) {
1913 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 1912 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1914 hcchar |= HCCHAR_CHDIS; 1913 hcchar |= HCCHAR_CHDIS;
1915 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1914 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1916 } 1915 }
1917 } 1916 }
1918 } 1917 }
@@ -1921,11 +1920,11 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1921 channel = hsotg->hc_ptr_array[i]; 1920 channel = hsotg->hc_ptr_array[i];
1922 if (!list_empty(&channel->hc_list_entry)) 1921 if (!list_empty(&channel->hc_list_entry))
1923 continue; 1922 continue;
1924 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1923 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1925 if (hcchar & HCCHAR_CHENA) { 1924 if (hcchar & HCCHAR_CHENA) {
1926 /* Halt the channel */ 1925 /* Halt the channel */
1927 hcchar |= HCCHAR_CHDIS; 1926 hcchar |= HCCHAR_CHDIS;
1928 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1927 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1929 } 1928 }
1930 1929
1931 dwc2_hc_cleanup(hsotg, channel); 1930 dwc2_hc_cleanup(hsotg, channel);
@@ -1985,11 +1984,11 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1985 * interrupt mask and status bits and disabling subsequent host 1984 * interrupt mask and status bits and disabling subsequent host
1986 * channel interrupts. 1985 * channel interrupts.
1987 */ 1986 */
1988 intr = dwc2_readl(hsotg->regs + GINTMSK); 1987 intr = dwc2_readl(hsotg, GINTMSK);
1989 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 1988 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1990 dwc2_writel(intr, hsotg->regs + GINTMSK); 1989 dwc2_writel(hsotg, intr, GINTMSK);
1991 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 1990 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1992 dwc2_writel(intr, hsotg->regs + GINTSTS); 1991 dwc2_writel(hsotg, intr, GINTSTS);
1993 1992
1994 /* 1993 /*
1995 * Turn off the vbus power only if the core has transitioned to device 1994 * Turn off the vbus power only if the core has transitioned to device
@@ -1999,7 +1998,7 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1999 if (dwc2_is_device_mode(hsotg)) { 1998 if (dwc2_is_device_mode(hsotg)) {
2000 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 1999 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
2001 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 2000 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
2002 dwc2_writel(0, hsotg->regs + HPRT0); 2001 dwc2_writel(hsotg, 0, HPRT0);
2003 } 2002 }
2004 2003
2005 dwc2_disable_host_interrupts(hsotg); 2004 dwc2_disable_host_interrupts(hsotg);
@@ -2027,7 +2026,7 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
2027 * and won't get any future interrupts to handle the connect. 2026 * and won't get any future interrupts to handle the connect.
2028 */ 2027 */
2029 if (!force) { 2028 if (!force) {
2030 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 2029 hprt0 = dwc2_readl(hsotg, HPRT0);
2031 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 2030 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
2032 dwc2_hcd_connect(hsotg); 2031 dwc2_hcd_connect(hsotg);
2033 } 2032 }
@@ -2071,7 +2070,7 @@ void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
2071 2070
2072 /* Turn off the vbus power */ 2071 /* Turn off the vbus power */
2073 dev_dbg(hsotg->dev, "PortPower off\n"); 2072 dev_dbg(hsotg->dev, "PortPower off\n");
2074 dwc2_writel(0, hsotg->regs + HPRT0); 2073 dwc2_writel(hsotg, 0, HPRT0);
2075} 2074}
2076 2075
2077/* Caller must hold driver lock */ 2076/* Caller must hold driver lock */
@@ -2095,7 +2094,7 @@ static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2095 if ((dev_speed == USB_SPEED_LOW) && 2094 if ((dev_speed == USB_SPEED_LOW) &&
2096 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 2095 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2097 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 2096 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2098 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 2097 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
2099 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 2098 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2100 2099
2101 if (prtspd == HPRT0_SPD_FULL_SPEED) 2100 if (prtspd == HPRT0_SPD_FULL_SPEED)
@@ -2114,7 +2113,7 @@ static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2114 return retval; 2113 return retval;
2115 } 2114 }
2116 2115
2117 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 2116 intr_mask = dwc2_readl(hsotg, GINTMSK);
2118 if (!(intr_mask & GINTSTS_SOF)) { 2117 if (!(intr_mask & GINTSTS_SOF)) {
2119 enum dwc2_transaction_type tr_type; 2118 enum dwc2_transaction_type tr_type;
2120 2119
@@ -2279,7 +2278,7 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2279 2278
2280 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2279 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2281 2280
2282 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 2281 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2283 2282
2284 /* Set ULPI External VBUS bit if needed */ 2283 /* Set ULPI External VBUS bit if needed */
2285 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 2284 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
@@ -2291,7 +2290,7 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2291 if (hsotg->params.ts_dline) 2290 if (hsotg->params.ts_dline)
2292 usbcfg |= GUSBCFG_TERMSELDLPULSE; 2291 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2293 2292
2294 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 2293 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2295 2294
2296 /* 2295 /*
2297 * Reset the Controller 2296 * Reset the Controller
@@ -2325,9 +2324,9 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2325 dwc2_gusbcfg_init(hsotg); 2324 dwc2_gusbcfg_init(hsotg);
2326 2325
2327 /* Program the GOTGCTL register */ 2326 /* Program the GOTGCTL register */
2328 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2327 otgctl = dwc2_readl(hsotg, GOTGCTL);
2329 otgctl &= ~GOTGCTL_OTGVER; 2328 otgctl &= ~GOTGCTL_OTGVER;
2330 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2329 dwc2_writel(hsotg, otgctl, GOTGCTL);
2331 2330
2332 /* Clear the SRP success bit for FS-I2c */ 2331 /* Clear the SRP success bit for FS-I2c */
2333 hsotg->srp_success = 0; 2332 hsotg->srp_success = 0;
@@ -2374,20 +2373,20 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2374 * introduced by the PHY in generating the linestate condition 2373 * introduced by the PHY in generating the linestate condition
2375 * can vary from one PHY to another. 2374 * can vary from one PHY to another.
2376 */ 2375 */
2377 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 2376 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2378 usbcfg |= GUSBCFG_TOUTCAL(7); 2377 usbcfg |= GUSBCFG_TOUTCAL(7);
2379 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 2378 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2380 2379
2381 /* Restart the Phy Clock */ 2380 /* Restart the Phy Clock */
2382 dwc2_writel(0, hsotg->regs + PCGCTL); 2381 dwc2_writel(hsotg, 0, PCGCTL);
2383 2382
2384 /* Initialize Host Configuration Register */ 2383 /* Initialize Host Configuration Register */
2385 dwc2_init_fs_ls_pclk_sel(hsotg); 2384 dwc2_init_fs_ls_pclk_sel(hsotg);
2386 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 2385 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2387 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { 2386 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2388 hcfg = dwc2_readl(hsotg->regs + HCFG); 2387 hcfg = dwc2_readl(hsotg, HCFG);
2389 hcfg |= HCFG_FSLSSUPP; 2388 hcfg |= HCFG_FSLSSUPP;
2390 dwc2_writel(hcfg, hsotg->regs + HCFG); 2389 dwc2_writel(hsotg, hcfg, HCFG);
2391 } 2390 }
2392 2391
2393 /* 2392 /*
@@ -2396,9 +2395,9 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2396 * and its value must not be changed during runtime. 2395 * and its value must not be changed during runtime.
2397 */ 2396 */
2398 if (hsotg->params.reload_ctl) { 2397 if (hsotg->params.reload_ctl) {
2399 hfir = dwc2_readl(hsotg->regs + HFIR); 2398 hfir = dwc2_readl(hsotg, HFIR);
2400 hfir |= HFIR_RLDCTRL; 2399 hfir |= HFIR_RLDCTRL;
2401 dwc2_writel(hfir, hsotg->regs + HFIR); 2400 dwc2_writel(hsotg, hfir, HFIR);
2402 } 2401 }
2403 2402
2404 if (hsotg->params.dma_desc_enable) { 2403 if (hsotg->params.dma_desc_enable) {
@@ -2415,9 +2414,9 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2415 "falling back to buffer DMA mode.\n"); 2414 "falling back to buffer DMA mode.\n");
2416 hsotg->params.dma_desc_enable = false; 2415 hsotg->params.dma_desc_enable = false;
2417 } else { 2416 } else {
2418 hcfg = dwc2_readl(hsotg->regs + HCFG); 2417 hcfg = dwc2_readl(hsotg, HCFG);
2419 hcfg |= HCFG_DESCDMA; 2418 hcfg |= HCFG_DESCDMA;
2420 dwc2_writel(hcfg, hsotg->regs + HCFG); 2419 dwc2_writel(hsotg, hcfg, HCFG);
2421 } 2420 }
2422 } 2421 }
2423 2422
@@ -2426,18 +2425,18 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2426 2425
2427 /* TODO - check this */ 2426 /* TODO - check this */
2428 /* Clear Host Set HNP Enable in the OTG Control Register */ 2427 /* Clear Host Set HNP Enable in the OTG Control Register */
2429 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2428 otgctl = dwc2_readl(hsotg, GOTGCTL);
2430 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2429 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2431 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2430 dwc2_writel(hsotg, otgctl, GOTGCTL);
2432 2431
2433 /* Make sure the FIFOs are flushed */ 2432 /* Make sure the FIFOs are flushed */
2434 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 2433 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2435 dwc2_flush_rx_fifo(hsotg); 2434 dwc2_flush_rx_fifo(hsotg);
2436 2435
2437 /* Clear Host Set HNP Enable in the OTG Control Register */ 2436 /* Clear Host Set HNP Enable in the OTG Control Register */
2438 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2437 otgctl = dwc2_readl(hsotg, GOTGCTL);
2439 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2438 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2440 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2439 dwc2_writel(hsotg, otgctl, GOTGCTL);
2441 2440
2442 if (!hsotg->params.dma_desc_enable) { 2441 if (!hsotg->params.dma_desc_enable) {
2443 int num_channels, i; 2442 int num_channels, i;
@@ -2446,19 +2445,19 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2446 /* Flush out any leftover queued requests */ 2445 /* Flush out any leftover queued requests */
2447 num_channels = hsotg->params.host_channels; 2446 num_channels = hsotg->params.host_channels;
2448 for (i = 0; i < num_channels; i++) { 2447 for (i = 0; i < num_channels; i++) {
2449 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2448 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2450 hcchar &= ~HCCHAR_CHENA; 2449 hcchar &= ~HCCHAR_CHENA;
2451 hcchar |= HCCHAR_CHDIS; 2450 hcchar |= HCCHAR_CHDIS;
2452 hcchar &= ~HCCHAR_EPDIR; 2451 hcchar &= ~HCCHAR_EPDIR;
2453 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2452 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2454 } 2453 }
2455 2454
2456 /* Halt all channels to put them into a known state */ 2455 /* Halt all channels to put them into a known state */
2457 for (i = 0; i < num_channels; i++) { 2456 for (i = 0; i < num_channels; i++) {
2458 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2457 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2459 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 2458 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2460 hcchar &= ~HCCHAR_EPDIR; 2459 hcchar &= ~HCCHAR_EPDIR;
2461 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2460 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2462 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 2461 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2463 __func__, i); 2462 __func__, i);
2464 2463
@@ -2482,7 +2481,7 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2482 !!(hprt0 & HPRT0_PWR)); 2481 !!(hprt0 & HPRT0_PWR));
2483 if (!(hprt0 & HPRT0_PWR)) { 2482 if (!(hprt0 & HPRT0_PWR)) {
2484 hprt0 |= HPRT0_PWR; 2483 hprt0 |= HPRT0_PWR;
2485 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2484 dwc2_writel(hsotg, hprt0, HPRT0);
2486 } 2485 }
2487 } 2486 }
2488 2487
@@ -3076,7 +3075,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
3076 if (dbg_perio()) 3075 if (dbg_perio())
3077 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 3076 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
3078 3077
3079 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 3078 tx_status = dwc2_readl(hsotg, HPTXSTS);
3080 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3079 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3081 TXSTS_QSPCAVAIL_SHIFT; 3080 TXSTS_QSPCAVAIL_SHIFT;
3082 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3081 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
@@ -3091,7 +3090,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
3091 3090
3092 qh_ptr = hsotg->periodic_sched_assigned.next; 3091 qh_ptr = hsotg->periodic_sched_assigned.next;
3093 while (qh_ptr != &hsotg->periodic_sched_assigned) { 3092 while (qh_ptr != &hsotg->periodic_sched_assigned) {
3094 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 3093 tx_status = dwc2_readl(hsotg, HPTXSTS);
3095 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3094 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3096 TXSTS_QSPCAVAIL_SHIFT; 3095 TXSTS_QSPCAVAIL_SHIFT;
3097 if (qspcavail == 0) { 3096 if (qspcavail == 0) {
@@ -3161,10 +3160,10 @@ exit:
3161 * level to ensure that new requests are loaded as 3160 * level to ensure that new requests are loaded as
3162 * soon as possible.) 3161 * soon as possible.)
3163 */ 3162 */
3164 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3163 gintmsk = dwc2_readl(hsotg, GINTMSK);
3165 if (!(gintmsk & GINTSTS_PTXFEMP)) { 3164 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3166 gintmsk |= GINTSTS_PTXFEMP; 3165 gintmsk |= GINTSTS_PTXFEMP;
3167 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3166 dwc2_writel(hsotg, gintmsk, GINTMSK);
3168 } 3167 }
3169 } else { 3168 } else {
3170 /* 3169 /*
@@ -3174,10 +3173,10 @@ exit:
3174 * handlers to queue more transactions as transfer 3173 * handlers to queue more transactions as transfer
3175 * states change. 3174 * states change.
3176 */ 3175 */
3177 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3176 gintmsk = dwc2_readl(hsotg, GINTMSK);
3178 if (gintmsk & GINTSTS_PTXFEMP) { 3177 if (gintmsk & GINTSTS_PTXFEMP) {
3179 gintmsk &= ~GINTSTS_PTXFEMP; 3178 gintmsk &= ~GINTSTS_PTXFEMP;
3180 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3179 dwc2_writel(hsotg, gintmsk, GINTMSK);
3181 } 3180 }
3182 } 3181 }
3183} 3182}
@@ -3206,7 +3205,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3206 3205
3207 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 3206 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3208 3207
3209 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3208 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3210 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3209 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3211 TXSTS_QSPCAVAIL_SHIFT; 3210 TXSTS_QSPCAVAIL_SHIFT;
3212 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3211 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
@@ -3229,7 +3228,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3229 * available in the request queue or the Tx FIFO 3228 * available in the request queue or the Tx FIFO
3230 */ 3229 */
3231 do { 3230 do {
3232 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3231 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3233 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3232 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3234 TXSTS_QSPCAVAIL_SHIFT; 3233 TXSTS_QSPCAVAIL_SHIFT;
3235 if (!hsotg->params.host_dma && qspcavail == 0) { 3234 if (!hsotg->params.host_dma && qspcavail == 0) {
@@ -3266,7 +3265,7 @@ next:
3266 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 3265 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3267 3266
3268 if (!hsotg->params.host_dma) { 3267 if (!hsotg->params.host_dma) {
3269 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3268 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3270 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3269 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3271 TXSTS_QSPCAVAIL_SHIFT; 3270 TXSTS_QSPCAVAIL_SHIFT;
3272 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3271 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
@@ -3286,9 +3285,9 @@ next:
3286 * level to ensure that new requests are loaded as 3285 * level to ensure that new requests are loaded as
3287 * soon as possible.) 3286 * soon as possible.)
3288 */ 3287 */
3289 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3288 gintmsk = dwc2_readl(hsotg, GINTMSK);
3290 gintmsk |= GINTSTS_NPTXFEMP; 3289 gintmsk |= GINTSTS_NPTXFEMP;
3291 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3290 dwc2_writel(hsotg, gintmsk, GINTMSK);
3292 } else { 3291 } else {
3293 /* 3292 /*
3294 * Disable the Tx FIFO empty interrupt since there are 3293 * Disable the Tx FIFO empty interrupt since there are
@@ -3297,9 +3296,9 @@ next:
3297 * handlers to queue more transactions as transfer 3296 * handlers to queue more transactions as transfer
3298 * states change. 3297 * states change.
3299 */ 3298 */
3300 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3299 gintmsk = dwc2_readl(hsotg, GINTMSK);
3301 gintmsk &= ~GINTSTS_NPTXFEMP; 3300 gintmsk &= ~GINTSTS_NPTXFEMP;
3302 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3301 dwc2_writel(hsotg, gintmsk, GINTMSK);
3303 } 3302 }
3304 } 3303 }
3305} 3304}
@@ -3336,10 +3335,10 @@ void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3336 * Ensure NP Tx FIFO empty interrupt is disabled when 3335 * Ensure NP Tx FIFO empty interrupt is disabled when
3337 * there are no non-periodic transfers to process 3336 * there are no non-periodic transfers to process
3338 */ 3337 */
3339 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3338 u32 gintmsk = dwc2_readl(hsotg, GINTMSK);
3340 3339
3341 gintmsk &= ~GINTSTS_NPTXFEMP; 3340 gintmsk &= ~GINTSTS_NPTXFEMP;
3342 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3341 dwc2_writel(hsotg, gintmsk, GINTMSK);
3343 } 3342 }
3344 } 3343 }
3345} 3344}
@@ -3354,7 +3353,7 @@ static void dwc2_conn_id_status_change(struct work_struct *work)
3354 3353
3355 dev_dbg(hsotg->dev, "%s()\n", __func__); 3354 dev_dbg(hsotg->dev, "%s()\n", __func__);
3356 3355
3357 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3356 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3358 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 3357 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3359 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 3358 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3360 !!(gotgctl & GOTGCTL_CONID_B)); 3359 !!(gotgctl & GOTGCTL_CONID_B));
@@ -3380,7 +3379,7 @@ static void dwc2_conn_id_status_change(struct work_struct *work)
3380 * check it again and jump to host mode if that was 3379 * check it again and jump to host mode if that was
3381 * the case. 3380 * the case.
3382 */ 3381 */
3383 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3382 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3384 if (!(gotgctl & GOTGCTL_CONID_B)) 3383 if (!(gotgctl & GOTGCTL_CONID_B))
3385 goto host; 3384 goto host;
3386 if (++count > 250) 3385 if (++count > 250)
@@ -3440,9 +3439,9 @@ static void dwc2_wakeup_detected(struct timer_list *t)
3440 hprt0 = dwc2_read_hprt0(hsotg); 3439 hprt0 = dwc2_read_hprt0(hsotg);
3441 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 3440 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3442 hprt0 &= ~HPRT0_RES; 3441 hprt0 &= ~HPRT0_RES;
3443 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3442 dwc2_writel(hsotg, hprt0, HPRT0);
3444 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 3443 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3445 dwc2_readl(hsotg->regs + HPRT0)); 3444 dwc2_readl(hsotg, HPRT0));
3446 3445
3447 dwc2_hcd_rem_wakeup(hsotg); 3446 dwc2_hcd_rem_wakeup(hsotg);
3448 hsotg->bus_suspended = false; 3447 hsotg->bus_suspended = false;
@@ -3471,15 +3470,15 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3471 spin_lock_irqsave(&hsotg->lock, flags); 3470 spin_lock_irqsave(&hsotg->lock, flags);
3472 3471
3473 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 3472 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3474 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3473 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3475 gotgctl |= GOTGCTL_HSTSETHNPEN; 3474 gotgctl |= GOTGCTL_HSTSETHNPEN;
3476 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 3475 dwc2_writel(hsotg, gotgctl, GOTGCTL);
3477 hsotg->op_state = OTG_STATE_A_SUSPEND; 3476 hsotg->op_state = OTG_STATE_A_SUSPEND;
3478 } 3477 }
3479 3478
3480 hprt0 = dwc2_read_hprt0(hsotg); 3479 hprt0 = dwc2_read_hprt0(hsotg);
3481 hprt0 |= HPRT0_SUSP; 3480 hprt0 |= HPRT0_SUSP;
3482 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3481 dwc2_writel(hsotg, hprt0, HPRT0);
3483 3482
3484 hsotg->bus_suspended = true; 3483 hsotg->bus_suspended = true;
3485 3484
@@ -3489,17 +3488,17 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3489 */ 3488 */
3490 if (!hsotg->params.power_down) { 3489 if (!hsotg->params.power_down) {
3491 /* Suspend the Phy Clock */ 3490 /* Suspend the Phy Clock */
3492 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3491 pcgctl = dwc2_readl(hsotg, PCGCTL);
3493 pcgctl |= PCGCTL_STOPPCLK; 3492 pcgctl |= PCGCTL_STOPPCLK;
3494 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3493 dwc2_writel(hsotg, pcgctl, PCGCTL);
3495 udelay(10); 3494 udelay(10);
3496 } 3495 }
3497 3496
3498 /* For HNP the bus must be suspended for at least 200ms */ 3497 /* For HNP the bus must be suspended for at least 200ms */
3499 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 3498 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3500 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3499 pcgctl = dwc2_readl(hsotg, PCGCTL);
3501 pcgctl &= ~PCGCTL_STOPPCLK; 3500 pcgctl &= ~PCGCTL_STOPPCLK;
3502 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3501 dwc2_writel(hsotg, pcgctl, PCGCTL);
3503 3502
3504 spin_unlock_irqrestore(&hsotg->lock, flags); 3503 spin_unlock_irqrestore(&hsotg->lock, flags);
3505 3504
@@ -3523,9 +3522,9 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3523 * after registers restore. 3522 * after registers restore.
3524 */ 3523 */
3525 if (!hsotg->params.power_down) { 3524 if (!hsotg->params.power_down) {
3526 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3525 pcgctl = dwc2_readl(hsotg, PCGCTL);
3527 pcgctl &= ~PCGCTL_STOPPCLK; 3526 pcgctl &= ~PCGCTL_STOPPCLK;
3528 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3527 dwc2_writel(hsotg, pcgctl, PCGCTL);
3529 spin_unlock_irqrestore(&hsotg->lock, flags); 3528 spin_unlock_irqrestore(&hsotg->lock, flags);
3530 msleep(20); 3529 msleep(20);
3531 spin_lock_irqsave(&hsotg->lock, flags); 3530 spin_lock_irqsave(&hsotg->lock, flags);
@@ -3534,7 +3533,7 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3534 hprt0 = dwc2_read_hprt0(hsotg); 3533 hprt0 = dwc2_read_hprt0(hsotg);
3535 hprt0 |= HPRT0_RES; 3534 hprt0 |= HPRT0_RES;
3536 hprt0 &= ~HPRT0_SUSP; 3535 hprt0 &= ~HPRT0_SUSP;
3537 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3536 dwc2_writel(hsotg, hprt0, HPRT0);
3538 spin_unlock_irqrestore(&hsotg->lock, flags); 3537 spin_unlock_irqrestore(&hsotg->lock, flags);
3539 3538
3540 msleep(USB_RESUME_TIMEOUT); 3539 msleep(USB_RESUME_TIMEOUT);
@@ -3542,7 +3541,7 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3542 spin_lock_irqsave(&hsotg->lock, flags); 3541 spin_lock_irqsave(&hsotg->lock, flags);
3543 hprt0 = dwc2_read_hprt0(hsotg); 3542 hprt0 = dwc2_read_hprt0(hsotg);
3544 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 3543 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3545 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3544 dwc2_writel(hsotg, hprt0, HPRT0);
3546 hsotg->bus_suspended = false; 3545 hsotg->bus_suspended = false;
3547 spin_unlock_irqrestore(&hsotg->lock, flags); 3546 spin_unlock_irqrestore(&hsotg->lock, flags);
3548} 3547}
@@ -3586,7 +3585,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3586 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 3585 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3587 hprt0 = dwc2_read_hprt0(hsotg); 3586 hprt0 = dwc2_read_hprt0(hsotg);
3588 hprt0 |= HPRT0_ENA; 3587 hprt0 |= HPRT0_ENA;
3589 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3588 dwc2_writel(hsotg, hprt0, HPRT0);
3590 break; 3589 break;
3591 3590
3592 case USB_PORT_FEAT_SUSPEND: 3591 case USB_PORT_FEAT_SUSPEND:
@@ -3606,7 +3605,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3606 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 3605 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3607 hprt0 = dwc2_read_hprt0(hsotg); 3606 hprt0 = dwc2_read_hprt0(hsotg);
3608 hprt0 &= ~HPRT0_PWR; 3607 hprt0 &= ~HPRT0_PWR;
3609 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3608 dwc2_writel(hsotg, hprt0, HPRT0);
3610 break; 3609 break;
3611 3610
3612 case USB_PORT_FEAT_INDICATOR: 3611 case USB_PORT_FEAT_INDICATOR:
@@ -3727,7 +3726,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3727 break; 3726 break;
3728 } 3727 }
3729 3728
3730 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 3729 hprt0 = dwc2_readl(hsotg, HPRT0);
3731 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 3730 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3732 3731
3733 if (hprt0 & HPRT0_CONNSTS) 3732 if (hprt0 & HPRT0_CONNSTS)
@@ -3768,9 +3767,9 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3768 3767
3769 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 3768 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3770 hsotg->params.dma_desc_enable = true; 3769 hsotg->params.dma_desc_enable = true;
3771 hcfg = dwc2_readl(hsotg->regs + HCFG); 3770 hcfg = dwc2_readl(hsotg, HCFG);
3772 hcfg |= HCFG_DESCDMA; 3771 hcfg |= HCFG_DESCDMA;
3773 dwc2_writel(hcfg, hsotg->regs + HCFG); 3772 dwc2_writel(hsotg, hcfg, HCFG);
3774 hsotg->new_connection = false; 3773 hsotg->new_connection = false;
3775 } 3774 }
3776 } 3775 }
@@ -3817,7 +3816,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3817 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 3816 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3818 hprt0 = dwc2_read_hprt0(hsotg); 3817 hprt0 = dwc2_read_hprt0(hsotg);
3819 hprt0 |= HPRT0_PWR; 3818 hprt0 |= HPRT0_PWR;
3820 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3819 dwc2_writel(hsotg, hprt0, HPRT0);
3821 break; 3820 break;
3822 3821
3823 case USB_PORT_FEAT_RESET: 3822 case USB_PORT_FEAT_RESET:
@@ -3827,11 +3826,11 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3827 hprt0 = dwc2_read_hprt0(hsotg); 3826 hprt0 = dwc2_read_hprt0(hsotg);
3828 dev_dbg(hsotg->dev, 3827 dev_dbg(hsotg->dev,
3829 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 3828 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3830 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3829 pcgctl = dwc2_readl(hsotg, PCGCTL);
3831 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 3830 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3832 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3831 dwc2_writel(hsotg, pcgctl, PCGCTL);
3833 /* ??? Original driver does this */ 3832 /* ??? Original driver does this */
3834 dwc2_writel(0, hsotg->regs + PCGCTL); 3833 dwc2_writel(hsotg, 0, PCGCTL);
3835 3834
3836 hprt0 = dwc2_read_hprt0(hsotg); 3835 hprt0 = dwc2_read_hprt0(hsotg);
3837 /* Clear suspend bit if resetting from suspend state */ 3836 /* Clear suspend bit if resetting from suspend state */
@@ -3846,13 +3845,13 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3846 hprt0 |= HPRT0_PWR | HPRT0_RST; 3845 hprt0 |= HPRT0_PWR | HPRT0_RST;
3847 dev_dbg(hsotg->dev, 3846 dev_dbg(hsotg->dev,
3848 "In host mode, hprt0=%08x\n", hprt0); 3847 "In host mode, hprt0=%08x\n", hprt0);
3849 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3848 dwc2_writel(hsotg, hprt0, HPRT0);
3850 } 3849 }
3851 3850
3852 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 3851 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3853 msleep(50); 3852 msleep(50);
3854 hprt0 &= ~HPRT0_RST; 3853 hprt0 &= ~HPRT0_RST;
3855 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3854 dwc2_writel(hsotg, hprt0, HPRT0);
3856 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 3855 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3857 break; 3856 break;
3858 3857
@@ -3868,7 +3867,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3868 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 3867 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3869 hprt0 &= ~HPRT0_TSTCTL_MASK; 3868 hprt0 &= ~HPRT0_TSTCTL_MASK;
3870 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 3869 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3871 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3870 dwc2_writel(hsotg, hprt0, HPRT0);
3872 break; 3871 break;
3873 3872
3874 default: 3873 default:
@@ -3925,7 +3924,7 @@ static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3925 3924
3926int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 3925int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3927{ 3926{
3928 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3927 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3929 3928
3930#ifdef DWC2_DEBUG_SOF 3929#ifdef DWC2_DEBUG_SOF
3931 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 3930 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
@@ -3936,9 +3935,9 @@ int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3936 3935
3937int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) 3936int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3938{ 3937{
3939 u32 hprt = dwc2_readl(hsotg->regs + HPRT0); 3938 u32 hprt = dwc2_readl(hsotg, HPRT0);
3940 u32 hfir = dwc2_readl(hsotg->regs + HFIR); 3939 u32 hfir = dwc2_readl(hsotg, HFIR);
3941 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3940 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3942 unsigned int us_per_frame; 3941 unsigned int us_per_frame;
3943 unsigned int frame_number; 3942 unsigned int frame_number;
3944 unsigned int remaining; 3943 unsigned int remaining;
@@ -4057,11 +4056,11 @@ void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
4057 if (chan->xfer_started) { 4056 if (chan->xfer_started) {
4058 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 4057 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
4059 4058
4060 hfnum = dwc2_readl(hsotg->regs + HFNUM); 4059 hfnum = dwc2_readl(hsotg, HFNUM);
4061 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 4060 hcchar = dwc2_readl(hsotg, HCCHAR(i));
4062 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); 4061 hctsiz = dwc2_readl(hsotg, HCTSIZ(i));
4063 hcint = dwc2_readl(hsotg->regs + HCINT(i)); 4062 hcint = dwc2_readl(hsotg, HCINT(i));
4064 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); 4063 hcintmsk = dwc2_readl(hsotg, HCINTMSK(i));
4065 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 4064 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
4066 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 4065 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
4067 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 4066 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
@@ -4109,12 +4108,12 @@ void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
4109 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 4108 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
4110 hsotg->periodic_channels); 4109 hsotg->periodic_channels);
4111 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 4110 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
4112 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 4111 np_tx_status = dwc2_readl(hsotg, GNPTXSTS);
4113 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 4112 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
4114 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 4113 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4115 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 4114 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
4116 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 4115 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4117 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 4116 p_tx_status = dwc2_readl(hsotg, HPTXSTS);
4118 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 4117 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
4119 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 4118 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4120 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 4119 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
@@ -4364,7 +4363,7 @@ static void dwc2_hcd_reset_func(struct work_struct *work)
4364 4363
4365 hprt0 = dwc2_read_hprt0(hsotg); 4364 hprt0 = dwc2_read_hprt0(hsotg);
4366 hprt0 &= ~HPRT0_RST; 4365 hprt0 &= ~HPRT0_RST;
4367 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4366 dwc2_writel(hsotg, hprt0, HPRT0);
4368 hsotg->flags.b.port_reset_change = 1; 4367 hsotg->flags.b.port_reset_change = 1;
4369 4368
4370 spin_unlock_irqrestore(&hsotg->lock, flags); 4369 spin_unlock_irqrestore(&hsotg->lock, flags);
@@ -4474,7 +4473,7 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4474 hprt0 = dwc2_read_hprt0(hsotg); 4473 hprt0 = dwc2_read_hprt0(hsotg);
4475 hprt0 |= HPRT0_SUSP; 4474 hprt0 |= HPRT0_SUSP;
4476 hprt0 &= ~HPRT0_PWR; 4475 hprt0 &= ~HPRT0_PWR;
4477 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4476 dwc2_writel(hsotg, hprt0, HPRT0);
4478 dwc2_vbus_supply_exit(hsotg); 4477 dwc2_vbus_supply_exit(hsotg);
4479 } 4478 }
4480 4479
@@ -4565,8 +4564,8 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4565 * Clear Port Enable and Port Status changes. 4564 * Clear Port Enable and Port Status changes.
4566 * Enable Port Power. 4565 * Enable Port Power.
4567 */ 4566 */
4568 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | 4567 dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET |
4569 HPRT0_ENACHG, hsotg->regs + HPRT0); 4568 HPRT0_ENACHG, HPRT0);
4570 /* Wait for controller to detect Port Connect */ 4569 /* Wait for controller to detect Port Connect */
4571 usleep_range(5000, 7000); 4570 usleep_range(5000, 7000);
4572 } 4571 }
@@ -5086,17 +5085,17 @@ static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
5086 hsotg->status_buf = NULL; 5085 hsotg->status_buf = NULL;
5087 } 5086 }
5088 5087
5089 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 5088 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
5090 5089
5091 /* Disable all interrupts */ 5090 /* Disable all interrupts */
5092 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 5091 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
5093 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 5092 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
5094 dwc2_writel(0, hsotg->regs + GINTMSK); 5093 dwc2_writel(hsotg, 0, GINTMSK);
5095 5094
5096 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 5095 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5097 dctl = dwc2_readl(hsotg->regs + DCTL); 5096 dctl = dwc2_readl(hsotg, DCTL);
5098 dctl |= DCTL_SFTDISCON; 5097 dctl |= DCTL_SFTDISCON;
5099 dwc2_writel(dctl, hsotg->regs + DCTL); 5098 dwc2_writel(hsotg, dctl, DCTL);
5100 } 5099 }
5101 5100
5102 if (hsotg->wq_otg) { 5101 if (hsotg->wq_otg) {
@@ -5139,7 +5138,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5139 5138
5140 retval = -ENOMEM; 5139 retval = -ENOMEM;
5141 5140
5142 hcfg = dwc2_readl(hsotg->regs + HCFG); 5141 hcfg = dwc2_readl(hsotg, HCFG);
5143 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 5142 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5144 5143
5145#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5144#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
@@ -5429,14 +5428,14 @@ int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5429 5428
5430 /* Backup Host regs */ 5429 /* Backup Host regs */
5431 hr = &hsotg->hr_backup; 5430 hr = &hsotg->hr_backup;
5432 hr->hcfg = dwc2_readl(hsotg->regs + HCFG); 5431 hr->hcfg = dwc2_readl(hsotg, HCFG);
5433 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); 5432 hr->haintmsk = dwc2_readl(hsotg, HAINTMSK);
5434 for (i = 0; i < hsotg->params.host_channels; ++i) 5433 for (i = 0; i < hsotg->params.host_channels; ++i)
5435 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i)); 5434 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i));
5436 5435
5437 hr->hprt0 = dwc2_read_hprt0(hsotg); 5436 hr->hprt0 = dwc2_read_hprt0(hsotg);
5438 hr->hfir = dwc2_readl(hsotg->regs + HFIR); 5437 hr->hfir = dwc2_readl(hsotg, HFIR);
5439 hr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 5438 hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
5440 hr->valid = true; 5439 hr->valid = true;
5441 5440
5442 return 0; 5441 return 0;
@@ -5465,15 +5464,15 @@ int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5465 } 5464 }
5466 hr->valid = false; 5465 hr->valid = false;
5467 5466
5468 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 5467 dwc2_writel(hsotg, hr->hcfg, HCFG);
5469 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK); 5468 dwc2_writel(hsotg, hr->haintmsk, HAINTMSK);
5470 5469
5471 for (i = 0; i < hsotg->params.host_channels; ++i) 5470 for (i = 0; i < hsotg->params.host_channels; ++i)
5472 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); 5471 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i));
5473 5472
5474 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0); 5473 dwc2_writel(hsotg, hr->hprt0, HPRT0);
5475 dwc2_writel(hr->hfir, hsotg->regs + HFIR); 5474 dwc2_writel(hsotg, hr->hfir, HFIR);
5476 dwc2_writel(hr->hptxfsiz, hsotg->regs + HPTXFSIZ); 5475 dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ);
5477 hsotg->frame_number = 0; 5476 hsotg->frame_number = 0;
5478 5477
5479 return 0; 5478 return 0;
@@ -5508,10 +5507,10 @@ int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5508 } 5507 }
5509 5508
5510 /* Enter USB Suspend Mode */ 5509 /* Enter USB Suspend Mode */
5511 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 5510 hprt0 = dwc2_readl(hsotg, HPRT0);
5512 hprt0 |= HPRT0_SUSP; 5511 hprt0 |= HPRT0_SUSP;
5513 hprt0 &= ~HPRT0_ENA; 5512 hprt0 &= ~HPRT0_ENA;
5514 dwc2_writel(hprt0, hsotg->regs + HPRT0); 5513 dwc2_writel(hsotg, hprt0, HPRT0);
5515 5514
5516 /* Wait for the HPRT0.PrtSusp register field to be set */ 5515 /* Wait for the HPRT0.PrtSusp register field to be set */
5517 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000)) 5516 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000))
@@ -5524,56 +5523,56 @@ int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5524 spin_lock_irqsave(&hsotg->lock, flags); 5523 spin_lock_irqsave(&hsotg->lock, flags);
5525 hsotg->lx_state = DWC2_L2; 5524 hsotg->lx_state = DWC2_L2;
5526 5525
5527 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 5526 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
5528 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) { 5527 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
5529 /* ULPI interface */ 5528 /* ULPI interface */
5530 /* Suspend the Phy Clock */ 5529 /* Suspend the Phy Clock */
5531 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 5530 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5532 pcgcctl |= PCGCTL_STOPPCLK; 5531 pcgcctl |= PCGCTL_STOPPCLK;
5533 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 5532 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5534 udelay(10); 5533 udelay(10);
5535 5534
5536 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5535 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5537 gpwrdn |= GPWRDN_PMUACTV; 5536 gpwrdn |= GPWRDN_PMUACTV;
5538 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5537 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5539 udelay(10); 5538 udelay(10);
5540 } else { 5539 } else {
5541 /* UTMI+ Interface */ 5540 /* UTMI+ Interface */
5542 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5541 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5543 gpwrdn |= GPWRDN_PMUACTV; 5542 gpwrdn |= GPWRDN_PMUACTV;
5544 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5543 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5545 udelay(10); 5544 udelay(10);
5546 5545
5547 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 5546 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5548 pcgcctl |= PCGCTL_STOPPCLK; 5547 pcgcctl |= PCGCTL_STOPPCLK;
5549 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 5548 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5550 udelay(10); 5549 udelay(10);
5551 } 5550 }
5552 5551
5553 /* Enable interrupts from wake up logic */ 5552 /* Enable interrupts from wake up logic */
5554 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5553 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5555 gpwrdn |= GPWRDN_PMUINTSEL; 5554 gpwrdn |= GPWRDN_PMUINTSEL;
5556 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5555 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5557 udelay(10); 5556 udelay(10);
5558 5557
5559 /* Unmask host mode interrupts in GPWRDN */ 5558 /* Unmask host mode interrupts in GPWRDN */
5560 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5559 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5561 gpwrdn |= GPWRDN_DISCONN_DET_MSK; 5560 gpwrdn |= GPWRDN_DISCONN_DET_MSK;
5562 gpwrdn |= GPWRDN_LNSTSCHG_MSK; 5561 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5563 gpwrdn |= GPWRDN_STS_CHGINT_MSK; 5562 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5564 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5563 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5565 udelay(10); 5564 udelay(10);
5566 5565
5567 /* Enable Power Down Clamp */ 5566 /* Enable Power Down Clamp */
5568 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5567 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5569 gpwrdn |= GPWRDN_PWRDNCLMP; 5568 gpwrdn |= GPWRDN_PWRDNCLMP;
5570 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5569 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5571 udelay(10); 5570 udelay(10);
5572 5571
5573 /* Switch off VDD */ 5572 /* Switch off VDD */
5574 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5573 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5575 gpwrdn |= GPWRDN_PWRDNSWTCH; 5574 gpwrdn |= GPWRDN_PWRDNSWTCH;
5576 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5575 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5577 5576
5578 hsotg->hibernated = 1; 5577 hsotg->hibernated = 1;
5579 hsotg->bus_suspended = 1; 5578 hsotg->bus_suspended = 1;
@@ -5621,29 +5620,29 @@ int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5621 mdelay(100); 5620 mdelay(100);
5622 5621
5623 /* Clear all pending interupts */ 5622 /* Clear all pending interupts */
5624 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 5623 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5625 5624
5626 /* De-assert Restore */ 5625 /* De-assert Restore */
5627 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5626 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5628 gpwrdn &= ~GPWRDN_RESTORE; 5627 gpwrdn &= ~GPWRDN_RESTORE;
5629 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5628 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5630 udelay(10); 5629 udelay(10);
5631 5630
5632 /* Restore GUSBCFG, HCFG */ 5631 /* Restore GUSBCFG, HCFG */
5633 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); 5632 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5634 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 5633 dwc2_writel(hsotg, hr->hcfg, HCFG);
5635 5634
5636 /* De-assert Wakeup Logic */ 5635 /* De-assert Wakeup Logic */
5637 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5636 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5638 gpwrdn &= ~GPWRDN_PMUACTV; 5637 gpwrdn &= ~GPWRDN_PMUACTV;
5639 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5638 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5640 udelay(10); 5639 udelay(10);
5641 5640
5642 hprt0 = hr->hprt0; 5641 hprt0 = hr->hprt0;
5643 hprt0 |= HPRT0_PWR; 5642 hprt0 |= HPRT0_PWR;
5644 hprt0 &= ~HPRT0_ENA; 5643 hprt0 &= ~HPRT0_ENA;
5645 hprt0 &= ~HPRT0_SUSP; 5644 hprt0 &= ~HPRT0_SUSP;
5646 dwc2_writel(hprt0, hsotg->regs + HPRT0); 5645 dwc2_writel(hsotg, hprt0, HPRT0);
5647 5646
5648 hprt0 = hr->hprt0; 5647 hprt0 = hr->hprt0;
5649 hprt0 |= HPRT0_PWR; 5648 hprt0 |= HPRT0_PWR;
@@ -5652,32 +5651,32 @@ int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5652 5651
5653 if (reset) { 5652 if (reset) {
5654 hprt0 |= HPRT0_RST; 5653 hprt0 |= HPRT0_RST;
5655 dwc2_writel(hprt0, hsotg->regs + HPRT0); 5654 dwc2_writel(hsotg, hprt0, HPRT0);
5656 5655
5657 /* Wait for Resume time and then program HPRT again */ 5656 /* Wait for Resume time and then program HPRT again */
5658 mdelay(60); 5657 mdelay(60);
5659 hprt0 &= ~HPRT0_RST; 5658 hprt0 &= ~HPRT0_RST;
5660 dwc2_writel(hprt0, hsotg->regs + HPRT0); 5659 dwc2_writel(hsotg, hprt0, HPRT0);
5661 } else { 5660 } else {
5662 hprt0 |= HPRT0_RES; 5661 hprt0 |= HPRT0_RES;
5663 dwc2_writel(hprt0, hsotg->regs + HPRT0); 5662 dwc2_writel(hsotg, hprt0, HPRT0);
5664 5663
5665 /* Wait for Resume time and then program HPRT again */ 5664 /* Wait for Resume time and then program HPRT again */
5666 mdelay(100); 5665 mdelay(100);
5667 hprt0 &= ~HPRT0_RES; 5666 hprt0 &= ~HPRT0_RES;
5668 dwc2_writel(hprt0, hsotg->regs + HPRT0); 5667 dwc2_writel(hsotg, hprt0, HPRT0);
5669 } 5668 }
5670 /* Clear all interrupt status */ 5669 /* Clear all interrupt status */
5671 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 5670 hprt0 = dwc2_readl(hsotg, HPRT0);
5672 hprt0 |= HPRT0_CONNDET; 5671 hprt0 |= HPRT0_CONNDET;
5673 hprt0 |= HPRT0_ENACHG; 5672 hprt0 |= HPRT0_ENACHG;
5674 hprt0 &= ~HPRT0_ENA; 5673 hprt0 &= ~HPRT0_ENA;
5675 dwc2_writel(hprt0, hsotg->regs + HPRT0); 5674 dwc2_writel(hsotg, hprt0, HPRT0);
5676 5675
5677 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 5676 hprt0 = dwc2_readl(hsotg, HPRT0);
5678 5677
5679 /* Clear all pending interupts */ 5678 /* Clear all pending interupts */
5680 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 5679 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5681 5680
5682 /* Restore global registers */ 5681 /* Restore global registers */
5683 ret = dwc2_restore_global_registers(hsotg); 5682 ret = dwc2_restore_global_registers(hsotg);
diff --git a/drivers/usb/dwc2/hcd.h b/drivers/usb/dwc2/hcd.h
index 5502a501f516..3f9bccc95add 100644
--- a/drivers/usb/dwc2/hcd.h
+++ b/drivers/usb/dwc2/hcd.h
@@ -469,10 +469,10 @@ static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg)
469 */ 469 */
470static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 470static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
471{ 471{
472 u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); 472 u32 mask = dwc2_readl(hsotg, HCINTMSK(chnum));
473 473
474 mask &= ~intr; 474 mask &= ~intr;
475 dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum)); 475 dwc2_writel(hsotg, mask, HCINTMSK(chnum));
476} 476}
477 477
478void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 478void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
@@ -487,7 +487,7 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
487 */ 487 */
488static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 488static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
489{ 489{
490 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 490 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
491 491
492 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 492 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
493 return hprt0; 493 return hprt0;
@@ -690,8 +690,8 @@ static inline u16 dwc2_micro_frame_num(u16 frame)
690 */ 690 */
691static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 691static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
692{ 692{
693 return dwc2_readl(hsotg->regs + GINTSTS) & 693 return dwc2_readl(hsotg, GINTSTS) &
694 dwc2_readl(hsotg->regs + GINTMSK); 694 dwc2_readl(hsotg, GINTMSK);
695} 695}
696 696
697static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 697static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
diff --git a/drivers/usb/dwc2/hcd_ddma.c b/drivers/usb/dwc2/hcd_ddma.c
index 74f11c823f79..a858b5f9c1d6 100644
--- a/drivers/usb/dwc2/hcd_ddma.c
+++ b/drivers/usb/dwc2/hcd_ddma.c
@@ -185,19 +185,19 @@ static void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en)
185 185
186 spin_lock_irqsave(&hsotg->lock, flags); 186 spin_lock_irqsave(&hsotg->lock, flags);
187 187
188 hcfg = dwc2_readl(hsotg->regs + HCFG); 188 hcfg = dwc2_readl(hsotg, HCFG);
189 if (hcfg & HCFG_PERSCHEDENA) { 189 if (hcfg & HCFG_PERSCHEDENA) {
190 /* already enabled */ 190 /* already enabled */
191 spin_unlock_irqrestore(&hsotg->lock, flags); 191 spin_unlock_irqrestore(&hsotg->lock, flags);
192 return; 192 return;
193 } 193 }
194 194
195 dwc2_writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR); 195 dwc2_writel(hsotg, hsotg->frame_list_dma, HFLBADDR);
196 196
197 hcfg &= ~HCFG_FRLISTEN_MASK; 197 hcfg &= ~HCFG_FRLISTEN_MASK;
198 hcfg |= fr_list_en | HCFG_PERSCHEDENA; 198 hcfg |= fr_list_en | HCFG_PERSCHEDENA;
199 dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n"); 199 dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n");
200 dwc2_writel(hcfg, hsotg->regs + HCFG); 200 dwc2_writel(hsotg, hcfg, HCFG);
201 201
202 spin_unlock_irqrestore(&hsotg->lock, flags); 202 spin_unlock_irqrestore(&hsotg->lock, flags);
203} 203}
@@ -209,7 +209,7 @@ static void dwc2_per_sched_disable(struct dwc2_hsotg *hsotg)
209 209
210 spin_lock_irqsave(&hsotg->lock, flags); 210 spin_lock_irqsave(&hsotg->lock, flags);
211 211
212 hcfg = dwc2_readl(hsotg->regs + HCFG); 212 hcfg = dwc2_readl(hsotg, HCFG);
213 if (!(hcfg & HCFG_PERSCHEDENA)) { 213 if (!(hcfg & HCFG_PERSCHEDENA)) {
214 /* already disabled */ 214 /* already disabled */
215 spin_unlock_irqrestore(&hsotg->lock, flags); 215 spin_unlock_irqrestore(&hsotg->lock, flags);
@@ -218,7 +218,7 @@ static void dwc2_per_sched_disable(struct dwc2_hsotg *hsotg)
218 218
219 hcfg &= ~HCFG_PERSCHEDENA; 219 hcfg &= ~HCFG_PERSCHEDENA;
220 dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n"); 220 dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n");
221 dwc2_writel(hcfg, hsotg->regs + HCFG); 221 dwc2_writel(hsotg, hcfg, HCFG);
222 222
223 spin_unlock_irqrestore(&hsotg->lock, flags); 223 spin_unlock_irqrestore(&hsotg->lock, flags);
224} 224}
diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index ed7f05cf4906..c98ae3653086 100644
--- a/drivers/usb/dwc2/hcd_intr.c
+++ b/drivers/usb/dwc2/hcd_intr.c
@@ -144,7 +144,7 @@ static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
144 enum dwc2_transaction_type tr_type; 144 enum dwc2_transaction_type tr_type;
145 145
146 /* Clear interrupt */ 146 /* Clear interrupt */
147 dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS); 147 dwc2_writel(hsotg, GINTSTS_SOF, GINTSTS);
148 148
149#ifdef DEBUG_SOF 149#ifdef DEBUG_SOF
150 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n"); 150 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
@@ -191,7 +191,7 @@ static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
191 if (dbg_perio()) 191 if (dbg_perio())
192 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n"); 192 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
193 193
194 grxsts = dwc2_readl(hsotg->regs + GRXSTSP); 194 grxsts = dwc2_readl(hsotg, GRXSTSP);
195 chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT; 195 chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
196 chan = hsotg->hc_ptr_array[chnum]; 196 chan = hsotg->hc_ptr_array[chnum];
197 if (!chan) { 197 if (!chan) {
@@ -274,11 +274,11 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
274 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 274 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
275 275
276 /* Every time when port enables calculate HFIR.FrInterval */ 276 /* Every time when port enables calculate HFIR.FrInterval */
277 hfir = dwc2_readl(hsotg->regs + HFIR); 277 hfir = dwc2_readl(hsotg, HFIR);
278 hfir &= ~HFIR_FRINT_MASK; 278 hfir &= ~HFIR_FRINT_MASK;
279 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT & 279 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
280 HFIR_FRINT_MASK; 280 HFIR_FRINT_MASK;
281 dwc2_writel(hfir, hsotg->regs + HFIR); 281 dwc2_writel(hsotg, hfir, HFIR);
282 282
283 /* Check if we need to adjust the PHY clock speed for low power */ 283 /* Check if we need to adjust the PHY clock speed for low power */
284 if (!params->host_support_fs_ls_low_power) { 284 if (!params->host_support_fs_ls_low_power) {
@@ -287,7 +287,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
287 return; 287 return;
288 } 288 }
289 289
290 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 290 usbcfg = dwc2_readl(hsotg, GUSBCFG);
291 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 291 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
292 292
293 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) { 293 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
@@ -295,11 +295,11 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
295 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) { 295 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
296 /* Set PHY low power clock select for FS/LS devices */ 296 /* Set PHY low power clock select for FS/LS devices */
297 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL; 297 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
298 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 298 dwc2_writel(hsotg, usbcfg, GUSBCFG);
299 do_reset = 1; 299 do_reset = 1;
300 } 300 }
301 301
302 hcfg = dwc2_readl(hsotg->regs + HCFG); 302 hcfg = dwc2_readl(hsotg, HCFG);
303 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >> 303 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
304 HCFG_FSLSPCLKSEL_SHIFT; 304 HCFG_FSLSPCLKSEL_SHIFT;
305 305
@@ -312,7 +312,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
312 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ; 312 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
313 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 313 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
314 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; 314 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
315 dwc2_writel(hcfg, hsotg->regs + HCFG); 315 dwc2_writel(hsotg, hcfg, HCFG);
316 do_reset = 1; 316 do_reset = 1;
317 } 317 }
318 } else { 318 } else {
@@ -323,7 +323,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
323 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ; 323 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
324 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 324 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
325 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; 325 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
326 dwc2_writel(hcfg, hsotg->regs + HCFG); 326 dwc2_writel(hsotg, hcfg, HCFG);
327 do_reset = 1; 327 do_reset = 1;
328 } 328 }
329 } 329 }
@@ -331,14 +331,14 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
331 /* Not low power */ 331 /* Not low power */
332 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) { 332 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
333 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL; 333 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
334 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 334 dwc2_writel(hsotg, usbcfg, GUSBCFG);
335 do_reset = 1; 335 do_reset = 1;
336 } 336 }
337 } 337 }
338 338
339 if (do_reset) { 339 if (do_reset) {
340 *hprt0_modify |= HPRT0_RST; 340 *hprt0_modify |= HPRT0_RST;
341 dwc2_writel(*hprt0_modify, hsotg->regs + HPRT0); 341 dwc2_writel(hsotg, *hprt0_modify, HPRT0);
342 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work, 342 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
343 msecs_to_jiffies(60)); 343 msecs_to_jiffies(60));
344 } else { 344 } else {
@@ -359,7 +359,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
359 359
360 dev_vdbg(hsotg->dev, "--Port Interrupt--\n"); 360 dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
361 361
362 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 362 hprt0 = dwc2_readl(hsotg, HPRT0);
363 hprt0_modify = hprt0; 363 hprt0_modify = hprt0;
364 364
365 /* 365 /*
@@ -374,7 +374,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
374 * Set flag and clear if detected 374 * Set flag and clear if detected
375 */ 375 */
376 if (hprt0 & HPRT0_CONNDET) { 376 if (hprt0 & HPRT0_CONNDET) {
377 dwc2_writel(hprt0_modify | HPRT0_CONNDET, hsotg->regs + HPRT0); 377 dwc2_writel(hsotg, hprt0_modify | HPRT0_CONNDET, HPRT0);
378 378
379 dev_vdbg(hsotg->dev, 379 dev_vdbg(hsotg->dev,
380 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n", 380 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
@@ -392,7 +392,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
392 * Clear if detected - Set internal flag if disabled 392 * Clear if detected - Set internal flag if disabled
393 */ 393 */
394 if (hprt0 & HPRT0_ENACHG) { 394 if (hprt0 & HPRT0_ENACHG) {
395 dwc2_writel(hprt0_modify | HPRT0_ENACHG, hsotg->regs + HPRT0); 395 dwc2_writel(hsotg, hprt0_modify | HPRT0_ENACHG, HPRT0);
396 dev_vdbg(hsotg->dev, 396 dev_vdbg(hsotg->dev,
397 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n", 397 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
398 hprt0, !!(hprt0 & HPRT0_ENA)); 398 hprt0, !!(hprt0 & HPRT0_ENA));
@@ -406,17 +406,17 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
406 406
407 hsotg->params.dma_desc_enable = false; 407 hsotg->params.dma_desc_enable = false;
408 hsotg->new_connection = false; 408 hsotg->new_connection = false;
409 hcfg = dwc2_readl(hsotg->regs + HCFG); 409 hcfg = dwc2_readl(hsotg, HCFG);
410 hcfg &= ~HCFG_DESCDMA; 410 hcfg &= ~HCFG_DESCDMA;
411 dwc2_writel(hcfg, hsotg->regs + HCFG); 411 dwc2_writel(hsotg, hcfg, HCFG);
412 } 412 }
413 } 413 }
414 } 414 }
415 415
416 /* Overcurrent Change Interrupt */ 416 /* Overcurrent Change Interrupt */
417 if (hprt0 & HPRT0_OVRCURRCHG) { 417 if (hprt0 & HPRT0_OVRCURRCHG) {
418 dwc2_writel(hprt0_modify | HPRT0_OVRCURRCHG, 418 dwc2_writel(hsotg, hprt0_modify | HPRT0_OVRCURRCHG,
419 hsotg->regs + HPRT0); 419 HPRT0);
420 dev_vdbg(hsotg->dev, 420 dev_vdbg(hsotg->dev,
421 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n", 421 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
422 hprt0); 422 hprt0);
@@ -441,7 +441,7 @@ static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
441{ 441{
442 u32 hctsiz, count, length; 442 u32 hctsiz, count, length;
443 443
444 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 444 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
445 445
446 if (halt_status == DWC2_HC_XFER_COMPLETE) { 446 if (halt_status == DWC2_HC_XFER_COMPLETE) {
447 if (chan->ep_is_in) { 447 if (chan->ep_is_in) {
@@ -518,7 +518,7 @@ static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
518 urb->status = 0; 518 urb->status = 0;
519 } 519 }
520 520
521 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 521 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
522 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", 522 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
523 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); 523 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
524 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len); 524 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
@@ -541,7 +541,7 @@ void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
541 struct dwc2_host_chan *chan, int chnum, 541 struct dwc2_host_chan *chan, int chnum,
542 struct dwc2_qtd *qtd) 542 struct dwc2_qtd *qtd)
543{ 543{
544 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 544 u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
545 u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; 545 u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
546 546
547 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) { 547 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
@@ -780,9 +780,9 @@ cleanup:
780 } 780 }
781 } 781 }
782 782
783 haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); 783 haintmsk = dwc2_readl(hsotg, HAINTMSK);
784 haintmsk &= ~(1 << chan->hc_num); 784 haintmsk &= ~(1 << chan->hc_num);
785 dwc2_writel(haintmsk, hsotg->regs + HAINTMSK); 785 dwc2_writel(hsotg, haintmsk, HAINTMSK);
786 786
787 /* Try to queue more transfers now that there's a free channel */ 787 /* Try to queue more transfers now that there's a free channel */
788 tr_type = dwc2_hcd_select_transactions(hsotg); 788 tr_type = dwc2_hcd_select_transactions(hsotg);
@@ -829,9 +829,9 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
829 * is enabled so that the non-periodic schedule will 829 * is enabled so that the non-periodic schedule will
830 * be processed 830 * be processed
831 */ 831 */
832 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 832 gintmsk = dwc2_readl(hsotg, GINTMSK);
833 gintmsk |= GINTSTS_NPTXFEMP; 833 gintmsk |= GINTSTS_NPTXFEMP;
834 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 834 dwc2_writel(hsotg, gintmsk, GINTMSK);
835 } else { 835 } else {
836 dev_vdbg(hsotg->dev, "isoc/intr\n"); 836 dev_vdbg(hsotg->dev, "isoc/intr\n");
837 /* 837 /*
@@ -848,9 +848,9 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
848 * enabled so that the periodic schedule will be 848 * enabled so that the periodic schedule will be
849 * processed 849 * processed
850 */ 850 */
851 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 851 gintmsk = dwc2_readl(hsotg, GINTMSK);
852 gintmsk |= GINTSTS_PTXFEMP; 852 gintmsk |= GINTSTS_PTXFEMP;
853 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 853 dwc2_writel(hsotg, gintmsk, GINTMSK);
854 } 854 }
855 } 855 }
856} 856}
@@ -915,7 +915,7 @@ static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
915 struct dwc2_qtd *qtd, 915 struct dwc2_qtd *qtd,
916 enum dwc2_halt_status halt_status) 916 enum dwc2_halt_status halt_status)
917{ 917{
918 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 918 u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
919 919
920 qtd->error_count = 0; 920 qtd->error_count = 0;
921 921
@@ -959,7 +959,7 @@ static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
959 959
960 qtd->isoc_split_offset += len; 960 qtd->isoc_split_offset += len;
961 961
962 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 962 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
963 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; 963 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
964 964
965 if (frame_desc->actual_length >= frame_desc->length || pid == 0) { 965 if (frame_desc->actual_length >= frame_desc->length || pid == 0) {
@@ -1185,7 +1185,7 @@ static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1185 1185
1186 urb->actual_length += xfer_length; 1186 urb->actual_length += xfer_length;
1187 1187
1188 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 1188 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1189 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", 1189 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1190 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); 1190 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1191 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n", 1191 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
@@ -1561,10 +1561,10 @@ static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1561 1561
1562 dwc2_hc_handle_tt_clear(hsotg, chan, qtd); 1562 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1563 1563
1564 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); 1564 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1565 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); 1565 hcsplt = dwc2_readl(hsotg, HCSPLT(chnum));
1566 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 1566 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1567 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum)); 1567 hc_dma = dwc2_readl(hsotg, HCDMA(chnum));
1568 1568
1569 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum); 1569 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1570 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt); 1570 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
@@ -1776,10 +1776,10 @@ static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1776 * This code is here only as a check. This condition should 1776 * This code is here only as a check. This condition should
1777 * never happen. Ignore the halt if it does occur. 1777 * never happen. Ignore the halt if it does occur.
1778 */ 1778 */
1779 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); 1779 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1780 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); 1780 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1781 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); 1781 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
1782 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); 1782 hcsplt = dwc2_readl(hsotg, HCSPLT(chnum));
1783 dev_dbg(hsotg->dev, 1783 dev_dbg(hsotg->dev,
1784 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n", 1784 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1785 __func__); 1785 __func__);
@@ -1803,7 +1803,7 @@ static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1803 * when the halt interrupt occurs. Halt the channel again if it does 1803 * when the halt interrupt occurs. Halt the channel again if it does
1804 * occur. 1804 * occur.
1805 */ 1805 */
1806 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); 1806 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1807 if (hcchar & HCCHAR_CHDIS) { 1807 if (hcchar & HCCHAR_CHDIS) {
1808 dev_warn(hsotg->dev, 1808 dev_warn(hsotg->dev,
1809 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n", 1809 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
@@ -1863,7 +1863,7 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1863 return; 1863 return;
1864 } 1864 }
1865 1865
1866 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); 1866 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
1867 1867
1868 if (chan->hcint & HCINTMSK_XFERCOMPL) { 1868 if (chan->hcint & HCINTMSK_XFERCOMPL) {
1869 /* 1869 /*
@@ -1958,7 +1958,7 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1958 dev_err(hsotg->dev, 1958 dev_err(hsotg->dev,
1959 "hcint 0x%08x, intsts 0x%08x\n", 1959 "hcint 0x%08x, intsts 0x%08x\n",
1960 chan->hcint, 1960 chan->hcint,
1961 dwc2_readl(hsotg->regs + GINTSTS)); 1961 dwc2_readl(hsotg, GINTSTS));
1962 goto error; 1962 goto error;
1963 } 1963 }
1964 } 1964 }
@@ -2031,11 +2031,11 @@ static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
2031 2031
2032 chan = hsotg->hc_ptr_array[chnum]; 2032 chan = hsotg->hc_ptr_array[chnum];
2033 2033
2034 hcint = dwc2_readl(hsotg->regs + HCINT(chnum)); 2034 hcint = dwc2_readl(hsotg, HCINT(chnum));
2035 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); 2035 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
2036 if (!chan) { 2036 if (!chan) {
2037 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n"); 2037 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
2038 dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); 2038 dwc2_writel(hsotg, hcint, HCINT(chnum));
2039 return; 2039 return;
2040 } 2040 }
2041 2041
@@ -2047,7 +2047,7 @@ static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
2047 hcint, hcintmsk, hcint & hcintmsk); 2047 hcint, hcintmsk, hcint & hcintmsk);
2048 } 2048 }
2049 2049
2050 dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); 2050 dwc2_writel(hsotg, hcint, HCINT(chnum));
2051 2051
2052 /* 2052 /*
2053 * If we got an interrupt after someone called 2053 * If we got an interrupt after someone called
@@ -2182,7 +2182,7 @@ static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2182 int i; 2182 int i;
2183 struct dwc2_host_chan *chan, *chan_tmp; 2183 struct dwc2_host_chan *chan, *chan_tmp;
2184 2184
2185 haint = dwc2_readl(hsotg->regs + HAINT); 2185 haint = dwc2_readl(hsotg, HAINT);
2186 if (dbg_perio()) { 2186 if (dbg_perio()) {
2187 dev_vdbg(hsotg->dev, "%s()\n", __func__); 2187 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2188 2188
@@ -2266,8 +2266,8 @@ irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2266 "DWC OTG HCD Finished Servicing Interrupts\n"); 2266 "DWC OTG HCD Finished Servicing Interrupts\n");
2267 dev_vdbg(hsotg->dev, 2267 dev_vdbg(hsotg->dev,
2268 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n", 2268 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2269 dwc2_readl(hsotg->regs + GINTSTS), 2269 dwc2_readl(hsotg, GINTSTS),
2270 dwc2_readl(hsotg->regs + GINTMSK)); 2270 dwc2_readl(hsotg, GINTMSK));
2271 } 2271 }
2272 } 2272 }
2273 2273
diff --git a/drivers/usb/dwc2/hcd_queue.c b/drivers/usb/dwc2/hcd_queue.c
index 301ced1618f8..40839591d2ec 100644
--- a/drivers/usb/dwc2/hcd_queue.c
+++ b/drivers/usb/dwc2/hcd_queue.c
@@ -1510,7 +1510,7 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1510 bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info); 1510 bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info);
1511 bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC); 1511 bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC);
1512 bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT); 1512 bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT);
1513 u32 hprt = dwc2_readl(hsotg->regs + HPRT0); 1513 u32 hprt = dwc2_readl(hsotg, HPRT0);
1514 u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1514 u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1515 bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED && 1515 bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED &&
1516 dev_speed != USB_SPEED_HIGH); 1516 dev_speed != USB_SPEED_HIGH);
@@ -1747,9 +1747,9 @@ int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1747 if (status) 1747 if (status)
1748 return status; 1748 return status;
1749 if (!hsotg->periodic_qh_count) { 1749 if (!hsotg->periodic_qh_count) {
1750 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 1750 intr_mask = dwc2_readl(hsotg, GINTMSK);
1751 intr_mask |= GINTSTS_SOF; 1751 intr_mask |= GINTSTS_SOF;
1752 dwc2_writel(intr_mask, hsotg->regs + GINTMSK); 1752 dwc2_writel(hsotg, intr_mask, GINTMSK);
1753 } 1753 }
1754 hsotg->periodic_qh_count++; 1754 hsotg->periodic_qh_count++;
1755 1755
@@ -1788,9 +1788,9 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1788 hsotg->periodic_qh_count--; 1788 hsotg->periodic_qh_count--;
1789 if (!hsotg->periodic_qh_count && 1789 if (!hsotg->periodic_qh_count &&
1790 !hsotg->params.dma_desc_enable) { 1790 !hsotg->params.dma_desc_enable) {
1791 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 1791 intr_mask = dwc2_readl(hsotg, GINTMSK);
1792 intr_mask &= ~GINTSTS_SOF; 1792 intr_mask &= ~GINTSTS_SOF;
1793 dwc2_writel(intr_mask, hsotg->regs + GINTMSK); 1793 dwc2_writel(hsotg, intr_mask, GINTMSK);
1794 } 1794 }
1795} 1795}
1796 1796
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index af075d4da895..f66d0dd5db1c 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -654,8 +654,8 @@ static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
654 654
655 dwc2_force_mode(hsotg, true); 655 dwc2_force_mode(hsotg, true);
656 656
657 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 657 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
658 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 658 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
659 659
660 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 660 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
661 FIFOSIZE_DEPTH_SHIFT; 661 FIFOSIZE_DEPTH_SHIFT;
@@ -679,13 +679,13 @@ static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
679 679
680 dwc2_force_mode(hsotg, false); 680 dwc2_force_mode(hsotg, false);
681 681
682 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 682 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
683 683
684 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 684 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
685 685
686 for (fifo = 1; fifo <= fifo_count; fifo++) { 686 for (fifo = 1; fifo <= fifo_count; fifo++) {
687 hw->g_tx_fifo_size[fifo] = 687 hw->g_tx_fifo_size[fifo] =
688 (dwc2_readl(hsotg->regs + DPTXFSIZN(fifo)) & 688 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
689 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 689 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
690 } 690 }
691 691
@@ -713,7 +713,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
713 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx 713 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
714 */ 714 */
715 715
716 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); 716 hw->snpsid = dwc2_readl(hsotg, GSNPSID);
717 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID && 717 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
718 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID && 718 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
719 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) { 719 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
@@ -726,11 +726,11 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
726 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 726 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
727 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 727 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
728 728
729 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); 729 hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
730 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 730 hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
731 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); 731 hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
732 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 732 hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
733 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 733 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
734 734
735 /* hwcfg1 */ 735 /* hwcfg1 */
736 hw->dev_ep_dirs = hwcfg1; 736 hw->dev_ep_dirs = hwcfg1;
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 07:28:41 -0400