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authorTony Lindgren <tony@atomide.com>2016-10-20 09:42:19 -0400
committerTony Lindgren <tony@atomide.com>2016-11-10 14:42:49 -0500
commite9f5f1e456084fc3a2611b3a40ef8b036b2961cb (patch)
treecf281671b277f4b004dd3f40d7e7434f4bc53b1a
parentb42814557fd5a9cc943dbe326b99dd104af23195 (diff)
ARM: OMAP2+: Remove legacy mux code
All the boards booting with device tree use drivers/pinctrl-single.c instead. Note that mach-omap1 is still using the legacy mux, so let's move the related Kconfig options from plat-omap to mach-omap1. Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat
-rw-r--r--arch/arm/mach-omap1/Kconfig26
-rw-r--r--arch/arm/mach-omap2/Makefile5
-rw-r--r--arch/arm/mach-omap2/common.h9
-rw-r--r--arch/arm/mach-omap2/dss-common.c1
-rw-r--r--arch/arm/mach-omap2/hsmmc.c88
-rw-r--r--arch/arm/mach-omap2/io.c1
-rw-r--r--arch/arm/mach-omap2/msdi.c1
-rw-r--r--arch/arm/mach-omap2/mux.c1153
-rw-r--r--arch/arm/mach-omap2/mux.h352
-rw-r--r--arch/arm/mach-omap2/mux34xx.c2061
-rw-r--r--arch/arm/mach-omap2/mux34xx.h402
-rw-r--r--arch/arm/plat-omap/Kconfig26
12 files changed, 27 insertions, 4098 deletions
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index afb809509140..45c6b733c881 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -31,6 +31,32 @@ config ARCH_OMAP16XX
31 select ARCH_OMAP_OTG 31 select ARCH_OMAP_OTG
32 select CPU_ARM926T 32 select CPU_ARM926T
33 33
34config OMAP_MUX
35 bool "OMAP multiplexing support"
36 depends on ARCH_OMAP
37 default y
38 help
39 Pin multiplexing support for OMAP boards. If your bootloader
40 sets the multiplexing correctly, say N. Otherwise, or if unsure,
41 say Y.
42
43config OMAP_MUX_DEBUG
44 bool "Multiplexing debug output"
45 depends on OMAP_MUX
46 help
47 Makes the multiplexing functions print out a lot of debug info.
48 This is useful if you want to find out the correct values of the
49 multiplexing registers.
50
51config OMAP_MUX_WARNINGS
52 bool "Warn about pins the bootloader didn't set up"
53 depends on OMAP_MUX
54 default y
55 help
56 Choose Y here to warn whenever driver initialization logic needs
57 to change the pin multiplexing setup. When there are no warnings
58 printed, it's safe to deselect OMAP_MUX for your product.
59
34comment "OMAP Board Type" 60comment "OMAP Board Type"
35 depends on ARCH_OMAP1 61 depends on ARCH_OMAP1
36 62
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 231b1e5cbf8c..aedfca455de3 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -6,7 +6,7 @@ ccflags-y := -I$(srctree)/$(src)/include \
6 -I$(srctree)/arch/arm/plat-omap/include 6 -I$(srctree)/arch/arm/plat-omap/include
7 7
8# Common support 8# Common support
9obj-y := id.o io.o control.o mux.o devices.o fb.o timer.o pm.o \ 9obj-y := id.o io.o control.o devices.o fb.o timer.o pm.o \
10 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ 10 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
11 omap_device.o omap-headsmp.o sram.o drm.o 11 omap_device.o omap-headsmp.o sram.o drm.o
12 12
@@ -63,9 +63,6 @@ obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
63obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o 63obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
64obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o 64obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
65 65
66# Pin multiplexing
67obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
68
69# SMS/SDRC 66# SMS/SDRC
70obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o 67obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
71# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o 68# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index deed42e1dd9c..4aec2723ece7 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -77,15 +77,6 @@ static inline int omap4_pm_init_early(void)
77} 77}
78#endif 78#endif
79 79
80#ifdef CONFIG_OMAP_MUX
81int omap_mux_late_init(void);
82#else
83static inline int omap_mux_late_init(void)
84{
85 return 0;
86}
87#endif
88
89extern void omap2_init_common_infrastructure(void); 80extern void omap2_init_common_infrastructure(void);
90 81
91extern void omap_init_time(void); 82extern void omap_init_time(void);
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
index 1d583bc0b1a9..77b618b0a76b 100644
--- a/arch/arm/mach-omap2/dss-common.c
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -32,6 +32,5 @@
32 32
33#include "soc.h" 33#include "soc.h"
34#include "dss-common.h" 34#include "dss-common.h"
35#include "mux.h"
36#include "display.h" 35#include "display.h"
37 36
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 478097741bce..cb754c46747e 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -22,7 +22,6 @@
22#include "omap_device.h" 22#include "omap_device.h"
23#include "omap-pm.h" 23#include "omap-pm.h"
24 24
25#include "mux.h"
26#include "hsmmc.h" 25#include "hsmmc.h"
27#include "control.h" 26#include "control.h"
28 27
@@ -147,91 +146,6 @@ static int nop_mmc_set_power(struct device *dev, int power_on, int vdd)
147 return 0; 146 return 0;
148} 147}
149 148
150static inline void omap_hsmmc_mux(struct omap_hsmmc_platform_data
151 *mmc_controller, int controller_nr)
152{
153 if (gpio_is_valid(mmc_controller->gpio_cd) &&
154 (mmc_controller->gpio_cd < OMAP_MAX_GPIO_LINES))
155 omap_mux_init_gpio(mmc_controller->gpio_cd,
156 OMAP_PIN_INPUT_PULLUP);
157 if (gpio_is_valid(mmc_controller->gpio_cod) &&
158 (mmc_controller->gpio_cod < OMAP_MAX_GPIO_LINES))
159 omap_mux_init_gpio(mmc_controller->gpio_cod,
160 OMAP_PIN_INPUT_PULLUP);
161 if (gpio_is_valid(mmc_controller->gpio_wp) &&
162 (mmc_controller->gpio_wp < OMAP_MAX_GPIO_LINES))
163 omap_mux_init_gpio(mmc_controller->gpio_wp,
164 OMAP_PIN_INPUT_PULLUP);
165 if (cpu_is_omap34xx()) {
166 if (controller_nr == 0) {
167 omap_mux_init_signal("sdmmc1_clk",
168 OMAP_PIN_INPUT_PULLUP);
169 omap_mux_init_signal("sdmmc1_cmd",
170 OMAP_PIN_INPUT_PULLUP);
171 omap_mux_init_signal("sdmmc1_dat0",
172 OMAP_PIN_INPUT_PULLUP);
173 if (mmc_controller->caps &
174 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
175 omap_mux_init_signal("sdmmc1_dat1",
176 OMAP_PIN_INPUT_PULLUP);
177 omap_mux_init_signal("sdmmc1_dat2",
178 OMAP_PIN_INPUT_PULLUP);
179 omap_mux_init_signal("sdmmc1_dat3",
180 OMAP_PIN_INPUT_PULLUP);
181 }
182 if (mmc_controller->caps &
183 MMC_CAP_8_BIT_DATA) {
184 omap_mux_init_signal("sdmmc1_dat4",
185 OMAP_PIN_INPUT_PULLUP);
186 omap_mux_init_signal("sdmmc1_dat5",
187 OMAP_PIN_INPUT_PULLUP);
188 omap_mux_init_signal("sdmmc1_dat6",
189 OMAP_PIN_INPUT_PULLUP);
190 omap_mux_init_signal("sdmmc1_dat7",
191 OMAP_PIN_INPUT_PULLUP);
192 }
193 }
194 if (controller_nr == 1) {
195 /* MMC2 */
196 omap_mux_init_signal("sdmmc2_clk",
197 OMAP_PIN_INPUT_PULLUP);
198 omap_mux_init_signal("sdmmc2_cmd",
199 OMAP_PIN_INPUT_PULLUP);
200 omap_mux_init_signal("sdmmc2_dat0",
201 OMAP_PIN_INPUT_PULLUP);
202
203 /*
204 * For 8 wire configurations, Lines DAT4, 5, 6 and 7
205 * need to be muxed in the board-*.c files
206 */
207 if (mmc_controller->caps &
208 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
209 omap_mux_init_signal("sdmmc2_dat1",
210 OMAP_PIN_INPUT_PULLUP);
211 omap_mux_init_signal("sdmmc2_dat2",
212 OMAP_PIN_INPUT_PULLUP);
213 omap_mux_init_signal("sdmmc2_dat3",
214 OMAP_PIN_INPUT_PULLUP);
215 }
216 if (mmc_controller->caps &
217 MMC_CAP_8_BIT_DATA) {
218 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
219 OMAP_PIN_INPUT_PULLUP);
220 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
221 OMAP_PIN_INPUT_PULLUP);
222 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
223 OMAP_PIN_INPUT_PULLUP);
224 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
225 OMAP_PIN_INPUT_PULLUP);
226 }
227 }
228
229 /*
230 * For MMC3 the pins need to be muxed in the board-*.c files
231 */
232 }
233}
234
235static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, 149static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
236 struct omap_hsmmc_platform_data *mmc) 150 struct omap_hsmmc_platform_data *mmc)
237{ 151{
@@ -410,8 +324,6 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
410 if (res < 0) 324 if (res < 0)
411 goto free_mmc; 325 goto free_mmc;
412 326
413 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
414
415 name = "omap_hsmmc"; 327 name = "omap_hsmmc";
416 res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN, 328 res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
417 "mmc%d", ctrl_nr); 329 "mmc%d", ctrl_nr);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 0e9acdd95d70..b7a467651427 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -427,7 +427,6 @@ static void __init omap_hwmod_init_postsetup(void)
427 427
428static void __init __maybe_unused omap_common_late_init(void) 428static void __init __maybe_unused omap_common_late_init(void)
429{ 429{
430 omap_mux_late_init();
431 omap2_common_pm_late_init(); 430 omap2_common_pm_late_init();
432 omap_soc_device_init(); 431 omap_soc_device_init();
433} 432}
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index 8bdf182422bd..5a3bc3de58d0 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -30,7 +30,6 @@
30#include "control.h" 30#include "control.h"
31#include "omap_hwmod.h" 31#include "omap_hwmod.h"
32#include "omap_device.h" 32#include "omap_device.h"
33#include "mux.h"
34#include "mmc.h" 33#include "mmc.h"
35 34
36/* 35/*
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
deleted file mode 100644
index e1fa39e1ecf8..000000000000
--- a/arch/arm/mach-omap2/mux.c
+++ /dev/null
@@ -1,1153 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/mux.c
3 *
4 * OMAP2, OMAP3 and OMAP4 pin multiplexing configurations
5 *
6 * Copyright (C) 2004 - 2010 Texas Instruments Inc.
7 * Copyright (C) 2003 - 2008 Nokia Corporation
8 *
9 * Written by Tony Lindgren
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 */
26#include <linux/kernel.h>
27#include <linux/init.h>
28#include <linux/io.h>
29#include <linux/list.h>
30#include <linux/slab.h>
31#include <linux/ctype.h>
32#include <linux/debugfs.h>
33#include <linux/seq_file.h>
34#include <linux/uaccess.h>
35#include <linux/irq.h>
36#include <linux/interrupt.h>
37
38
39#include "omap_hwmod.h"
40
41#include "soc.h"
42#include "control.h"
43#include "mux.h"
44#include "prm.h"
45#include "common.h"
46
47#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
48#define OMAP_MUX_BASE_SZ 0x5ca
49
50struct omap_mux_entry {
51 struct omap_mux mux;
52 struct list_head node;
53};
54
55static LIST_HEAD(mux_partitions);
56static DEFINE_MUTEX(muxmode_mutex);
57
58struct omap_mux_partition *omap_mux_get(const char *name)
59{
60 struct omap_mux_partition *partition;
61
62 list_for_each_entry(partition, &mux_partitions, node) {
63 if (!strcmp(name, partition->name))
64 return partition;
65 }
66
67 return NULL;
68}
69
70u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
71{
72 if (partition->flags & OMAP_MUX_REG_8BIT)
73 return readb_relaxed(partition->base + reg);
74 else
75 return readw_relaxed(partition->base + reg);
76}
77
78void omap_mux_write(struct omap_mux_partition *partition, u16 val,
79 u16 reg)
80{
81 if (partition->flags & OMAP_MUX_REG_8BIT)
82 writeb_relaxed(val, partition->base + reg);
83 else
84 writew_relaxed(val, partition->base + reg);
85}
86
87void omap_mux_write_array(struct omap_mux_partition *partition,
88 struct omap_board_mux *board_mux)
89{
90 if (!board_mux)
91 return;
92
93 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
94 omap_mux_write(partition, board_mux->value,
95 board_mux->reg_offset);
96 board_mux++;
97 }
98}
99
100#ifdef CONFIG_OMAP_MUX
101
102static char *omap_mux_options;
103
104static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
105 int gpio, int val)
106{
107 struct omap_mux_entry *e;
108 struct omap_mux *gpio_mux = NULL;
109 u16 old_mode;
110 u16 mux_mode;
111 int found = 0;
112 struct list_head *muxmodes = &partition->muxmodes;
113
114 if (!gpio)
115 return -EINVAL;
116
117 list_for_each_entry(e, muxmodes, node) {
118 struct omap_mux *m = &e->mux;
119 if (gpio == m->gpio) {
120 gpio_mux = m;
121 found++;
122 }
123 }
124
125 if (found == 0) {
126 pr_err("%s: Could not set gpio%i\n", __func__, gpio);
127 return -ENODEV;
128 }
129
130 if (found > 1) {
131 pr_info("%s: Multiple gpio paths (%d) for gpio%i\n", __func__,
132 found, gpio);
133 return -EINVAL;
134 }
135
136 old_mode = omap_mux_read(partition, gpio_mux->reg_offset);
137 mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
138 mux_mode |= partition->gpio;
139 pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__,
140 gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
141 omap_mux_write(partition, mux_mode, gpio_mux->reg_offset);
142
143 return 0;
144}
145
146int __init omap_mux_init_gpio(int gpio, int val)
147{
148 struct omap_mux_partition *partition;
149 int ret;
150
151 list_for_each_entry(partition, &mux_partitions, node) {
152 ret = _omap_mux_init_gpio(partition, gpio, val);
153 if (!ret)
154 return ret;
155 }
156
157 return -ENODEV;
158}
159
160static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
161 const char *muxname,
162 struct omap_mux **found_mux)
163{
164 struct omap_mux *mux = NULL;
165 struct omap_mux_entry *e;
166 const char *mode_name;
167 int found = 0, found_mode = 0, mode0_len = 0;
168 struct list_head *muxmodes = &partition->muxmodes;
169
170 mode_name = strchr(muxname, '.');
171 if (mode_name) {
172 mode0_len = strlen(muxname) - strlen(mode_name);
173 mode_name++;
174 } else {
175 mode_name = muxname;
176 }
177
178 list_for_each_entry(e, muxmodes, node) {
179 char *m0_entry;
180 int i;
181
182 mux = &e->mux;
183 m0_entry = mux->muxnames[0];
184
185 /* First check for full name in mode0.muxmode format */
186 if (mode0_len)
187 if (strncmp(muxname, m0_entry, mode0_len) ||
188 (strlen(m0_entry) != mode0_len))
189 continue;
190
191 /* Then check for muxmode only */
192 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
193 char *mode_cur = mux->muxnames[i];
194
195 if (!mode_cur)
196 continue;
197
198 if (!strcmp(mode_name, mode_cur)) {
199 *found_mux = mux;
200 found++;
201 found_mode = i;
202 }
203 }
204 }
205
206 if (found == 1) {
207 return found_mode;
208 }
209
210 if (found > 1) {
211 pr_err("%s: Multiple signal paths (%i) for %s\n", __func__,
212 found, muxname);
213 return -EINVAL;
214 }
215
216 return -ENODEV;
217}
218
219int __init omap_mux_get_by_name(const char *muxname,
220 struct omap_mux_partition **found_partition,
221 struct omap_mux **found_mux)
222{
223 struct omap_mux_partition *partition;
224
225 list_for_each_entry(partition, &mux_partitions, node) {
226 struct omap_mux *mux = NULL;
227 int mux_mode = _omap_mux_get_by_name(partition, muxname, &mux);
228 if (mux_mode < 0)
229 continue;
230
231 *found_partition = partition;
232 *found_mux = mux;
233
234 return mux_mode;
235 }
236
237 pr_err("%s: Could not find signal %s\n", __func__, muxname);
238
239 return -ENODEV;
240}
241
242int __init omap_mux_init_signal(const char *muxname, int val)
243{
244 struct omap_mux_partition *partition = NULL;
245 struct omap_mux *mux = NULL;
246 u16 old_mode;
247 int mux_mode;
248
249 mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
250 if (mux_mode < 0 || !mux)
251 return mux_mode;
252
253 old_mode = omap_mux_read(partition, mux->reg_offset);
254 mux_mode |= val;
255 pr_debug("%s: Setting signal %s 0x%04x -> 0x%04x\n",
256 __func__, muxname, old_mode, mux_mode);
257 omap_mux_write(partition, mux_mode, mux->reg_offset);
258
259 return 0;
260}
261
262struct omap_hwmod_mux_info * __init
263omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
264{
265 struct omap_hwmod_mux_info *hmux;
266 int i, nr_pads_dynamic = 0;
267
268 if (!bpads || nr_pads < 1)
269 return NULL;
270
271 hmux = kzalloc(sizeof(struct omap_hwmod_mux_info), GFP_KERNEL);
272 if (!hmux)
273 goto err1;
274
275 hmux->nr_pads = nr_pads;
276
277 hmux->pads = kzalloc(sizeof(struct omap_device_pad) *
278 nr_pads, GFP_KERNEL);
279 if (!hmux->pads)
280 goto err2;
281
282 for (i = 0; i < hmux->nr_pads; i++) {
283 struct omap_mux_partition *partition;
284 struct omap_device_pad *bpad = &bpads[i], *pad = &hmux->pads[i];
285 struct omap_mux *mux;
286 int mux_mode;
287
288 mux_mode = omap_mux_get_by_name(bpad->name, &partition, &mux);
289 if (mux_mode < 0)
290 goto err3;
291 if (!pad->partition)
292 pad->partition = partition;
293 if (!pad->mux)
294 pad->mux = mux;
295
296 pad->name = kzalloc(strlen(bpad->name) + 1, GFP_KERNEL);
297 if (!pad->name) {
298 int j;
299
300 for (j = i - 1; j >= 0; j--)
301 kfree(hmux->pads[j].name);
302 goto err3;
303 }
304 strcpy(pad->name, bpad->name);
305
306 pad->flags = bpad->flags;
307 pad->enable = bpad->enable;
308 pad->idle = bpad->idle;
309 pad->off = bpad->off;
310
311 if (pad->flags &
312 (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP))
313 nr_pads_dynamic++;
314
315 pr_debug("%s: Initialized %s\n", __func__, pad->name);
316 }
317
318 if (!nr_pads_dynamic)
319 return hmux;
320
321 /*
322 * Add pads that need dynamic muxing into a separate list
323 */
324
325 hmux->nr_pads_dynamic = nr_pads_dynamic;
326 hmux->pads_dynamic = kzalloc(sizeof(struct omap_device_pad *) *
327 nr_pads_dynamic, GFP_KERNEL);
328 if (!hmux->pads_dynamic) {
329 pr_err("%s: Could not allocate dynamic pads\n", __func__);
330 return hmux;
331 }
332
333 nr_pads_dynamic = 0;
334 for (i = 0; i < hmux->nr_pads; i++) {
335 struct omap_device_pad *pad = &hmux->pads[i];
336
337 if (pad->flags &
338 (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP)) {
339 pr_debug("%s: pad %s tagged dynamic\n",
340 __func__, pad->name);
341 hmux->pads_dynamic[nr_pads_dynamic] = pad;
342 nr_pads_dynamic++;
343 }
344 }
345
346 return hmux;
347
348err3:
349 kfree(hmux->pads);
350err2:
351 kfree(hmux);
352err1:
353 pr_err("%s: Could not allocate device mux entry\n", __func__);
354
355 return NULL;
356}
357
358/**
359 * omap_hwmod_mux_scan_wakeups - omap hwmod scan wakeup pads
360 * @hmux: Pads for a hwmod
361 * @mpu_irqs: MPU irq array for a hwmod
362 *
363 * Scans the wakeup status of pads for a single hwmod. If an irq
364 * array is defined for this mux, the parser will call the registered
365 * ISRs for corresponding pads, otherwise the parser will stop at the
366 * first wakeup active pad and return. Returns true if there is a
367 * pending and non-served wakeup event for the mux, otherwise false.
368 */
369static bool omap_hwmod_mux_scan_wakeups(struct omap_hwmod_mux_info *hmux,
370 struct omap_hwmod_irq_info *mpu_irqs)
371{
372 int i, irq;
373 unsigned int val;
374 u32 handled_irqs = 0;
375
376 for (i = 0; i < hmux->nr_pads_dynamic; i++) {
377 struct omap_device_pad *pad = hmux->pads_dynamic[i];
378
379 if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP) ||
380 !(pad->idle & OMAP_WAKEUP_EN))
381 continue;
382
383 val = omap_mux_read(pad->partition, pad->mux->reg_offset);
384 if (!(val & OMAP_WAKEUP_EVENT))
385 continue;
386
387 if (!hmux->irqs)
388 return true;
389
390 irq = hmux->irqs[i];
391 /* make sure we only handle each irq once */
392 if (handled_irqs & 1 << irq)
393 continue;
394
395 handled_irqs |= 1 << irq;
396
397 generic_handle_irq(mpu_irqs[irq].irq);
398 }
399
400 return false;
401}
402
403/**
404 * _omap_hwmod_mux_handle_irq - Process wakeup events for a single hwmod
405 *
406 * Checks a single hwmod for every wakeup capable pad to see if there is an
407 * active wakeup event. If this is the case, call the corresponding ISR.
408 */
409static int _omap_hwmod_mux_handle_irq(struct omap_hwmod *oh, void *data)
410{
411 if (!oh->mux || !oh->mux->enabled)
412 return 0;
413 if (omap_hwmod_mux_scan_wakeups(oh->mux, oh->mpu_irqs))
414 generic_handle_irq(oh->mpu_irqs[0].irq);
415 return 0;
416}
417
418/**
419 * omap_hwmod_mux_handle_irq - Process pad wakeup irqs.
420 *
421 * Calls a function for each registered omap_hwmod to check
422 * pad wakeup statuses.
423 */
424static irqreturn_t omap_hwmod_mux_handle_irq(int irq, void *unused)
425{
426 omap_hwmod_for_each(_omap_hwmod_mux_handle_irq, NULL);
427 return IRQ_HANDLED;
428}
429
430/* Assumes the calling function takes care of locking */
431void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
432{
433 int i;
434
435 /* Runtime idling of dynamic pads */
436 if (state == _HWMOD_STATE_IDLE && hmux->enabled) {
437 for (i = 0; i < hmux->nr_pads_dynamic; i++) {
438 struct omap_device_pad *pad = hmux->pads_dynamic[i];
439 int val = -EINVAL;
440
441 val = pad->idle;
442 omap_mux_write(pad->partition, val,
443 pad->mux->reg_offset);
444 }
445
446 return;
447 }
448
449 /* Runtime enabling of dynamic pads */
450 if ((state == _HWMOD_STATE_ENABLED) && hmux->pads_dynamic
451 && hmux->enabled) {
452 for (i = 0; i < hmux->nr_pads_dynamic; i++) {
453 struct omap_device_pad *pad = hmux->pads_dynamic[i];
454 int val = -EINVAL;
455
456 val = pad->enable;
457 omap_mux_write(pad->partition, val,
458 pad->mux->reg_offset);
459 }
460
461 return;
462 }
463
464 /* Enabling or disabling of all pads */
465 for (i = 0; i < hmux->nr_pads; i++) {
466 struct omap_device_pad *pad = &hmux->pads[i];
467 int flags, val = -EINVAL;
468
469 flags = pad->flags;
470
471 switch (state) {
472 case _HWMOD_STATE_ENABLED:
473 val = pad->enable;
474 pr_debug("%s: Enabling %s %x\n", __func__,
475 pad->name, val);
476 break;
477 case _HWMOD_STATE_DISABLED:
478 /* Use safe mode unless OMAP_DEVICE_PAD_REMUX */
479 if (flags & OMAP_DEVICE_PAD_REMUX)
480 val = pad->off;
481 else
482 val = OMAP_MUX_MODE7;
483 pr_debug("%s: Disabling %s %x\n", __func__,
484 pad->name, val);
485 break;
486 default:
487 /* Nothing to be done */
488 break;
489 }
490
491 if (val >= 0) {
492 omap_mux_write(pad->partition, val,
493 pad->mux->reg_offset);
494 pad->flags = flags;
495 }
496 }
497
498 if (state == _HWMOD_STATE_ENABLED)
499 hmux->enabled = true;
500 else
501 hmux->enabled = false;
502}
503
504#ifdef CONFIG_DEBUG_FS
505
506#define OMAP_MUX_MAX_NR_FLAGS 10
507#define OMAP_MUX_TEST_FLAG(val, mask) \
508 if (((val) & (mask)) == (mask)) { \
509 i++; \
510 flags[i] = #mask; \
511 }
512
513/* REVISIT: Add checking for non-optimal mux settings */
514static inline void omap_mux_decode(struct seq_file *s, u16 val)
515{
516 char *flags[OMAP_MUX_MAX_NR_FLAGS];
517 char mode[sizeof("OMAP_MUX_MODE") + 1];
518 int i = -1;
519
520 sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
521 i++;
522 flags[i] = mode;
523
524 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
525 if (val & OMAP_OFF_EN) {
526 if (!(val & OMAP_OFFOUT_EN)) {
527 if (!(val & OMAP_OFF_PULL_UP)) {
528 OMAP_MUX_TEST_FLAG(val,
529 OMAP_PIN_OFF_INPUT_PULLDOWN);
530 } else {
531 OMAP_MUX_TEST_FLAG(val,
532 OMAP_PIN_OFF_INPUT_PULLUP);
533 }
534 } else {
535 if (!(val & OMAP_OFFOUT_VAL)) {
536 OMAP_MUX_TEST_FLAG(val,
537 OMAP_PIN_OFF_OUTPUT_LOW);
538 } else {
539 OMAP_MUX_TEST_FLAG(val,
540 OMAP_PIN_OFF_OUTPUT_HIGH);
541 }
542 }
543 }
544
545 if (val & OMAP_INPUT_EN) {
546 if (val & OMAP_PULL_ENA) {
547 if (!(val & OMAP_PULL_UP)) {
548 OMAP_MUX_TEST_FLAG(val,
549 OMAP_PIN_INPUT_PULLDOWN);
550 } else {
551 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
552 }
553 } else {
554 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
555 }
556 } else {
557 i++;
558 flags[i] = "OMAP_PIN_OUTPUT";
559 }
560
561 do {
562 seq_printf(s, "%s", flags[i]);
563 if (i > 0)
564 seq_puts(s, " | ");
565 } while (i-- > 0);
566}
567
568#define OMAP_MUX_DEFNAME_LEN 32
569
570static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
571{
572 struct omap_mux_partition *partition = s->private;
573 struct omap_mux_entry *e;
574 u8 omap_gen = omap_rev() >> 28;
575
576 list_for_each_entry(e, &partition->muxmodes, node) {
577 struct omap_mux *m = &e->mux;
578 char m0_def[OMAP_MUX_DEFNAME_LEN];
579 char *m0_name = m->muxnames[0];
580 u16 val;
581 int i, mode;
582
583 if (!m0_name)
584 continue;
585
586 /* REVISIT: Needs to be updated if mode0 names get longer */
587 for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
588 if (m0_name[i] == '\0') {
589 m0_def[i] = m0_name[i];
590 break;
591 }
592 m0_def[i] = toupper(m0_name[i]);
593 }
594 val = omap_mux_read(partition, m->reg_offset);
595 mode = val & OMAP_MUX_MODE7;
596 if (mode != 0)
597 seq_printf(s, "/* %s */\n", m->muxnames[mode]);
598
599 /*
600 * XXX: Might be revisited to support differences across
601 * same OMAP generation.
602 */
603 seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
604 omap_mux_decode(s, val);
605 seq_puts(s, "),\n");
606 }
607
608 return 0;
609}
610
611static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
612{
613 return single_open(file, omap_mux_dbg_board_show, inode->i_private);
614}
615
616static const struct file_operations omap_mux_dbg_board_fops = {
617 .open = omap_mux_dbg_board_open,
618 .read = seq_read,
619 .llseek = seq_lseek,
620 .release = single_release,
621};
622
623static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux)
624{
625 struct omap_mux_partition *partition;
626
627 list_for_each_entry(partition, &mux_partitions, node) {
628 struct list_head *muxmodes = &partition->muxmodes;
629 struct omap_mux_entry *e;
630
631 list_for_each_entry(e, muxmodes, node) {
632 struct omap_mux *m = &e->mux;
633
634 if (m == mux)
635 return partition;
636 }
637 }
638
639 return NULL;
640}
641
642static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
643{
644 struct omap_mux *m = s->private;
645 struct omap_mux_partition *partition;
646 const char *none = "NA";
647 u16 val;
648 int mode;
649
650 partition = omap_mux_get_partition(m);
651 if (!partition)
652 return 0;
653
654 val = omap_mux_read(partition, m->reg_offset);
655 mode = val & OMAP_MUX_MODE7;
656
657 seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n",
658 m->muxnames[0], m->muxnames[mode],
659 partition->phys + m->reg_offset, m->reg_offset, val,
660 m->balls[0] ? m->balls[0] : none,
661 m->balls[1] ? m->balls[1] : none);
662 seq_puts(s, "mode: ");
663 omap_mux_decode(s, val);
664 seq_putc(s, '\n');
665 seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n",
666 m->muxnames[0] ? m->muxnames[0] : none,
667 m->muxnames[1] ? m->muxnames[1] : none,
668 m->muxnames[2] ? m->muxnames[2] : none,
669 m->muxnames[3] ? m->muxnames[3] : none,
670 m->muxnames[4] ? m->muxnames[4] : none,
671 m->muxnames[5] ? m->muxnames[5] : none,
672 m->muxnames[6] ? m->muxnames[6] : none,
673 m->muxnames[7] ? m->muxnames[7] : none);
674
675 return 0;
676}
677
678#define OMAP_MUX_MAX_ARG_CHAR 7
679
680static ssize_t omap_mux_dbg_signal_write(struct file *file,
681 const char __user *user_buf,
682 size_t count, loff_t *ppos)
683{
684 struct seq_file *seqf;
685 struct omap_mux *m;
686 u16 val;
687 int ret;
688 struct omap_mux_partition *partition;
689
690 if (count > OMAP_MUX_MAX_ARG_CHAR)
691 return -EINVAL;
692
693 ret = kstrtou16_from_user(user_buf, count, 0x10, &val);
694 if (ret < 0)
695 return ret;
696
697 seqf = file->private_data;
698 m = seqf->private;
699
700 partition = omap_mux_get_partition(m);
701 if (!partition)
702 return -ENODEV;
703
704 omap_mux_write(partition, val, m->reg_offset);
705 *ppos += count;
706
707 return count;
708}
709
710static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file)
711{
712 return single_open(file, omap_mux_dbg_signal_show, inode->i_private);
713}
714
715static const struct file_operations omap_mux_dbg_signal_fops = {
716 .open = omap_mux_dbg_signal_open,
717 .read = seq_read,
718 .write = omap_mux_dbg_signal_write,
719 .llseek = seq_lseek,
720 .release = single_release,
721};
722
723static struct dentry *mux_dbg_dir;
724
725static void __init omap_mux_dbg_create_entry(
726 struct omap_mux_partition *partition,
727 struct dentry *mux_dbg_dir)
728{
729 struct omap_mux_entry *e;
730
731 list_for_each_entry(e, &partition->muxmodes, node) {
732 struct omap_mux *m = &e->mux;
733
734 (void)debugfs_create_file(m->muxnames[0], S_IWUSR | S_IRUGO,
735 mux_dbg_dir, m,
736 &omap_mux_dbg_signal_fops);
737 }
738}
739
740static void __init omap_mux_dbg_init(void)
741{
742 struct omap_mux_partition *partition;
743 static struct dentry *mux_dbg_board_dir;
744
745 mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
746 if (!mux_dbg_dir)
747 return;
748
749 mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir);
750 if (!mux_dbg_board_dir)
751 return;
752
753 list_for_each_entry(partition, &mux_partitions, node) {
754 omap_mux_dbg_create_entry(partition, mux_dbg_dir);
755 (void)debugfs_create_file(partition->name, S_IRUGO,
756 mux_dbg_board_dir, partition,
757 &omap_mux_dbg_board_fops);
758 }
759}
760
761#else
762static inline void omap_mux_dbg_init(void)
763{
764}
765#endif /* CONFIG_DEBUG_FS */
766
767static void __init omap_mux_free_names(struct omap_mux *m)
768{
769 int i;
770
771 for (i = 0; i < OMAP_MUX_NR_MODES; i++)
772 kfree(m->muxnames[i]);
773
774#ifdef CONFIG_DEBUG_FS
775 for (i = 0; i < OMAP_MUX_NR_SIDES; i++)
776 kfree(m->balls[i]);
777#endif
778
779}
780
781/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
782int __init omap_mux_late_init(void)
783{
784 struct omap_mux_partition *partition;
785 int ret;
786
787 list_for_each_entry(partition, &mux_partitions, node) {
788 struct omap_mux_entry *e, *tmp;
789 list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) {
790 struct omap_mux *m = &e->mux;
791 u16 mode = omap_mux_read(partition, m->reg_offset);
792
793 if (OMAP_MODE_GPIO(partition, mode))
794 continue;
795
796#ifndef CONFIG_DEBUG_FS
797 mutex_lock(&muxmode_mutex);
798 list_del(&e->node);
799 mutex_unlock(&muxmode_mutex);
800 omap_mux_free_names(m);
801 kfree(m);
802#endif
803 }
804 }
805
806 omap_mux_dbg_init();
807
808 /* see pinctrl-single-omap for the wake-up interrupt handling */
809 if (of_have_populated_dt())
810 return 0;
811
812 ret = request_irq(omap_prcm_event_to_irq("io"),
813 omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND,
814 "hwmod_io", omap_mux_late_init);
815
816 if (ret)
817 pr_warn("mux: Failed to setup hwmod io irq %d\n", ret);
818
819 return 0;
820}
821
822static void __init omap_mux_package_fixup(struct omap_mux *p,
823 struct omap_mux *superset)
824{
825 while (p->reg_offset != OMAP_MUX_TERMINATOR) {
826 struct omap_mux *s = superset;
827 int found = 0;
828
829 while (s->reg_offset != OMAP_MUX_TERMINATOR) {
830 if (s->reg_offset == p->reg_offset) {
831 *s = *p;
832 found++;
833 break;
834 }
835 s++;
836 }
837 if (!found)
838 pr_err("%s: Unknown entry offset 0x%x\n", __func__,
839 p->reg_offset);
840 p++;
841 }
842}
843
844#ifdef CONFIG_DEBUG_FS
845
846static void __init omap_mux_package_init_balls(struct omap_ball *b,
847 struct omap_mux *superset)
848{
849 while (b->reg_offset != OMAP_MUX_TERMINATOR) {
850 struct omap_mux *s = superset;
851 int found = 0;
852
853 while (s->reg_offset != OMAP_MUX_TERMINATOR) {
854 if (s->reg_offset == b->reg_offset) {
855 s->balls[0] = b->balls[0];
856 s->balls[1] = b->balls[1];
857 found++;
858 break;
859 }
860 s++;
861 }
862 if (!found)
863 pr_err("%s: Unknown ball offset 0x%x\n", __func__,
864 b->reg_offset);
865 b++;
866 }
867}
868
869#else /* CONFIG_DEBUG_FS */
870
871static inline void omap_mux_package_init_balls(struct omap_ball *b,
872 struct omap_mux *superset)
873{
874}
875
876#endif /* CONFIG_DEBUG_FS */
877
878static int __init omap_mux_setup(char *options)
879{
880 if (!options)
881 return 0;
882
883 omap_mux_options = options;
884
885 return 1;
886}
887__setup("omap_mux=", omap_mux_setup);
888
889/*
890 * Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234
891 * cmdline options only override the bootloader values.
892 * During development, please enable CONFIG_DEBUG_FS, and use the
893 * signal specific entries under debugfs.
894 */
895static void __init omap_mux_set_cmdline_signals(void)
896{
897 char *options, *next_opt, *token;
898
899 if (!omap_mux_options)
900 return;
901
902 options = kstrdup(omap_mux_options, GFP_KERNEL);
903 if (!options)
904 return;
905
906 next_opt = options;
907
908 while ((token = strsep(&next_opt, ",")) != NULL) {
909 char *keyval, *name;
910 u16 val;
911
912 keyval = token;
913 name = strsep(&keyval, "=");
914 if (name) {
915 int res;
916
917 res = kstrtou16(keyval, 0x10, &val);
918 if (res < 0)
919 continue;
920
921 omap_mux_init_signal(name, (u16)val);
922 }
923 }
924
925 kfree(options);
926}
927
928static int __init omap_mux_copy_names(struct omap_mux *src,
929 struct omap_mux *dst)
930{
931 int i;
932
933 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
934 if (src->muxnames[i]) {
935 dst->muxnames[i] = kstrdup(src->muxnames[i],
936 GFP_KERNEL);
937 if (!dst->muxnames[i])
938 goto free;
939 }
940 }
941
942#ifdef CONFIG_DEBUG_FS
943 for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
944 if (src->balls[i]) {
945 dst->balls[i] = kstrdup(src->balls[i], GFP_KERNEL);
946 if (!dst->balls[i])
947 goto free;
948 }
949 }
950#endif
951
952 return 0;
953
954free:
955 omap_mux_free_names(dst);
956 return -ENOMEM;
957
958}
959
960#endif /* CONFIG_OMAP_MUX */
961
962static struct omap_mux *omap_mux_get_by_gpio(
963 struct omap_mux_partition *partition,
964 int gpio)
965{
966 struct omap_mux_entry *e;
967 struct omap_mux *ret = NULL;
968
969 list_for_each_entry(e, &partition->muxmodes, node) {
970 struct omap_mux *m = &e->mux;
971 if (m->gpio == gpio) {
972 ret = m;
973 break;
974 }
975 }
976
977 return ret;
978}
979
980/* Needed for dynamic muxing of GPIO pins for off-idle */
981u16 omap_mux_get_gpio(int gpio)
982{
983 struct omap_mux_partition *partition;
984 struct omap_mux *m = NULL;
985
986 list_for_each_entry(partition, &mux_partitions, node) {
987 m = omap_mux_get_by_gpio(partition, gpio);
988 if (m)
989 return omap_mux_read(partition, m->reg_offset);
990 }
991
992 if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
993 pr_err("%s: Could not get gpio%i\n", __func__, gpio);
994
995 return OMAP_MUX_TERMINATOR;
996}
997
998/* Needed for dynamic muxing of GPIO pins for off-idle */
999void omap_mux_set_gpio(u16 val, int gpio)
1000{
1001 struct omap_mux_partition *partition;
1002 struct omap_mux *m = NULL;
1003
1004 list_for_each_entry(partition, &mux_partitions, node) {
1005 m = omap_mux_get_by_gpio(partition, gpio);
1006 if (m) {
1007 omap_mux_write(partition, val, m->reg_offset);
1008 return;
1009 }
1010 }
1011
1012 if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
1013 pr_err("%s: Could not set gpio%i\n", __func__, gpio);
1014}
1015
1016static struct omap_mux * __init omap_mux_list_add(
1017 struct omap_mux_partition *partition,
1018 struct omap_mux *src)
1019{
1020 struct omap_mux_entry *entry;
1021 struct omap_mux *m;
1022
1023 entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL);
1024 if (!entry)
1025 return NULL;
1026
1027 m = &entry->mux;
1028 entry->mux = *src;
1029
1030#ifdef CONFIG_OMAP_MUX
1031 if (omap_mux_copy_names(src, m)) {
1032 kfree(entry);
1033 return NULL;
1034 }
1035#endif
1036
1037 mutex_lock(&muxmode_mutex);
1038 list_add_tail(&entry->node, &partition->muxmodes);
1039 mutex_unlock(&muxmode_mutex);
1040
1041 return m;
1042}
1043
1044/*
1045 * Note if CONFIG_OMAP_MUX is not selected, we will only initialize
1046 * the GPIO to mux offset mapping that is needed for dynamic muxing
1047 * of GPIO pins for off-idle.
1048 */
1049static void __init omap_mux_init_list(struct omap_mux_partition *partition,
1050 struct omap_mux *superset)
1051{
1052 while (superset->reg_offset != OMAP_MUX_TERMINATOR) {
1053 struct omap_mux *entry;
1054
1055#ifdef CONFIG_OMAP_MUX
1056 if (!superset->muxnames[0]) {
1057 superset++;
1058 continue;
1059 }
1060#else
1061 /* Skip pins that are not muxed as GPIO by bootloader */
1062 if (!OMAP_MODE_GPIO(partition, omap_mux_read(partition,
1063 superset->reg_offset))) {
1064 superset++;
1065 continue;
1066 }
1067#endif
1068
1069 entry = omap_mux_list_add(partition, superset);
1070 if (!entry) {
1071 pr_err("%s: Could not add entry\n", __func__);
1072 return;
1073 }
1074 superset++;
1075 }
1076}
1077
1078#ifdef CONFIG_OMAP_MUX
1079
1080static void omap_mux_init_package(struct omap_mux *superset,
1081 struct omap_mux *package_subset,
1082 struct omap_ball *package_balls)
1083{
1084 if (package_subset)
1085 omap_mux_package_fixup(package_subset, superset);
1086 if (package_balls)
1087 omap_mux_package_init_balls(package_balls, superset);
1088}
1089
1090static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
1091 struct omap_board_mux *board_mux)
1092{
1093 omap_mux_set_cmdline_signals();
1094 omap_mux_write_array(partition, board_mux);
1095}
1096
1097#else
1098
1099static void omap_mux_init_package(struct omap_mux *superset,
1100 struct omap_mux *package_subset,
1101 struct omap_ball *package_balls)
1102{
1103}
1104
1105static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
1106 struct omap_board_mux *board_mux)
1107{
1108}
1109
1110#endif
1111
1112static u32 mux_partitions_cnt;
1113
1114int __init omap_mux_init(const char *name, u32 flags,
1115 u32 mux_pbase, u32 mux_size,
1116 struct omap_mux *superset,
1117 struct omap_mux *package_subset,
1118 struct omap_board_mux *board_mux,
1119 struct omap_ball *package_balls)
1120{
1121 struct omap_mux_partition *partition;
1122
1123 partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL);
1124 if (!partition)
1125 return -ENOMEM;
1126
1127 partition->name = name;
1128 partition->flags = flags;
1129 partition->gpio = flags & OMAP_MUX_MODE7;
1130 partition->size = mux_size;
1131 partition->phys = mux_pbase;
1132 partition->base = ioremap(mux_pbase, mux_size);
1133 if (!partition->base) {
1134 pr_err("%s: Could not ioremap mux partition at 0x%08x\n",
1135 __func__, partition->phys);
1136 kfree(partition);
1137 return -ENODEV;
1138 }
1139
1140 INIT_LIST_HEAD(&partition->muxmodes);
1141
1142 list_add_tail(&partition->node, &mux_partitions);
1143 mux_partitions_cnt++;
1144 pr_info("%s: Add partition: #%d: %s, flags: %x\n", __func__,
1145 mux_partitions_cnt, partition->name, partition->flags);
1146
1147 omap_mux_init_package(superset, package_subset, package_balls);
1148 omap_mux_init_list(partition, superset);
1149 omap_mux_init_signals(partition, board_mux);
1150
1151 return 0;
1152}
1153
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
deleted file mode 100644
index d121fb6df4e6..000000000000
--- a/arch/arm/mach-omap2/mux.h
+++ /dev/null
@@ -1,352 +0,0 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009-2010 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include "mux34xx.h"
11
12#define OMAP_MUX_TERMINATOR 0xffff
13
14/* 34xx mux mode options for each pin. See TRM for options */
15#define OMAP_MUX_MODE0 0
16#define OMAP_MUX_MODE1 1
17#define OMAP_MUX_MODE2 2
18#define OMAP_MUX_MODE3 3
19#define OMAP_MUX_MODE4 4
20#define OMAP_MUX_MODE5 5
21#define OMAP_MUX_MODE6 6
22#define OMAP_MUX_MODE7 7
23
24/* 24xx/34xx mux bit defines */
25#define OMAP_PULL_ENA (1 << 3)
26#define OMAP_PULL_UP (1 << 4)
27#define OMAP_ALTELECTRICALSEL (1 << 5)
28
29/* omap3/4/5 specific mux bit defines */
30#define OMAP_INPUT_EN (1 << 8)
31#define OMAP_OFF_EN (1 << 9)
32#define OMAP_OFFOUT_EN (1 << 10)
33#define OMAP_OFFOUT_VAL (1 << 11)
34#define OMAP_OFF_PULL_EN (1 << 12)
35#define OMAP_OFF_PULL_UP (1 << 13)
36#define OMAP_WAKEUP_EN (1 << 14)
37#define OMAP_WAKEUP_EVENT (1 << 15)
38
39/* Active pin states */
40#define OMAP_PIN_OUTPUT 0
41#define OMAP_PIN_INPUT OMAP_INPUT_EN
42#define OMAP_PIN_INPUT_PULLUP (OMAP_PULL_ENA | OMAP_INPUT_EN \
43 | OMAP_PULL_UP)
44#define OMAP_PIN_INPUT_PULLDOWN (OMAP_PULL_ENA | OMAP_INPUT_EN)
45
46/* Off mode states */
47#define OMAP_PIN_OFF_NONE 0
48#define OMAP_PIN_OFF_OUTPUT_HIGH (OMAP_OFF_EN | OMAP_OFFOUT_EN \
49 | OMAP_OFFOUT_VAL)
50#define OMAP_PIN_OFF_OUTPUT_LOW (OMAP_OFF_EN | OMAP_OFFOUT_EN)
51#define OMAP_PIN_OFF_INPUT_PULLUP (OMAP_OFF_EN | OMAP_OFF_PULL_EN \
52 | OMAP_OFF_PULL_UP)
53#define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN)
54#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN
55
56#define OMAP_MODE_GPIO(partition, x) (((x) & OMAP_MUX_MODE7) == \
57 partition->gpio)
58#define OMAP_MODE_UART(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE0)
59
60/* Flags for omapX_mux_init */
61#define OMAP_PACKAGE_MASK 0xffff
62#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
63#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
64#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */
65#define OMAP_PACKAGE_CBC 3 /* 515-pin 0.50 0.65 */
66
67#define OMAP_MUX_NR_MODES 8 /* Available modes */
68#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */
69
70/*
71 * omap_mux_init flags definition:
72 *
73 * OMAP_GPIO_MUX_MODE, bits 0-2: gpio muxing mode, same like pad control
74 * register which includes values from 0-7.
75 * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
76 * The default value is 16 bits.
77 */
78#define OMAP_MUX_GPIO_IN_MODE0 OMAP_MUX_MODE0
79#define OMAP_MUX_GPIO_IN_MODE1 OMAP_MUX_MODE1
80#define OMAP_MUX_GPIO_IN_MODE2 OMAP_MUX_MODE2
81#define OMAP_MUX_GPIO_IN_MODE3 OMAP_MUX_MODE3
82#define OMAP_MUX_GPIO_IN_MODE4 OMAP_MUX_MODE4
83#define OMAP_MUX_GPIO_IN_MODE5 OMAP_MUX_MODE5
84#define OMAP_MUX_GPIO_IN_MODE6 OMAP_MUX_MODE6
85#define OMAP_MUX_GPIO_IN_MODE7 OMAP_MUX_MODE7
86#define OMAP_MUX_REG_8BIT (1 << 3)
87
88/**
89 * struct omap_board_data - board specific device data
90 * @id: instance id
91 * @flags: additional flags for platform init code
92 * @pads: array of device specific pads
93 * @pads_cnt: ARRAY_SIZE() of pads
94 */
95struct omap_board_data {
96 int id;
97 u32 flags;
98 struct omap_device_pad *pads;
99 int pads_cnt;
100};
101
102/**
103 * struct mux_partition - contain partition related information
104 * @name: name of the current partition
105 * @flags: flags specific to this partition
106 * @gpio: gpio mux mode
107 * @phys: physical address
108 * @size: partition size
109 * @base: virtual address after ioremap
110 * @muxmodes: list of nodes that belong to a partition
111 * @node: list node for the partitions linked list
112 */
113struct omap_mux_partition {
114 const char *name;
115 u32 flags;
116 u32 gpio;
117 u32 phys;
118 u32 size;
119 void __iomem *base;
120 struct list_head muxmodes;
121 struct list_head node;
122};
123
124/**
125 * struct omap_mux - data for omap mux register offset and it's value
126 * @reg_offset: mux register offset from the mux base
127 * @gpio: GPIO number
128 * @muxnames: available signal modes for a ball
129 * @balls: available balls on the package
130 */
131struct omap_mux {
132 u16 reg_offset;
133 u16 gpio;
134#ifdef CONFIG_OMAP_MUX
135 char *muxnames[OMAP_MUX_NR_MODES];
136#ifdef CONFIG_DEBUG_FS
137 char *balls[OMAP_MUX_NR_SIDES];
138#endif
139#endif
140};
141
142/**
143 * struct omap_ball - data for balls on omap package
144 * @reg_offset: mux register offset from the mux base
145 * @balls: available balls on the package
146 */
147struct omap_ball {
148 u16 reg_offset;
149 char *balls[OMAP_MUX_NR_SIDES];
150};
151
152/**
153 * struct omap_board_mux - data for initializing mux registers
154 * @reg_offset: mux register offset from the mux base
155 * @mux_value: desired mux value to set
156 */
157struct omap_board_mux {
158 u16 reg_offset;
159 u16 value;
160};
161
162#define OMAP_DEVICE_PAD_REMUX BIT(1) /* Dynamically remux a pad,
163 needs enable, idle and off
164 values */
165#define OMAP_DEVICE_PAD_WAKEUP BIT(0) /* Pad is wake-up capable */
166
167/**
168 * struct omap_device_pad - device specific pad configuration
169 * @name: signal name
170 * @flags: pad specific runtime flags
171 * @enable: runtime value for a pad
172 * @idle: idle value for a pad
173 * @off: off value for a pad, defaults to safe mode
174 * @partition: mux partition
175 * @mux: mux register
176 */
177struct omap_device_pad {
178 char *name;
179 u8 flags;
180 u16 enable;
181 u16 idle;
182 u16 off;
183 struct omap_mux_partition *partition;
184 struct omap_mux *mux;
185};
186
187struct omap_hwmod_mux_info;
188
189#define OMAP_MUX_STATIC(signal, mode) \
190{ \
191 .name = (signal), \
192 .enable = (mode), \
193}
194
195#if defined(CONFIG_OMAP_MUX)
196
197/**
198 * omap_mux_init_gpio - initialize a signal based on the GPIO number
199 * @gpio: GPIO number
200 * @val: Options for the mux register value
201 */
202int omap_mux_init_gpio(int gpio, int val);
203
204/**
205 * omap_mux_init_signal - initialize a signal based on the signal name
206 * @muxname: Mux name in mode0_name.signal_name format
207 * @val: Options for the mux register value
208 */
209int omap_mux_init_signal(const char *muxname, int val);
210
211/**
212 * omap_hwmod_mux_init - initialize hwmod specific mux data
213 * @bpads: Board specific device signal names
214 * @nr_pads: Number of signal names for the device
215 */
216extern struct omap_hwmod_mux_info *
217omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads);
218
219/**
220 * omap_hwmod_mux - omap hwmod specific pin muxing
221 * @hmux: Pads for a hwmod
222 * @state: Desired _HWMOD_STATE
223 *
224 * Called only from omap_hwmod.c, do not use.
225 */
226void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state);
227
228int omap_mux_get_by_name(const char *muxname,
229 struct omap_mux_partition **found_partition,
230 struct omap_mux **found_mux);
231#else
232
233static inline int omap_mux_get_by_name(const char *muxname,
234 struct omap_mux_partition **found_partition,
235 struct omap_mux **found_mux)
236{
237 return 0;
238}
239
240static inline int omap_mux_init_gpio(int gpio, int val)
241{
242 return 0;
243}
244static inline int omap_mux_init_signal(char *muxname, int val)
245{
246 return 0;
247}
248
249static inline struct omap_hwmod_mux_info *
250omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
251{
252 return NULL;
253}
254
255static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
256{
257}
258
259static struct omap_board_mux *board_mux __maybe_unused;
260
261#endif
262
263/**
264 * omap_mux_get_gpio() - get mux register value based on GPIO number
265 * @gpio: GPIO number
266 *
267 */
268u16 omap_mux_get_gpio(int gpio);
269
270/**
271 * omap_mux_set_gpio() - set mux register value based on GPIO number
272 * @val: New mux register value
273 * @gpio: GPIO number
274 *
275 */
276void omap_mux_set_gpio(u16 val, int gpio);
277
278/**
279 * omap_mux_get() - get a mux partition by name
280 * @name: Name of the mux partition
281 *
282 */
283struct omap_mux_partition *omap_mux_get(const char *name);
284
285/**
286 * omap_mux_read() - read mux register
287 * @partition: Mux partition
288 * @mux_offset: Offset of the mux register
289 *
290 */
291u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset);
292
293/**
294 * omap_mux_write() - write mux register
295 * @partition: Mux partition
296 * @val: New mux register value
297 * @mux_offset: Offset of the mux register
298 *
299 * This should be only needed for dynamic remuxing of non-gpio signals.
300 */
301void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset);
302
303/**
304 * omap_mux_write_array() - write an array of mux registers
305 * @partition: Mux partition
306 * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
307 *
308 * This should be only needed for dynamic remuxing of non-gpio signals.
309 */
310void omap_mux_write_array(struct omap_mux_partition *p,
311 struct omap_board_mux *board_mux);
312
313/**
314 * omap2420_mux_init() - initialize mux system with board specific set
315 * @board_mux: Board specific mux table
316 * @flags: OMAP package type used for the board
317 */
318int omap2420_mux_init(struct omap_board_mux *board_mux, int flags);
319
320/**
321 * omap2430_mux_init() - initialize mux system with board specific set
322 * @board_mux: Board specific mux table
323 * @flags: OMAP package type used for the board
324 */
325int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
326
327/**
328 * omap3_mux_init() - initialize mux system with board specific set
329 * @board_mux: Board specific mux table
330 * @flags: OMAP package type used for the board
331 */
332int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
333
334/**
335 * omap4_mux_init() - initialize mux system with board specific set
336 * @board_subset: Board specific mux table
337 * @board_wkup_subset: Board specific mux table for wakeup instance
338 * @flags: OMAP package type used for the board
339 */
340int omap4_mux_init(struct omap_board_mux *board_subset,
341 struct omap_board_mux *board_wkup_subset, int flags);
342
343/**
344 * omap_mux_init - private mux init function, do not call
345 */
346int omap_mux_init(const char *name, u32 flags,
347 u32 mux_pbase, u32 mux_size,
348 struct omap_mux *superset,
349 struct omap_mux *package_subset,
350 struct omap_board_mux *board_mux,
351 struct omap_ball *package_balls);
352
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
deleted file mode 100644
index 393e687f99e2..000000000000
--- a/arch/arm/mach-omap2/mux34xx.c
+++ /dev/null
@@ -1,2061 +0,0 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12
13#include "mux.h"
14
15#ifdef CONFIG_OMAP_MUX
16
17#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
18{ \
19 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
20 .gpio = (g), \
21 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
22}
23
24#else
25
26#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
27{ \
28 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
29 .gpio = (g), \
30}
31
32#endif
33
34#define _OMAP3_BALLENTRY(M0, bb, bt) \
35{ \
36 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
37 .balls = { bb, bt }, \
38}
39
40/*
41 * Superset of all mux modes for omap3
42 */
43static struct omap_mux __initdata omap3_muxmodes[] = {
44 _OMAP3_MUXENTRY(CAM_D0, 99,
45 "cam_d0", NULL, NULL, NULL,
46 "gpio_99", NULL, NULL, "safe_mode"),
47 _OMAP3_MUXENTRY(CAM_D1, 100,
48 "cam_d1", NULL, NULL, NULL,
49 "gpio_100", NULL, NULL, "safe_mode"),
50 _OMAP3_MUXENTRY(CAM_D10, 109,
51 "cam_d10", NULL, NULL, NULL,
52 "gpio_109", "hw_dbg8", NULL, "safe_mode"),
53 _OMAP3_MUXENTRY(CAM_D11, 110,
54 "cam_d11", NULL, NULL, NULL,
55 "gpio_110", "hw_dbg9", NULL, "safe_mode"),
56 _OMAP3_MUXENTRY(CAM_D2, 101,
57 "cam_d2", NULL, NULL, NULL,
58 "gpio_101", "hw_dbg4", NULL, "safe_mode"),
59 _OMAP3_MUXENTRY(CAM_D3, 102,
60 "cam_d3", NULL, NULL, NULL,
61 "gpio_102", "hw_dbg5", NULL, "safe_mode"),
62 _OMAP3_MUXENTRY(CAM_D4, 103,
63 "cam_d4", NULL, NULL, NULL,
64 "gpio_103", "hw_dbg6", NULL, "safe_mode"),
65 _OMAP3_MUXENTRY(CAM_D5, 104,
66 "cam_d5", NULL, NULL, NULL,
67 "gpio_104", "hw_dbg7", NULL, "safe_mode"),
68 _OMAP3_MUXENTRY(CAM_D6, 105,
69 "cam_d6", NULL, NULL, NULL,
70 "gpio_105", NULL, NULL, "safe_mode"),
71 _OMAP3_MUXENTRY(CAM_D7, 106,
72 "cam_d7", NULL, NULL, NULL,
73 "gpio_106", NULL, NULL, "safe_mode"),
74 _OMAP3_MUXENTRY(CAM_D8, 107,
75 "cam_d8", NULL, NULL, NULL,
76 "gpio_107", NULL, NULL, "safe_mode"),
77 _OMAP3_MUXENTRY(CAM_D9, 108,
78 "cam_d9", NULL, NULL, NULL,
79 "gpio_108", NULL, NULL, "safe_mode"),
80 _OMAP3_MUXENTRY(CAM_FLD, 98,
81 "cam_fld", NULL, "cam_global_reset", NULL,
82 "gpio_98", "hw_dbg3", NULL, "safe_mode"),
83 _OMAP3_MUXENTRY(CAM_HS, 94,
84 "cam_hs", NULL, NULL, NULL,
85 "gpio_94", "hw_dbg0", NULL, "safe_mode"),
86 _OMAP3_MUXENTRY(CAM_PCLK, 97,
87 "cam_pclk", NULL, NULL, NULL,
88 "gpio_97", "hw_dbg2", NULL, "safe_mode"),
89 _OMAP3_MUXENTRY(CAM_STROBE, 126,
90 "cam_strobe", NULL, NULL, NULL,
91 "gpio_126", "hw_dbg11", NULL, "safe_mode"),
92 _OMAP3_MUXENTRY(CAM_VS, 95,
93 "cam_vs", NULL, NULL, NULL,
94 "gpio_95", "hw_dbg1", NULL, "safe_mode"),
95 _OMAP3_MUXENTRY(CAM_WEN, 167,
96 "cam_wen", NULL, "cam_shutter", NULL,
97 "gpio_167", "hw_dbg10", NULL, "safe_mode"),
98 _OMAP3_MUXENTRY(CAM_XCLKA, 96,
99 "cam_xclka", NULL, NULL, NULL,
100 "gpio_96", NULL, NULL, "safe_mode"),
101 _OMAP3_MUXENTRY(CAM_XCLKB, 111,
102 "cam_xclkb", NULL, NULL, NULL,
103 "gpio_111", NULL, NULL, "safe_mode"),
104 _OMAP3_MUXENTRY(CSI2_DX0, 112,
105 "csi2_dx0", NULL, NULL, NULL,
106 "gpio_112", NULL, NULL, "safe_mode"),
107 _OMAP3_MUXENTRY(CSI2_DX1, 114,
108 "csi2_dx1", NULL, NULL, NULL,
109 "gpio_114", NULL, NULL, "safe_mode"),
110 _OMAP3_MUXENTRY(CSI2_DY0, 113,
111 "csi2_dy0", NULL, NULL, NULL,
112 "gpio_113", NULL, NULL, "safe_mode"),
113 _OMAP3_MUXENTRY(CSI2_DY1, 115,
114 "csi2_dy1", NULL, NULL, NULL,
115 "gpio_115", NULL, NULL, "safe_mode"),
116 _OMAP3_MUXENTRY(DSS_ACBIAS, 69,
117 "dss_acbias", NULL, NULL, NULL,
118 "gpio_69", NULL, NULL, "safe_mode"),
119 _OMAP3_MUXENTRY(DSS_DATA0, 70,
120 "dss_data0", NULL, "uart1_cts", NULL,
121 "gpio_70", NULL, NULL, "safe_mode"),
122 _OMAP3_MUXENTRY(DSS_DATA1, 71,
123 "dss_data1", NULL, "uart1_rts", NULL,
124 "gpio_71", NULL, NULL, "safe_mode"),
125 _OMAP3_MUXENTRY(DSS_DATA10, 80,
126 "dss_data10", NULL, NULL, NULL,
127 "gpio_80", NULL, NULL, "safe_mode"),
128 _OMAP3_MUXENTRY(DSS_DATA11, 81,
129 "dss_data11", NULL, NULL, NULL,
130 "gpio_81", NULL, NULL, "safe_mode"),
131 _OMAP3_MUXENTRY(DSS_DATA12, 82,
132 "dss_data12", NULL, NULL, NULL,
133 "gpio_82", NULL, NULL, "safe_mode"),
134 _OMAP3_MUXENTRY(DSS_DATA13, 83,
135 "dss_data13", NULL, NULL, NULL,
136 "gpio_83", NULL, NULL, "safe_mode"),
137 _OMAP3_MUXENTRY(DSS_DATA14, 84,
138 "dss_data14", NULL, NULL, NULL,
139 "gpio_84", NULL, NULL, "safe_mode"),
140 _OMAP3_MUXENTRY(DSS_DATA15, 85,
141 "dss_data15", NULL, NULL, NULL,
142 "gpio_85", NULL, NULL, "safe_mode"),
143 _OMAP3_MUXENTRY(DSS_DATA16, 86,
144 "dss_data16", NULL, NULL, NULL,
145 "gpio_86", NULL, NULL, "safe_mode"),
146 _OMAP3_MUXENTRY(DSS_DATA17, 87,
147 "dss_data17", NULL, NULL, NULL,
148 "gpio_87", NULL, NULL, "safe_mode"),
149 _OMAP3_MUXENTRY(DSS_DATA18, 88,
150 "dss_data18", NULL, "mcspi3_clk", "dss_data0",
151 "gpio_88", NULL, NULL, "safe_mode"),
152 _OMAP3_MUXENTRY(DSS_DATA19, 89,
153 "dss_data19", NULL, "mcspi3_simo", "dss_data1",
154 "gpio_89", NULL, NULL, "safe_mode"),
155 _OMAP3_MUXENTRY(DSS_DATA20, 90,
156 "dss_data20", NULL, "mcspi3_somi", "dss_data2",
157 "gpio_90", NULL, NULL, "safe_mode"),
158 _OMAP3_MUXENTRY(DSS_DATA21, 91,
159 "dss_data21", NULL, "mcspi3_cs0", "dss_data3",
160 "gpio_91", NULL, NULL, "safe_mode"),
161 _OMAP3_MUXENTRY(DSS_DATA22, 92,
162 "dss_data22", NULL, "mcspi3_cs1", "dss_data4",
163 "gpio_92", NULL, NULL, "safe_mode"),
164 _OMAP3_MUXENTRY(DSS_DATA23, 93,
165 "dss_data23", NULL, NULL, "dss_data5",
166 "gpio_93", NULL, NULL, "safe_mode"),
167 _OMAP3_MUXENTRY(DSS_DATA2, 72,
168 "dss_data2", NULL, NULL, NULL,
169 "gpio_72", NULL, NULL, "safe_mode"),
170 _OMAP3_MUXENTRY(DSS_DATA3, 73,
171 "dss_data3", NULL, NULL, NULL,
172 "gpio_73", NULL, NULL, "safe_mode"),
173 _OMAP3_MUXENTRY(DSS_DATA4, 74,
174 "dss_data4", NULL, "uart3_rx_irrx", NULL,
175 "gpio_74", NULL, NULL, "safe_mode"),
176 _OMAP3_MUXENTRY(DSS_DATA5, 75,
177 "dss_data5", NULL, "uart3_tx_irtx", NULL,
178 "gpio_75", NULL, NULL, "safe_mode"),
179 _OMAP3_MUXENTRY(DSS_DATA6, 76,
180 "dss_data6", NULL, "uart1_tx", NULL,
181 "gpio_76", "hw_dbg14", NULL, "safe_mode"),
182 _OMAP3_MUXENTRY(DSS_DATA7, 77,
183 "dss_data7", NULL, "uart1_rx", NULL,
184 "gpio_77", "hw_dbg15", NULL, "safe_mode"),
185 _OMAP3_MUXENTRY(DSS_DATA8, 78,
186 "dss_data8", NULL, NULL, NULL,
187 "gpio_78", "hw_dbg16", NULL, "safe_mode"),
188 _OMAP3_MUXENTRY(DSS_DATA9, 79,
189 "dss_data9", NULL, NULL, NULL,
190 "gpio_79", "hw_dbg17", NULL, "safe_mode"),
191 _OMAP3_MUXENTRY(DSS_HSYNC, 67,
192 "dss_hsync", NULL, NULL, NULL,
193 "gpio_67", "hw_dbg13", NULL, "safe_mode"),
194 _OMAP3_MUXENTRY(DSS_PCLK, 66,
195 "dss_pclk", NULL, NULL, NULL,
196 "gpio_66", "hw_dbg12", NULL, "safe_mode"),
197 _OMAP3_MUXENTRY(DSS_VSYNC, 68,
198 "dss_vsync", NULL, NULL, NULL,
199 "gpio_68", NULL, NULL, "safe_mode"),
200 _OMAP3_MUXENTRY(ETK_CLK, 12,
201 "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
202 "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", "hw_dbg0"),
203 _OMAP3_MUXENTRY(ETK_CTL, 13,
204 "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
205 "gpio_13", NULL, "hsusb1_tll_clk", "hw_dbg1"),
206 _OMAP3_MUXENTRY(ETK_D0, 14,
207 "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
208 "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", "hw_dbg2"),
209 _OMAP3_MUXENTRY(ETK_D1, 15,
210 "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
211 "gpio_15", "mm1_txse0", "hsusb1_tll_data1", "hw_dbg3"),
212 _OMAP3_MUXENTRY(ETK_D10, 24,
213 "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
214 "gpio_24", NULL, "hsusb2_tll_clk", "hw_dbg12"),
215 _OMAP3_MUXENTRY(ETK_D11, 25,
216 "etk_d11", NULL, NULL, "hsusb2_stp",
217 "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", "hw_dbg13"),
218 _OMAP3_MUXENTRY(ETK_D12, 26,
219 "etk_d12", NULL, NULL, "hsusb2_dir",
220 "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
221 _OMAP3_MUXENTRY(ETK_D13, 27,
222 "etk_d13", NULL, NULL, "hsusb2_nxt",
223 "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", "hw_dbg15"),
224 _OMAP3_MUXENTRY(ETK_D14, 28,
225 "etk_d14", NULL, NULL, "hsusb2_data0",
226 "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", "hw_dbg16"),
227 _OMAP3_MUXENTRY(ETK_D15, 29,
228 "etk_d15", NULL, NULL, "hsusb2_data1",
229 "gpio_29", "mm2_txse0", "hsusb2_tll_data1", "hw_dbg17"),
230 _OMAP3_MUXENTRY(ETK_D2, 16,
231 "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
232 "gpio_16", "mm1_txdat", "hsusb1_tll_data2", "hw_dbg4"),
233 _OMAP3_MUXENTRY(ETK_D3, 17,
234 "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
235 "gpio_17", NULL, "hsusb1_tll_data7", "hw_dbg5"),
236 _OMAP3_MUXENTRY(ETK_D4, 18,
237 "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
238 "gpio_18", NULL, "hsusb1_tll_data4", "hw_dbg6"),
239 _OMAP3_MUXENTRY(ETK_D5, 19,
240 "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
241 "gpio_19", NULL, "hsusb1_tll_data5", "hw_dbg7"),
242 _OMAP3_MUXENTRY(ETK_D6, 20,
243 "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
244 "gpio_20", NULL, "hsusb1_tll_data6", "hw_dbg8"),
245 _OMAP3_MUXENTRY(ETK_D7, 21,
246 "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
247 "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", "hw_dbg9"),
248 _OMAP3_MUXENTRY(ETK_D8, 22,
249 "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
250 "gpio_22", NULL, "hsusb1_tll_dir", "hw_dbg10"),
251 _OMAP3_MUXENTRY(ETK_D9, 23,
252 "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
253 "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", "hw_dbg11"),
254 _OMAP3_MUXENTRY(GPMC_A1, 34,
255 "gpmc_a1", NULL, NULL, NULL,
256 "gpio_34", NULL, NULL, "safe_mode"),
257 _OMAP3_MUXENTRY(GPMC_A10, 43,
258 "gpmc_a10", "sys_ndmareq3", NULL, NULL,
259 "gpio_43", NULL, NULL, "safe_mode"),
260 _OMAP3_MUXENTRY(GPMC_A2, 35,
261 "gpmc_a2", NULL, NULL, NULL,
262 "gpio_35", NULL, NULL, "safe_mode"),
263 _OMAP3_MUXENTRY(GPMC_A3, 36,
264 "gpmc_a3", NULL, NULL, NULL,
265 "gpio_36", NULL, NULL, "safe_mode"),
266 _OMAP3_MUXENTRY(GPMC_A4, 37,
267 "gpmc_a4", NULL, NULL, NULL,
268 "gpio_37", NULL, NULL, "safe_mode"),
269 _OMAP3_MUXENTRY(GPMC_A5, 38,
270 "gpmc_a5", NULL, NULL, NULL,
271 "gpio_38", NULL, NULL, "safe_mode"),
272 _OMAP3_MUXENTRY(GPMC_A6, 39,
273 "gpmc_a6", NULL, NULL, NULL,
274 "gpio_39", NULL, NULL, "safe_mode"),
275 _OMAP3_MUXENTRY(GPMC_A7, 40,
276 "gpmc_a7", NULL, NULL, NULL,
277 "gpio_40", NULL, NULL, "safe_mode"),
278 _OMAP3_MUXENTRY(GPMC_A8, 41,
279 "gpmc_a8", NULL, NULL, NULL,
280 "gpio_41", NULL, NULL, "safe_mode"),
281 _OMAP3_MUXENTRY(GPMC_A9, 42,
282 "gpmc_a9", "sys_ndmareq2", NULL, NULL,
283 "gpio_42", NULL, NULL, "safe_mode"),
284 _OMAP3_MUXENTRY(GPMC_CLK, 59,
285 "gpmc_clk", NULL, NULL, NULL,
286 "gpio_59", NULL, NULL, "safe_mode"),
287 _OMAP3_MUXENTRY(GPMC_D10, 46,
288 "gpmc_d10", NULL, NULL, NULL,
289 "gpio_46", NULL, NULL, "safe_mode"),
290 _OMAP3_MUXENTRY(GPMC_D11, 47,
291 "gpmc_d11", NULL, NULL, NULL,
292 "gpio_47", NULL, NULL, "safe_mode"),
293 _OMAP3_MUXENTRY(GPMC_D12, 48,
294 "gpmc_d12", NULL, NULL, NULL,
295 "gpio_48", NULL, NULL, "safe_mode"),
296 _OMAP3_MUXENTRY(GPMC_D13, 49,
297 "gpmc_d13", NULL, NULL, NULL,
298 "gpio_49", NULL, NULL, "safe_mode"),
299 _OMAP3_MUXENTRY(GPMC_D14, 50,
300 "gpmc_d14", NULL, NULL, NULL,
301 "gpio_50", NULL, NULL, "safe_mode"),
302 _OMAP3_MUXENTRY(GPMC_D15, 51,
303 "gpmc_d15", NULL, NULL, NULL,
304 "gpio_51", NULL, NULL, "safe_mode"),
305 _OMAP3_MUXENTRY(GPMC_D8, 44,
306 "gpmc_d8", NULL, NULL, NULL,
307 "gpio_44", NULL, NULL, "safe_mode"),
308 _OMAP3_MUXENTRY(GPMC_D9, 45,
309 "gpmc_d9", NULL, NULL, NULL,
310 "gpio_45", NULL, NULL, "safe_mode"),
311 _OMAP3_MUXENTRY(GPMC_NBE0_CLE, 60,
312 "gpmc_nbe0_cle", NULL, NULL, NULL,
313 "gpio_60", NULL, NULL, "safe_mode"),
314 _OMAP3_MUXENTRY(GPMC_NBE1, 61,
315 "gpmc_nbe1", NULL, NULL, NULL,
316 "gpio_61", NULL, NULL, "safe_mode"),
317 _OMAP3_MUXENTRY(GPMC_NCS1, 52,
318 "gpmc_ncs1", NULL, NULL, NULL,
319 "gpio_52", NULL, NULL, "safe_mode"),
320 _OMAP3_MUXENTRY(GPMC_NCS2, 53,
321 "gpmc_ncs2", NULL, NULL, NULL,
322 "gpio_53", NULL, NULL, "safe_mode"),
323 _OMAP3_MUXENTRY(GPMC_NCS3, 54,
324 "gpmc_ncs3", "sys_ndmareq0", NULL, NULL,
325 "gpio_54", NULL, NULL, "safe_mode"),
326 _OMAP3_MUXENTRY(GPMC_NCS4, 55,
327 "gpmc_ncs4", "sys_ndmareq1", "mcbsp4_clkx", "gpt9_pwm_evt",
328 "gpio_55", NULL, NULL, "safe_mode"),
329 _OMAP3_MUXENTRY(GPMC_NCS5, 56,
330 "gpmc_ncs5", "sys_ndmareq2", "mcbsp4_dr", "gpt10_pwm_evt",
331 "gpio_56", NULL, NULL, "safe_mode"),
332 _OMAP3_MUXENTRY(GPMC_NCS6, 57,
333 "gpmc_ncs6", "sys_ndmareq3", "mcbsp4_dx", "gpt11_pwm_evt",
334 "gpio_57", NULL, NULL, "safe_mode"),
335 _OMAP3_MUXENTRY(GPMC_NCS7, 58,
336 "gpmc_ncs7", "gpmc_io_dir", "mcbsp4_fsx", "gpt8_pwm_evt",
337 "gpio_58", NULL, NULL, "safe_mode"),
338 _OMAP3_MUXENTRY(GPMC_NWP, 62,
339 "gpmc_nwp", NULL, NULL, NULL,
340 "gpio_62", NULL, NULL, "safe_mode"),
341 _OMAP3_MUXENTRY(GPMC_WAIT1, 63,
342 "gpmc_wait1", NULL, NULL, NULL,
343 "gpio_63", NULL, NULL, "safe_mode"),
344 _OMAP3_MUXENTRY(GPMC_WAIT2, 64,
345 "gpmc_wait2", NULL, NULL, NULL,
346 "gpio_64", NULL, NULL, "safe_mode"),
347 _OMAP3_MUXENTRY(GPMC_WAIT3, 65,
348 "gpmc_wait3", "sys_ndmareq1", NULL, NULL,
349 "gpio_65", NULL, NULL, "safe_mode"),
350 _OMAP3_MUXENTRY(HDQ_SIO, 170,
351 "hdq_sio", "sys_altclk", "i2c2_sccbe", "i2c3_sccbe",
352 "gpio_170", NULL, NULL, "safe_mode"),
353 _OMAP3_MUXENTRY(HSUSB0_CLK, 120,
354 "hsusb0_clk", NULL, NULL, NULL,
355 "gpio_120", NULL, NULL, "safe_mode"),
356 _OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
357 "hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
358 "gpio_125", NULL, NULL, "safe_mode"),
359 _OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
360 "hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
361 "gpio_130", NULL, NULL, "safe_mode"),
362 _OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
363 "hsusb0_data2", NULL, "uart3_rts_sd", NULL,
364 "gpio_131", NULL, NULL, "safe_mode"),
365 _OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
366 "hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
367 "gpio_169", NULL, NULL, "safe_mode"),
368 _OMAP3_MUXENTRY(HSUSB0_DATA4, 188,
369 "hsusb0_data4", NULL, NULL, NULL,
370 "gpio_188", NULL, NULL, "safe_mode"),
371 _OMAP3_MUXENTRY(HSUSB0_DATA5, 189,
372 "hsusb0_data5", NULL, NULL, NULL,
373 "gpio_189", NULL, NULL, "safe_mode"),
374 _OMAP3_MUXENTRY(HSUSB0_DATA6, 190,
375 "hsusb0_data6", NULL, NULL, NULL,
376 "gpio_190", NULL, NULL, "safe_mode"),
377 _OMAP3_MUXENTRY(HSUSB0_DATA7, 191,
378 "hsusb0_data7", NULL, NULL, NULL,
379 "gpio_191", NULL, NULL, "safe_mode"),
380 _OMAP3_MUXENTRY(HSUSB0_DIR, 122,
381 "hsusb0_dir", NULL, NULL, NULL,
382 "gpio_122", NULL, NULL, "safe_mode"),
383 _OMAP3_MUXENTRY(HSUSB0_NXT, 124,
384 "hsusb0_nxt", NULL, NULL, NULL,
385 "gpio_124", NULL, NULL, "safe_mode"),
386 _OMAP3_MUXENTRY(HSUSB0_STP, 121,
387 "hsusb0_stp", NULL, NULL, NULL,
388 "gpio_121", NULL, NULL, "safe_mode"),
389 _OMAP3_MUXENTRY(I2C2_SCL, 168,
390 "i2c2_scl", NULL, NULL, NULL,
391 "gpio_168", NULL, NULL, "safe_mode"),
392 _OMAP3_MUXENTRY(I2C2_SDA, 183,
393 "i2c2_sda", NULL, NULL, NULL,
394 "gpio_183", NULL, NULL, "safe_mode"),
395 _OMAP3_MUXENTRY(I2C3_SCL, 184,
396 "i2c3_scl", NULL, NULL, NULL,
397 "gpio_184", NULL, NULL, "safe_mode"),
398 _OMAP3_MUXENTRY(I2C3_SDA, 185,
399 "i2c3_sda", NULL, NULL, NULL,
400 "gpio_185", NULL, NULL, "safe_mode"),
401 _OMAP3_MUXENTRY(I2C4_SCL, 0,
402 "i2c4_scl", "sys_nvmode1", NULL, NULL,
403 NULL, NULL, NULL, "safe_mode"),
404 _OMAP3_MUXENTRY(I2C4_SDA, 0,
405 "i2c4_sda", "sys_nvmode2", NULL, NULL,
406 NULL, NULL, NULL, "safe_mode"),
407 _OMAP3_MUXENTRY(JTAG_EMU0, 11,
408 "jtag_emu0", NULL, NULL, NULL,
409 "gpio_11", NULL, NULL, "safe_mode"),
410 _OMAP3_MUXENTRY(JTAG_EMU1, 31,
411 "jtag_emu1", NULL, NULL, NULL,
412 "gpio_31", NULL, NULL, "safe_mode"),
413 _OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
414 "mcbsp1_clkr", "mcspi4_clk", NULL, NULL,
415 "gpio_156", NULL, NULL, "safe_mode"),
416 _OMAP3_MUXENTRY(MCBSP1_CLKX, 162,
417 "mcbsp1_clkx", NULL, "mcbsp3_clkx", NULL,
418 "gpio_162", NULL, NULL, "safe_mode"),
419 _OMAP3_MUXENTRY(MCBSP1_DR, 159,
420 "mcbsp1_dr", "mcspi4_somi", "mcbsp3_dr", NULL,
421 "gpio_159", NULL, NULL, "safe_mode"),
422 _OMAP3_MUXENTRY(MCBSP1_DX, 158,
423 "mcbsp1_dx", "mcspi4_simo", "mcbsp3_dx", NULL,
424 "gpio_158", NULL, NULL, "safe_mode"),
425 _OMAP3_MUXENTRY(MCBSP1_FSR, 157,
426 "mcbsp1_fsr", NULL, "cam_global_reset", NULL,
427 "gpio_157", NULL, NULL, "safe_mode"),
428 _OMAP3_MUXENTRY(MCBSP1_FSX, 161,
429 "mcbsp1_fsx", "mcspi4_cs0", "mcbsp3_fsx", NULL,
430 "gpio_161", NULL, NULL, "safe_mode"),
431 _OMAP3_MUXENTRY(MCBSP2_CLKX, 117,
432 "mcbsp2_clkx", NULL, NULL, NULL,
433 "gpio_117", NULL, NULL, "safe_mode"),
434 _OMAP3_MUXENTRY(MCBSP2_DR, 118,
435 "mcbsp2_dr", NULL, NULL, NULL,
436 "gpio_118", NULL, NULL, "safe_mode"),
437 _OMAP3_MUXENTRY(MCBSP2_DX, 119,
438 "mcbsp2_dx", NULL, NULL, NULL,
439 "gpio_119", NULL, NULL, "safe_mode"),
440 _OMAP3_MUXENTRY(MCBSP2_FSX, 116,
441 "mcbsp2_fsx", NULL, NULL, NULL,
442 "gpio_116", NULL, NULL, "safe_mode"),
443 _OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
444 "mcbsp3_clkx", "uart2_tx", NULL, NULL,
445 "gpio_142", "hsusb3_tll_data6", NULL, "safe_mode"),
446 _OMAP3_MUXENTRY(MCBSP3_DR, 141,
447 "mcbsp3_dr", "uart2_rts", NULL, NULL,
448 "gpio_141", "hsusb3_tll_data5", NULL, "safe_mode"),
449 _OMAP3_MUXENTRY(MCBSP3_DX, 140,
450 "mcbsp3_dx", "uart2_cts", NULL, NULL,
451 "gpio_140", "hsusb3_tll_data4", NULL, "safe_mode"),
452 _OMAP3_MUXENTRY(MCBSP3_FSX, 143,
453 "mcbsp3_fsx", "uart2_rx", NULL, NULL,
454 "gpio_143", "hsusb3_tll_data7", NULL, "safe_mode"),
455 _OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
456 "mcbsp4_clkx", NULL, NULL, NULL,
457 "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
458 _OMAP3_MUXENTRY(MCBSP4_DR, 153,
459 "mcbsp4_dr", NULL, NULL, NULL,
460 "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
461 _OMAP3_MUXENTRY(MCBSP4_DX, 154,
462 "mcbsp4_dx", NULL, NULL, NULL,
463 "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
464 _OMAP3_MUXENTRY(MCBSP4_FSX, 155,
465 "mcbsp4_fsx", NULL, NULL, NULL,
466 "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
467 _OMAP3_MUXENTRY(MCBSP_CLKS, 160,
468 "mcbsp_clks", NULL, "cam_shutter", NULL,
469 "gpio_160", "uart1_cts", NULL, "safe_mode"),
470 _OMAP3_MUXENTRY(MCSPI1_CLK, 171,
471 "mcspi1_clk", "sdmmc2_dat4", NULL, NULL,
472 "gpio_171", NULL, NULL, "safe_mode"),
473 _OMAP3_MUXENTRY(MCSPI1_CS0, 174,
474 "mcspi1_cs0", "sdmmc2_dat7", NULL, NULL,
475 "gpio_174", NULL, NULL, "safe_mode"),
476 _OMAP3_MUXENTRY(MCSPI1_CS1, 175,
477 "mcspi1_cs1", NULL, NULL, "sdmmc3_cmd",
478 "gpio_175", NULL, NULL, "safe_mode"),
479 _OMAP3_MUXENTRY(MCSPI1_CS2, 176,
480 "mcspi1_cs2", NULL, NULL, "sdmmc3_clk",
481 "gpio_176", NULL, NULL, "safe_mode"),
482 _OMAP3_MUXENTRY(MCSPI1_CS3, 177,
483 "mcspi1_cs3", NULL, "hsusb2_tll_data2", "hsusb2_data2",
484 "gpio_177", "mm2_txdat", NULL, "safe_mode"),
485 _OMAP3_MUXENTRY(MCSPI1_SIMO, 172,
486 "mcspi1_simo", "sdmmc2_dat5", NULL, NULL,
487 "gpio_172", NULL, NULL, "safe_mode"),
488 _OMAP3_MUXENTRY(MCSPI1_SOMI, 173,
489 "mcspi1_somi", "sdmmc2_dat6", NULL, NULL,
490 "gpio_173", NULL, NULL, "safe_mode"),
491 _OMAP3_MUXENTRY(MCSPI2_CLK, 178,
492 "mcspi2_clk", NULL, "hsusb2_tll_data7", "hsusb2_data7",
493 "gpio_178", NULL, NULL, "safe_mode"),
494 _OMAP3_MUXENTRY(MCSPI2_CS0, 181,
495 "mcspi2_cs0", "gpt11_pwm_evt",
496 "hsusb2_tll_data6", "hsusb2_data6",
497 "gpio_181", NULL, NULL, "safe_mode"),
498 _OMAP3_MUXENTRY(MCSPI2_CS1, 182,
499 "mcspi2_cs1", "gpt8_pwm_evt",
500 "hsusb2_tll_data3", "hsusb2_data3",
501 "gpio_182", "mm2_txen_n", NULL, "safe_mode"),
502 _OMAP3_MUXENTRY(MCSPI2_SIMO, 179,
503 "mcspi2_simo", "gpt9_pwm_evt",
504 "hsusb2_tll_data4", "hsusb2_data4",
505 "gpio_179", NULL, NULL, "safe_mode"),
506 _OMAP3_MUXENTRY(MCSPI2_SOMI, 180,
507 "mcspi2_somi", "gpt10_pwm_evt",
508 "hsusb2_tll_data5", "hsusb2_data5",
509 "gpio_180", NULL, NULL, "safe_mode"),
510 _OMAP3_MUXENTRY(SDMMC1_CLK, 120,
511 "sdmmc1_clk", NULL, NULL, NULL,
512 "gpio_120", NULL, NULL, "safe_mode"),
513 _OMAP3_MUXENTRY(SDMMC1_CMD, 121,
514 "sdmmc1_cmd", NULL, NULL, NULL,
515 "gpio_121", NULL, NULL, "safe_mode"),
516 _OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
517 "sdmmc1_dat0", NULL, NULL, NULL,
518 "gpio_122", NULL, NULL, "safe_mode"),
519 _OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
520 "sdmmc1_dat1", NULL, NULL, NULL,
521 "gpio_123", NULL, NULL, "safe_mode"),
522 _OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
523 "sdmmc1_dat2", NULL, NULL, NULL,
524 "gpio_124", NULL, NULL, "safe_mode"),
525 _OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
526 "sdmmc1_dat3", NULL, NULL, NULL,
527 "gpio_125", NULL, NULL, "safe_mode"),
528 _OMAP3_MUXENTRY(SDMMC1_DAT4, 126,
529 "sdmmc1_dat4", NULL, "sim_io", NULL,
530 "gpio_126", NULL, NULL, "safe_mode"),
531 _OMAP3_MUXENTRY(SDMMC1_DAT5, 127,
532 "sdmmc1_dat5", NULL, "sim_clk", NULL,
533 "gpio_127", NULL, NULL, "safe_mode"),
534 _OMAP3_MUXENTRY(SDMMC1_DAT6, 128,
535 "sdmmc1_dat6", NULL, "sim_pwrctrl", NULL,
536 "gpio_128", NULL, NULL, "safe_mode"),
537 _OMAP3_MUXENTRY(SDMMC1_DAT7, 129,
538 "sdmmc1_dat7", NULL, "sim_rst", NULL,
539 "gpio_129", NULL, NULL, "safe_mode"),
540 _OMAP3_MUXENTRY(SDMMC2_CLK, 130,
541 "sdmmc2_clk", "mcspi3_clk", NULL, NULL,
542 "gpio_130", NULL, NULL, "safe_mode"),
543 _OMAP3_MUXENTRY(SDMMC2_CMD, 131,
544 "sdmmc2_cmd", "mcspi3_simo", NULL, NULL,
545 "gpio_131", NULL, NULL, "safe_mode"),
546 _OMAP3_MUXENTRY(SDMMC2_DAT0, 132,
547 "sdmmc2_dat0", "mcspi3_somi", NULL, NULL,
548 "gpio_132", NULL, NULL, "safe_mode"),
549 _OMAP3_MUXENTRY(SDMMC2_DAT1, 133,
550 "sdmmc2_dat1", NULL, NULL, NULL,
551 "gpio_133", NULL, NULL, "safe_mode"),
552 _OMAP3_MUXENTRY(SDMMC2_DAT2, 134,
553 "sdmmc2_dat2", "mcspi3_cs1", NULL, NULL,
554 "gpio_134", NULL, NULL, "safe_mode"),
555 _OMAP3_MUXENTRY(SDMMC2_DAT3, 135,
556 "sdmmc2_dat3", "mcspi3_cs0", NULL, NULL,
557 "gpio_135", NULL, NULL, "safe_mode"),
558 _OMAP3_MUXENTRY(SDMMC2_DAT4, 136,
559 "sdmmc2_dat4", "sdmmc2_dir_dat0", NULL, "sdmmc3_dat0",
560 "gpio_136", NULL, NULL, "safe_mode"),
561 _OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
562 "sdmmc2_dat5", "sdmmc2_dir_dat1",
563 "cam_global_reset", "sdmmc3_dat1",
564 "gpio_137", "hsusb3_tll_stp", "mm3_rxdp", "safe_mode"),
565 _OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
566 "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
567 "gpio_138", "hsusb3_tll_dir", NULL, "safe_mode"),
568 _OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
569 "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
570 "gpio_139", "hsusb3_tll_nxt", "mm3_rxdm", "safe_mode"),
571 _OMAP3_MUXENTRY(SDRC_CKE0, 0,
572 "sdrc_cke0", NULL, NULL, NULL,
573 NULL, NULL, NULL, "safe_mode"),
574 _OMAP3_MUXENTRY(SDRC_CKE1, 0,
575 "sdrc_cke1", NULL, NULL, NULL,
576 NULL, NULL, NULL, "safe_mode"),
577 _OMAP3_MUXENTRY(SYS_BOOT0, 2,
578 "sys_boot0", NULL, NULL, NULL,
579 "gpio_2", NULL, NULL, "safe_mode"),
580 _OMAP3_MUXENTRY(SYS_BOOT1, 3,
581 "sys_boot1", NULL, NULL, NULL,
582 "gpio_3", NULL, NULL, "safe_mode"),
583 _OMAP3_MUXENTRY(SYS_BOOT2, 4,
584 "sys_boot2", NULL, NULL, NULL,
585 "gpio_4", NULL, NULL, "safe_mode"),
586 _OMAP3_MUXENTRY(SYS_BOOT3, 5,
587 "sys_boot3", NULL, NULL, NULL,
588 "gpio_5", NULL, NULL, "safe_mode"),
589 _OMAP3_MUXENTRY(SYS_BOOT4, 6,
590 "sys_boot4", "sdmmc2_dir_dat2", NULL, NULL,
591 "gpio_6", NULL, NULL, "safe_mode"),
592 _OMAP3_MUXENTRY(SYS_BOOT5, 7,
593 "sys_boot5", "sdmmc2_dir_dat3", NULL, NULL,
594 "gpio_7", NULL, NULL, "safe_mode"),
595 _OMAP3_MUXENTRY(SYS_BOOT6, 8,
596 "sys_boot6", NULL, NULL, NULL,
597 "gpio_8", NULL, NULL, "safe_mode"),
598 _OMAP3_MUXENTRY(SYS_CLKOUT1, 10,
599 "sys_clkout1", NULL, NULL, NULL,
600 "gpio_10", NULL, NULL, "safe_mode"),
601 _OMAP3_MUXENTRY(SYS_CLKOUT2, 186,
602 "sys_clkout2", NULL, NULL, NULL,
603 "gpio_186", NULL, NULL, "safe_mode"),
604 _OMAP3_MUXENTRY(SYS_CLKREQ, 1,
605 "sys_clkreq", NULL, NULL, NULL,
606 "gpio_1", NULL, NULL, "safe_mode"),
607 _OMAP3_MUXENTRY(SYS_NIRQ, 0,
608 "sys_nirq", NULL, NULL, NULL,
609 "gpio_0", NULL, NULL, "safe_mode"),
610 _OMAP3_MUXENTRY(SYS_NRESWARM, 30,
611 "sys_nreswarm", NULL, NULL, NULL,
612 "gpio_30", NULL, NULL, "safe_mode"),
613 _OMAP3_MUXENTRY(SYS_OFF_MODE, 9,
614 "sys_off_mode", NULL, NULL, NULL,
615 "gpio_9", NULL, NULL, "safe_mode"),
616 _OMAP3_MUXENTRY(UART1_CTS, 150,
617 "uart1_cts", "ssi1_rdy_tx", NULL, NULL,
618 "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
619 _OMAP3_MUXENTRY(UART1_RTS, 149,
620 "uart1_rts", "ssi1_flag_tx", NULL, NULL,
621 "gpio_149", NULL, NULL, "safe_mode"),
622 _OMAP3_MUXENTRY(UART1_RX, 151,
623 "uart1_rx", "ssi1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",
624 "gpio_151", NULL, NULL, "safe_mode"),
625 _OMAP3_MUXENTRY(UART1_TX, 148,
626 "uart1_tx", "ssi1_dat_tx", NULL, NULL,
627 "gpio_148", NULL, NULL, "safe_mode"),
628 _OMAP3_MUXENTRY(UART2_CTS, 144,
629 "uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL,
630 "gpio_144", NULL, NULL, "safe_mode"),
631 _OMAP3_MUXENTRY(UART2_RTS, 145,
632 "uart2_rts", "mcbsp3_dr", "gpt10_pwm_evt", NULL,
633 "gpio_145", NULL, NULL, "safe_mode"),
634 _OMAP3_MUXENTRY(UART2_RX, 147,
635 "uart2_rx", "mcbsp3_fsx", "gpt8_pwm_evt", NULL,
636 "gpio_147", NULL, NULL, "safe_mode"),
637 _OMAP3_MUXENTRY(UART2_TX, 146,
638 "uart2_tx", "mcbsp3_clkx", "gpt11_pwm_evt", NULL,
639 "gpio_146", NULL, NULL, "safe_mode"),
640 _OMAP3_MUXENTRY(UART3_CTS_RCTX, 163,
641 "uart3_cts_rctx", NULL, NULL, NULL,
642 "gpio_163", NULL, NULL, "safe_mode"),
643 _OMAP3_MUXENTRY(UART3_RTS_SD, 164,
644 "uart3_rts_sd", NULL, NULL, NULL,
645 "gpio_164", NULL, NULL, "safe_mode"),
646 _OMAP3_MUXENTRY(UART3_RX_IRRX, 165,
647 "uart3_rx_irrx", NULL, NULL, NULL,
648 "gpio_165", NULL, NULL, "safe_mode"),
649 _OMAP3_MUXENTRY(UART3_TX_IRTX, 166,
650 "uart3_tx_irtx", NULL, NULL, NULL,
651 "gpio_166", NULL, NULL, "safe_mode"),
652
653 /* Only on 3630, see omap36xx_cbp_subset for the signals */
654 _OMAP3_MUXENTRY(GPMC_A11, 0,
655 NULL, NULL, NULL, NULL,
656 NULL, NULL, NULL, NULL),
657 _OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
658 NULL, NULL, NULL, NULL,
659 NULL, NULL, NULL, NULL),
660 _OMAP3_MUXENTRY(SAD2D_MREAD, 0,
661 NULL, NULL, NULL, NULL,
662 NULL, NULL, NULL, NULL),
663 _OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
664 NULL, NULL, NULL, NULL,
665 NULL, NULL, NULL, NULL),
666 _OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
667 NULL, NULL, NULL, NULL,
668 NULL, NULL, NULL, NULL),
669 _OMAP3_MUXENTRY(SAD2D_SREAD, 0,
670 NULL, NULL, NULL, NULL,
671 NULL, NULL, NULL, NULL),
672 _OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
673 NULL, NULL, NULL, NULL,
674 NULL, NULL, NULL, NULL),
675 _OMAP3_MUXENTRY(GPMC_A11, 0,
676 NULL, NULL, NULL, NULL,
677 NULL, NULL, NULL, NULL),
678 _OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
679 NULL, NULL, NULL, NULL,
680 NULL, NULL, NULL, NULL),
681 _OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
682 NULL, NULL, NULL, NULL,
683 NULL, NULL, NULL, NULL),
684 _OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
685 NULL, NULL, NULL, NULL,
686 NULL, NULL, NULL, NULL),
687 _OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
688 NULL, NULL, NULL, NULL,
689 NULL, NULL, NULL, NULL),
690 _OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
691 NULL, NULL, NULL, NULL,
692 NULL, NULL, NULL, NULL),
693 _OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
694 NULL, NULL, NULL, NULL,
695 NULL, NULL, NULL, NULL),
696 _OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
697 NULL, NULL, NULL, NULL,
698 NULL, NULL, NULL, NULL),
699 { .reg_offset = OMAP_MUX_TERMINATOR },
700};
701
702/*
703 * Signals different on CBC package compared to the superset
704 */
705#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBC)
706static struct omap_mux __initdata omap3_cbc_subset[] = {
707 { .reg_offset = OMAP_MUX_TERMINATOR },
708};
709#else
710#define omap3_cbc_subset NULL
711#endif
712
713/*
714 * Balls for CBC package
715 * 515-pin s-PBGA Package, 0.65mm Ball Pitch (Top), 0.50mm Ball Pitch (Bottom)
716 *
717 * FIXME: What's up with the outdated TI documentation? See:
718 *
719 * http://wiki.davincidsp.com/index.php/Datasheet_Errata_for_OMAP35x_CBC_Package
720 * http://community.ti.com/forums/t/10982.aspx
721 */
722#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
723 && defined(CONFIG_OMAP_PACKAGE_CBC)
724static struct omap_ball __initdata omap3_cbc_ball[] = {
725 _OMAP3_BALLENTRY(CAM_D0, "ae16", NULL),
726 _OMAP3_BALLENTRY(CAM_D1, "ae15", NULL),
727 _OMAP3_BALLENTRY(CAM_D10, "d25", NULL),
728 _OMAP3_BALLENTRY(CAM_D11, "e26", NULL),
729 _OMAP3_BALLENTRY(CAM_D2, "a24", NULL),
730 _OMAP3_BALLENTRY(CAM_D3, "b24", NULL),
731 _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
732 _OMAP3_BALLENTRY(CAM_D5, "c24", NULL),
733 _OMAP3_BALLENTRY(CAM_D6, "p25", NULL),
734 _OMAP3_BALLENTRY(CAM_D7, "p26", NULL),
735 _OMAP3_BALLENTRY(CAM_D8, "n25", NULL),
736 _OMAP3_BALLENTRY(CAM_D9, "n26", NULL),
737 _OMAP3_BALLENTRY(CAM_FLD, "b23", NULL),
738 _OMAP3_BALLENTRY(CAM_HS, "c23", NULL),
739 _OMAP3_BALLENTRY(CAM_PCLK, "c26", NULL),
740 _OMAP3_BALLENTRY(CAM_STROBE, "d26", NULL),
741 _OMAP3_BALLENTRY(CAM_VS, "d23", NULL),
742 _OMAP3_BALLENTRY(CAM_WEN, "a23", NULL),
743 _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
744 _OMAP3_BALLENTRY(CAM_XCLKB, "e25", NULL),
745 _OMAP3_BALLENTRY(CSI2_DX0, "ad17", NULL),
746 _OMAP3_BALLENTRY(CSI2_DX1, "ae18", NULL),
747 _OMAP3_BALLENTRY(CSI2_DY0, "ad16", NULL),
748 _OMAP3_BALLENTRY(CSI2_DY1, "ae17", NULL),
749 _OMAP3_BALLENTRY(DSS_ACBIAS, "f26", NULL),
750 _OMAP3_BALLENTRY(DSS_DATA0, "ae21", NULL),
751 _OMAP3_BALLENTRY(DSS_DATA1, "ae22", NULL),
752 _OMAP3_BALLENTRY(DSS_DATA10, "ac26", NULL),
753 _OMAP3_BALLENTRY(DSS_DATA11, "ad26", NULL),
754 _OMAP3_BALLENTRY(DSS_DATA12, "aa25", NULL),
755 _OMAP3_BALLENTRY(DSS_DATA13, "y25", NULL),
756 _OMAP3_BALLENTRY(DSS_DATA14, "aa26", NULL),
757 _OMAP3_BALLENTRY(DSS_DATA15, "ab26", NULL),
758 _OMAP3_BALLENTRY(DSS_DATA16, "l25", NULL),
759 _OMAP3_BALLENTRY(DSS_DATA17, "l26", NULL),
760 _OMAP3_BALLENTRY(DSS_DATA18, "m24", NULL),
761 _OMAP3_BALLENTRY(DSS_DATA19, "m26", NULL),
762 _OMAP3_BALLENTRY(DSS_DATA2, "ae23", NULL),
763 _OMAP3_BALLENTRY(DSS_DATA20, "f25", NULL),
764 _OMAP3_BALLENTRY(DSS_DATA21, "n24", NULL),
765 _OMAP3_BALLENTRY(DSS_DATA22, "ac25", NULL),
766 _OMAP3_BALLENTRY(DSS_DATA23, "ab25", NULL),
767 _OMAP3_BALLENTRY(DSS_DATA3, "ae24", NULL),
768 _OMAP3_BALLENTRY(DSS_DATA4, "ad23", NULL),
769 _OMAP3_BALLENTRY(DSS_DATA5, "ad24", NULL),
770 _OMAP3_BALLENTRY(DSS_DATA6, "g26", NULL),
771 _OMAP3_BALLENTRY(DSS_DATA7, "h25", NULL),
772 _OMAP3_BALLENTRY(DSS_DATA8, "h26", NULL),
773 _OMAP3_BALLENTRY(DSS_DATA9, "j26", NULL),
774 _OMAP3_BALLENTRY(DSS_HSYNC, "k24", NULL),
775 _OMAP3_BALLENTRY(DSS_PCLK, "g25", NULL),
776 _OMAP3_BALLENTRY(DSS_VSYNC, "m25", NULL),
777 _OMAP3_BALLENTRY(ETK_CLK, "ab2", NULL),
778 _OMAP3_BALLENTRY(ETK_CTL, "ab3", NULL),
779 _OMAP3_BALLENTRY(ETK_D0, "ac3", NULL),
780 _OMAP3_BALLENTRY(ETK_D1, "ad4", NULL),
781 _OMAP3_BALLENTRY(ETK_D10, "ae4", NULL),
782 _OMAP3_BALLENTRY(ETK_D11, "af6", NULL),
783 _OMAP3_BALLENTRY(ETK_D12, "ae6", NULL),
784 _OMAP3_BALLENTRY(ETK_D13, "af7", NULL),
785 _OMAP3_BALLENTRY(ETK_D14, "af9", NULL),
786 _OMAP3_BALLENTRY(ETK_D15, "ae9", NULL),
787 _OMAP3_BALLENTRY(ETK_D2, "ad3", NULL),
788 _OMAP3_BALLENTRY(ETK_D3, "aa3", NULL),
789 _OMAP3_BALLENTRY(ETK_D4, "y3", NULL),
790 _OMAP3_BALLENTRY(ETK_D5, "ab1", NULL),
791 _OMAP3_BALLENTRY(ETK_D6, "ae3", NULL),
792 _OMAP3_BALLENTRY(ETK_D7, "ad2", NULL),
793 _OMAP3_BALLENTRY(ETK_D8, "aa4", NULL),
794 _OMAP3_BALLENTRY(ETK_D9, "v2", NULL),
795 _OMAP3_BALLENTRY(GPMC_A1, "j2", NULL),
796 _OMAP3_BALLENTRY(GPMC_A10, "d2", NULL),
797 _OMAP3_BALLENTRY(GPMC_A2, "h1", NULL),
798 _OMAP3_BALLENTRY(GPMC_A3, "h2", NULL),
799 _OMAP3_BALLENTRY(GPMC_A4, "g2", NULL),
800 _OMAP3_BALLENTRY(GPMC_A5, "f1", NULL),
801 _OMAP3_BALLENTRY(GPMC_A6, "f2", NULL),
802 _OMAP3_BALLENTRY(GPMC_A7, "e1", NULL),
803 _OMAP3_BALLENTRY(GPMC_A8, "e2", NULL),
804 _OMAP3_BALLENTRY(GPMC_A9, "d1", NULL),
805 _OMAP3_BALLENTRY(GPMC_CLK, "n1", "l1"),
806 _OMAP3_BALLENTRY(GPMC_D10, "t1", "n1"),
807 _OMAP3_BALLENTRY(GPMC_D11, "u2", "p2"),
808 _OMAP3_BALLENTRY(GPMC_D12, "u1", "p1"),
809 _OMAP3_BALLENTRY(GPMC_D13, "p1", "m1"),
810 _OMAP3_BALLENTRY(GPMC_D14, "l2", "j2"),
811 _OMAP3_BALLENTRY(GPMC_D15, "m2", "k2"),
812 _OMAP3_BALLENTRY(GPMC_D8, "v1", "r1"),
813 _OMAP3_BALLENTRY(GPMC_D9, "y1", "t1"),
814 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k2", NULL),
815 _OMAP3_BALLENTRY(GPMC_NBE1, "j1", NULL),
816 _OMAP3_BALLENTRY(GPMC_NCS1, "ad1", "w1"),
817 _OMAP3_BALLENTRY(GPMC_NCS2, "a3", NULL),
818 _OMAP3_BALLENTRY(GPMC_NCS3, "b6", NULL),
819 _OMAP3_BALLENTRY(GPMC_NCS4, "b4", NULL),
820 _OMAP3_BALLENTRY(GPMC_NCS5, "c4", NULL),
821 _OMAP3_BALLENTRY(GPMC_NCS6, "b5", NULL),
822 _OMAP3_BALLENTRY(GPMC_NCS7, "c5", NULL),
823 _OMAP3_BALLENTRY(GPMC_NWP, "ac6", "y5"),
824 _OMAP3_BALLENTRY(GPMC_WAIT1, "ac8", "y8"),
825 _OMAP3_BALLENTRY(GPMC_WAIT2, "b3", NULL),
826 _OMAP3_BALLENTRY(GPMC_WAIT3, "c6", NULL),
827 _OMAP3_BALLENTRY(HDQ_SIO, "j23", NULL),
828 _OMAP3_BALLENTRY(HSUSB0_CLK, "w19", NULL),
829 _OMAP3_BALLENTRY(HSUSB0_DATA0, "v20", NULL),
830 _OMAP3_BALLENTRY(HSUSB0_DATA1, "y20", NULL),
831 _OMAP3_BALLENTRY(HSUSB0_DATA2, "v18", NULL),
832 _OMAP3_BALLENTRY(HSUSB0_DATA3, "w20", NULL),
833 _OMAP3_BALLENTRY(HSUSB0_DATA4, "w17", NULL),
834 _OMAP3_BALLENTRY(HSUSB0_DATA5, "y18", NULL),
835 _OMAP3_BALLENTRY(HSUSB0_DATA6, "y19", NULL),
836 _OMAP3_BALLENTRY(HSUSB0_DATA7, "y17", NULL),
837 _OMAP3_BALLENTRY(HSUSB0_DIR, "v19", NULL),
838 _OMAP3_BALLENTRY(HSUSB0_NXT, "w18", NULL),
839 _OMAP3_BALLENTRY(HSUSB0_STP, "u20", NULL),
840 _OMAP3_BALLENTRY(I2C2_SCL, "c2", NULL),
841 _OMAP3_BALLENTRY(I2C2_SDA, "c1", NULL),
842 _OMAP3_BALLENTRY(I2C3_SCL, "ab4", NULL),
843 _OMAP3_BALLENTRY(I2C3_SDA, "ac4", NULL),
844 _OMAP3_BALLENTRY(I2C4_SCL, "ad15", NULL),
845 _OMAP3_BALLENTRY(I2C4_SDA, "w16", NULL),
846 _OMAP3_BALLENTRY(JTAG_EMU0, "y15", NULL),
847 _OMAP3_BALLENTRY(JTAG_EMU1, "y14", NULL),
848 _OMAP3_BALLENTRY(MCBSP1_CLKR, "u19", NULL),
849 _OMAP3_BALLENTRY(MCBSP1_CLKX, "t17", NULL),
850 _OMAP3_BALLENTRY(MCBSP1_DR, "t20", NULL),
851 _OMAP3_BALLENTRY(MCBSP1_DX, "u17", NULL),
852 _OMAP3_BALLENTRY(MCBSP1_FSR, "v17", NULL),
853 _OMAP3_BALLENTRY(MCBSP1_FSX, "p20", NULL),
854 _OMAP3_BALLENTRY(MCBSP2_CLKX, "r18", NULL),
855 _OMAP3_BALLENTRY(MCBSP2_DR, "t18", NULL),
856 _OMAP3_BALLENTRY(MCBSP2_DX, "r19", NULL),
857 _OMAP3_BALLENTRY(MCBSP2_FSX, "u18", NULL),
858 _OMAP3_BALLENTRY(MCBSP3_CLKX, "u3", NULL),
859 _OMAP3_BALLENTRY(MCBSP3_DR, "n3", NULL),
860 _OMAP3_BALLENTRY(MCBSP3_DX, "p3", NULL),
861 _OMAP3_BALLENTRY(MCBSP3_FSX, "w3", NULL),
862 _OMAP3_BALLENTRY(MCBSP4_CLKX, "v3", NULL),
863 _OMAP3_BALLENTRY(MCBSP4_DR, "u4", NULL),
864 _OMAP3_BALLENTRY(MCBSP4_DX, "r3", NULL),
865 _OMAP3_BALLENTRY(MCBSP4_FSX, "t3", NULL),
866 _OMAP3_BALLENTRY(MCBSP_CLKS, "t19", NULL),
867 _OMAP3_BALLENTRY(MCSPI1_CLK, "p9", NULL),
868 _OMAP3_BALLENTRY(MCSPI1_CS0, "r7", NULL),
869 _OMAP3_BALLENTRY(MCSPI1_CS1, "r8", NULL),
870 _OMAP3_BALLENTRY(MCSPI1_CS2, "r9", NULL),
871 _OMAP3_BALLENTRY(MCSPI1_CS3, "t8", NULL),
872 _OMAP3_BALLENTRY(MCSPI1_SIMO, "p8", NULL),
873 _OMAP3_BALLENTRY(MCSPI1_SOMI, "p7", NULL),
874 _OMAP3_BALLENTRY(MCSPI2_CLK, "w7", NULL),
875 _OMAP3_BALLENTRY(MCSPI2_CS0, "v8", NULL),
876 _OMAP3_BALLENTRY(MCSPI2_CS1, "v9", NULL),
877 _OMAP3_BALLENTRY(MCSPI2_SIMO, "w8", NULL),
878 _OMAP3_BALLENTRY(MCSPI2_SOMI, "u8", NULL),
879 _OMAP3_BALLENTRY(SDMMC1_CLK, "n19", NULL),
880 _OMAP3_BALLENTRY(SDMMC1_CMD, "l18", NULL),
881 _OMAP3_BALLENTRY(SDMMC1_DAT0, "m19", NULL),
882 _OMAP3_BALLENTRY(SDMMC1_DAT1, "m18", NULL),
883 _OMAP3_BALLENTRY(SDMMC1_DAT2, "k18", NULL),
884 _OMAP3_BALLENTRY(SDMMC1_DAT3, "n20", NULL),
885 _OMAP3_BALLENTRY(SDMMC1_DAT4, "m20", NULL),
886 _OMAP3_BALLENTRY(SDMMC1_DAT5, "p17", NULL),
887 _OMAP3_BALLENTRY(SDMMC1_DAT6, "p18", NULL),
888 _OMAP3_BALLENTRY(SDMMC1_DAT7, "p19", NULL),
889 _OMAP3_BALLENTRY(SDMMC2_CLK, "w10", NULL),
890 _OMAP3_BALLENTRY(SDMMC2_CMD, "r10", NULL),
891 _OMAP3_BALLENTRY(SDMMC2_DAT0, "t10", NULL),
892 _OMAP3_BALLENTRY(SDMMC2_DAT1, "t9", NULL),
893 _OMAP3_BALLENTRY(SDMMC2_DAT2, "u10", NULL),
894 _OMAP3_BALLENTRY(SDMMC2_DAT3, "u9", NULL),
895 _OMAP3_BALLENTRY(SDMMC2_DAT4, "v10", NULL),
896 _OMAP3_BALLENTRY(SDMMC2_DAT5, "m3", NULL),
897 _OMAP3_BALLENTRY(SDMMC2_DAT6, "l3", NULL),
898 _OMAP3_BALLENTRY(SDMMC2_DAT7, "k3", NULL),
899 _OMAP3_BALLENTRY(SYS_BOOT0, "f3", NULL),
900 _OMAP3_BALLENTRY(SYS_BOOT1, "d3", NULL),
901 _OMAP3_BALLENTRY(SYS_BOOT2, "c3", NULL),
902 _OMAP3_BALLENTRY(SYS_BOOT3, "e3", NULL),
903 _OMAP3_BALLENTRY(SYS_BOOT4, "e4", NULL),
904 _OMAP3_BALLENTRY(SYS_BOOT5, "g3", NULL),
905 _OMAP3_BALLENTRY(SYS_BOOT6, "d4", NULL),
906 _OMAP3_BALLENTRY(SYS_CLKOUT1, "ae14", NULL),
907 _OMAP3_BALLENTRY(SYS_CLKOUT2, "w11", NULL),
908 _OMAP3_BALLENTRY(SYS_CLKREQ, "w15", NULL),
909 _OMAP3_BALLENTRY(SYS_NIRQ, "v16", NULL),
910 _OMAP3_BALLENTRY(SYS_NRESWARM, "ad7", "aa5"),
911 _OMAP3_BALLENTRY(SYS_OFF_MODE, "v12", NULL),
912 _OMAP3_BALLENTRY(UART1_CTS, "w2", NULL),
913 _OMAP3_BALLENTRY(UART1_RTS, "r2", NULL),
914 _OMAP3_BALLENTRY(UART1_RX, "h3", NULL),
915 _OMAP3_BALLENTRY(UART1_TX, "l4", NULL),
916 _OMAP3_BALLENTRY(UART2_CTS, "y24", NULL),
917 _OMAP3_BALLENTRY(UART2_RTS, "aa24", NULL),
918 _OMAP3_BALLENTRY(UART2_RX, "ad21", NULL),
919 _OMAP3_BALLENTRY(UART2_TX, "ad22", NULL),
920 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "f23", NULL),
921 _OMAP3_BALLENTRY(UART3_RTS_SD, "f24", NULL),
922 _OMAP3_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
923 _OMAP3_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
924 { .reg_offset = OMAP_MUX_TERMINATOR },
925};
926#else
927#define omap3_cbc_ball NULL
928#endif
929
930/*
931 * Signals different on CUS package compared to superset
932 */
933#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS)
934static struct omap_mux __initdata omap3_cus_subset[] = {
935 _OMAP3_MUXENTRY(CAM_D10, 109,
936 "cam_d10", NULL, NULL, NULL,
937 "gpio_109", NULL, NULL, "safe_mode"),
938 _OMAP3_MUXENTRY(CAM_D11, 110,
939 "cam_d11", NULL, NULL, NULL,
940 "gpio_110", NULL, NULL, "safe_mode"),
941 _OMAP3_MUXENTRY(CAM_D2, 101,
942 "cam_d2", NULL, NULL, NULL,
943 "gpio_101", NULL, NULL, "safe_mode"),
944 _OMAP3_MUXENTRY(CAM_D3, 102,
945 "cam_d3", NULL, NULL, NULL,
946 "gpio_102", NULL, NULL, "safe_mode"),
947 _OMAP3_MUXENTRY(CAM_D4, 103,
948 "cam_d4", NULL, NULL, NULL,
949 "gpio_103", NULL, NULL, "safe_mode"),
950 _OMAP3_MUXENTRY(CAM_D5, 104,
951 "cam_d5", NULL, NULL, NULL,
952 "gpio_104", NULL, NULL, "safe_mode"),
953 _OMAP3_MUXENTRY(CAM_FLD, 98,
954 "cam_fld", NULL, "cam_global_reset", NULL,
955 "gpio_98", NULL, NULL, "safe_mode"),
956 _OMAP3_MUXENTRY(CAM_HS, 94,
957 "cam_hs", NULL, NULL, NULL,
958 "gpio_94", NULL, NULL, "safe_mode"),
959 _OMAP3_MUXENTRY(CAM_PCLK, 97,
960 "cam_pclk", NULL, NULL, NULL,
961 "gpio_97", NULL, NULL, "safe_mode"),
962 _OMAP3_MUXENTRY(CAM_STROBE, 126,
963 "cam_strobe", NULL, NULL, NULL,
964 "gpio_126", NULL, NULL, "safe_mode"),
965 _OMAP3_MUXENTRY(CAM_VS, 95,
966 "cam_vs", NULL, NULL, NULL,
967 "gpio_95", NULL, NULL, "safe_mode"),
968 _OMAP3_MUXENTRY(CAM_WEN, 167,
969 "cam_wen", NULL, "cam_shutter", NULL,
970 "gpio_167", NULL, NULL, "safe_mode"),
971 _OMAP3_MUXENTRY(DSS_DATA6, 76,
972 "dss_data6", NULL, "uart1_tx", NULL,
973 "gpio_76", NULL, NULL, "safe_mode"),
974 _OMAP3_MUXENTRY(DSS_DATA7, 77,
975 "dss_data7", NULL, "uart1_rx", NULL,
976 "gpio_77", NULL, NULL, "safe_mode"),
977 _OMAP3_MUXENTRY(DSS_DATA8, 78,
978 "dss_data8", NULL, NULL, NULL,
979 "gpio_78", NULL, NULL, "safe_mode"),
980 _OMAP3_MUXENTRY(DSS_DATA9, 79,
981 "dss_data9", NULL, NULL, NULL,
982 "gpio_79", NULL, NULL, "safe_mode"),
983 _OMAP3_MUXENTRY(DSS_HSYNC, 67,
984 "dss_hsync", NULL, NULL, NULL,
985 "gpio_67", NULL, NULL, "safe_mode"),
986 _OMAP3_MUXENTRY(DSS_PCLK, 66,
987 "dss_pclk", NULL, NULL, NULL,
988 "gpio_66", NULL, NULL, "safe_mode"),
989 _OMAP3_MUXENTRY(ETK_CLK, 12,
990 "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
991 "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
992 _OMAP3_MUXENTRY(ETK_CTL, 13,
993 "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
994 "gpio_13", NULL, "hsusb1_tll_clk", NULL),
995 _OMAP3_MUXENTRY(ETK_D0, 14,
996 "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
997 "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
998 _OMAP3_MUXENTRY(ETK_D1, 15,
999 "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
1000 "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
1001 _OMAP3_MUXENTRY(ETK_D10, 24,
1002 "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
1003 "gpio_24", NULL, "hsusb2_tll_clk", NULL),
1004 _OMAP3_MUXENTRY(ETK_D11, 25,
1005 "etk_d11", NULL, NULL, "hsusb2_stp",
1006 "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
1007 _OMAP3_MUXENTRY(ETK_D12, 26,
1008 "etk_d12", NULL, NULL, "hsusb2_dir",
1009 "gpio_26", NULL, "hsusb2_tll_dir", NULL),
1010 _OMAP3_MUXENTRY(ETK_D13, 27,
1011 "etk_d13", NULL, NULL, "hsusb2_nxt",
1012 "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
1013 _OMAP3_MUXENTRY(ETK_D14, 28,
1014 "etk_d14", NULL, NULL, "hsusb2_data0",
1015 "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
1016 _OMAP3_MUXENTRY(ETK_D15, 29,
1017 "etk_d15", NULL, NULL, "hsusb2_data1",
1018 "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
1019 _OMAP3_MUXENTRY(ETK_D2, 16,
1020 "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
1021 "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
1022 _OMAP3_MUXENTRY(ETK_D3, 17,
1023 "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
1024 "gpio_17", NULL, "hsusb1_tll_data7", NULL),
1025 _OMAP3_MUXENTRY(ETK_D4, 18,
1026 "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
1027 "gpio_18", NULL, "hsusb1_tll_data4", NULL),
1028 _OMAP3_MUXENTRY(ETK_D5, 19,
1029 "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
1030 "gpio_19", NULL, "hsusb1_tll_data5", NULL),
1031 _OMAP3_MUXENTRY(ETK_D6, 20,
1032 "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
1033 "gpio_20", NULL, "hsusb1_tll_data6", NULL),
1034 _OMAP3_MUXENTRY(ETK_D7, 21,
1035 "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
1036 "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
1037 _OMAP3_MUXENTRY(ETK_D8, 22,
1038 "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
1039 "gpio_22", NULL, "hsusb1_tll_dir", NULL),
1040 _OMAP3_MUXENTRY(ETK_D9, 23,
1041 "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
1042 "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
1043 _OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
1044 "mcbsp3_clkx", "uart2_tx", NULL, NULL,
1045 "gpio_142", NULL, NULL, "safe_mode"),
1046 _OMAP3_MUXENTRY(MCBSP3_DR, 141,
1047 "mcbsp3_dr", "uart2_rts", NULL, NULL,
1048 "gpio_141", NULL, NULL, "safe_mode"),
1049 _OMAP3_MUXENTRY(MCBSP3_DX, 140,
1050 "mcbsp3_dx", "uart2_cts", NULL, NULL,
1051 "gpio_140", NULL, NULL, "safe_mode"),
1052 _OMAP3_MUXENTRY(MCBSP3_FSX, 143,
1053 "mcbsp3_fsx", "uart2_rx", NULL, NULL,
1054 "gpio_143", NULL, NULL, "safe_mode"),
1055 _OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
1056 "sdmmc2_dat5", "sdmmc2_dir_dat1",
1057 "cam_global_reset", "sdmmc3_dat1",
1058 "gpio_137", NULL, NULL, "safe_mode"),
1059 _OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
1060 "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
1061 "gpio_138", NULL, NULL, "safe_mode"),
1062 _OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
1063 "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
1064 "gpio_139", NULL, NULL, "safe_mode"),
1065 _OMAP3_MUXENTRY(UART1_CTS, 150,
1066 "uart1_cts", NULL, NULL, NULL,
1067 "gpio_150", NULL, NULL, "safe_mode"),
1068 { .reg_offset = OMAP_MUX_TERMINATOR },
1069};
1070#else
1071#define omap3_cus_subset NULL
1072#endif
1073
1074/*
1075 * Balls for CUS package
1076 * 423-pin s-PBGA Package, 0.65mm Ball Pitch (Bottom)
1077 */
1078#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1079 && defined(CONFIG_OMAP_PACKAGE_CUS)
1080static struct omap_ball __initdata omap3_cus_ball[] = {
1081 _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL),
1082 _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL),
1083 _OMAP3_BALLENTRY(CAM_D10, "f21", NULL),
1084 _OMAP3_BALLENTRY(CAM_D11, "g21", NULL),
1085 _OMAP3_BALLENTRY(CAM_D2, "g19", NULL),
1086 _OMAP3_BALLENTRY(CAM_D3, "f19", NULL),
1087 _OMAP3_BALLENTRY(CAM_D4, "g20", NULL),
1088 _OMAP3_BALLENTRY(CAM_D5, "b21", NULL),
1089 _OMAP3_BALLENTRY(CAM_D6, "l24", NULL),
1090 _OMAP3_BALLENTRY(CAM_D7, "k24", NULL),
1091 _OMAP3_BALLENTRY(CAM_D8, "j23", NULL),
1092 _OMAP3_BALLENTRY(CAM_D9, "k23", NULL),
1093 _OMAP3_BALLENTRY(CAM_FLD, "h24", NULL),
1094 _OMAP3_BALLENTRY(CAM_HS, "a22", NULL),
1095 _OMAP3_BALLENTRY(CAM_PCLK, "j19", NULL),
1096 _OMAP3_BALLENTRY(CAM_STROBE, "j20", NULL),
1097 _OMAP3_BALLENTRY(CAM_VS, "e18", NULL),
1098 _OMAP3_BALLENTRY(CAM_WEN, "f18", NULL),
1099 _OMAP3_BALLENTRY(CAM_XCLKA, "b22", NULL),
1100 _OMAP3_BALLENTRY(CAM_XCLKB, "c22", NULL),
1101 _OMAP3_BALLENTRY(DSS_ACBIAS, "j21", NULL),
1102 _OMAP3_BALLENTRY(DSS_DATA0, "ac19", NULL),
1103 _OMAP3_BALLENTRY(DSS_DATA1, "ab19", NULL),
1104 _OMAP3_BALLENTRY(DSS_DATA10, "ac22", NULL),
1105 _OMAP3_BALLENTRY(DSS_DATA11, "ac23", NULL),
1106 _OMAP3_BALLENTRY(DSS_DATA12, "ab22", NULL),
1107 _OMAP3_BALLENTRY(DSS_DATA13, "y22", NULL),
1108 _OMAP3_BALLENTRY(DSS_DATA14, "w22", NULL),
1109 _OMAP3_BALLENTRY(DSS_DATA15, "v22", NULL),
1110 _OMAP3_BALLENTRY(DSS_DATA16, "j22", NULL),
1111 _OMAP3_BALLENTRY(DSS_DATA17, "g23", NULL),
1112 _OMAP3_BALLENTRY(DSS_DATA18, "g24", NULL),
1113 _OMAP3_BALLENTRY(DSS_DATA19, "h23", NULL),
1114 _OMAP3_BALLENTRY(DSS_DATA2, "ad20", NULL),
1115 _OMAP3_BALLENTRY(DSS_DATA20, "d23", NULL),
1116 _OMAP3_BALLENTRY(DSS_DATA21, "k22", NULL),
1117 _OMAP3_BALLENTRY(DSS_DATA22, "v21", NULL),
1118 _OMAP3_BALLENTRY(DSS_DATA23, "w21", NULL),
1119 _OMAP3_BALLENTRY(DSS_DATA3, "ac20", NULL),
1120 _OMAP3_BALLENTRY(DSS_DATA4, "ad21", NULL),
1121 _OMAP3_BALLENTRY(DSS_DATA5, "ac21", NULL),
1122 _OMAP3_BALLENTRY(DSS_DATA6, "d24", NULL),
1123 _OMAP3_BALLENTRY(DSS_DATA7, "e23", NULL),
1124 _OMAP3_BALLENTRY(DSS_DATA8, "e24", NULL),
1125 _OMAP3_BALLENTRY(DSS_DATA9, "f23", NULL),
1126 _OMAP3_BALLENTRY(DSS_HSYNC, "e22", NULL),
1127 _OMAP3_BALLENTRY(DSS_PCLK, "g22", NULL),
1128 _OMAP3_BALLENTRY(DSS_VSYNC, "f22", NULL),
1129 _OMAP3_BALLENTRY(ETK_CLK, "ac1", NULL),
1130 _OMAP3_BALLENTRY(ETK_CTL, "ad3", NULL),
1131 _OMAP3_BALLENTRY(ETK_D0, "ad6", NULL),
1132 _OMAP3_BALLENTRY(ETK_D1, "ac6", NULL),
1133 _OMAP3_BALLENTRY(ETK_D10, "ac3", NULL),
1134 _OMAP3_BALLENTRY(ETK_D11, "ac9", NULL),
1135 _OMAP3_BALLENTRY(ETK_D12, "ac10", NULL),
1136 _OMAP3_BALLENTRY(ETK_D13, "ad11", NULL),
1137 _OMAP3_BALLENTRY(ETK_D14, "ac11", NULL),
1138 _OMAP3_BALLENTRY(ETK_D15, "ad12", NULL),
1139 _OMAP3_BALLENTRY(ETK_D2, "ac7", NULL),
1140 _OMAP3_BALLENTRY(ETK_D3, "ad8", NULL),
1141 _OMAP3_BALLENTRY(ETK_D4, "ac5", NULL),
1142 _OMAP3_BALLENTRY(ETK_D5, "ad2", NULL),
1143 _OMAP3_BALLENTRY(ETK_D6, "ac8", NULL),
1144 _OMAP3_BALLENTRY(ETK_D7, "ad9", NULL),
1145 _OMAP3_BALLENTRY(ETK_D8, "ac4", NULL),
1146 _OMAP3_BALLENTRY(ETK_D9, "ad5", NULL),
1147 _OMAP3_BALLENTRY(GPMC_A1, "k4", NULL),
1148 _OMAP3_BALLENTRY(GPMC_A10, "g2", NULL),
1149 _OMAP3_BALLENTRY(GPMC_A2, "k3", NULL),
1150 _OMAP3_BALLENTRY(GPMC_A3, "k2", NULL),
1151 _OMAP3_BALLENTRY(GPMC_A4, "j4", NULL),
1152 _OMAP3_BALLENTRY(GPMC_A5, "j3", NULL),
1153 _OMAP3_BALLENTRY(GPMC_A6, "j2", NULL),
1154 _OMAP3_BALLENTRY(GPMC_A7, "j1", NULL),
1155 _OMAP3_BALLENTRY(GPMC_A8, "h1", NULL),
1156 _OMAP3_BALLENTRY(GPMC_A9, "h2", NULL),
1157 _OMAP3_BALLENTRY(GPMC_CLK, "w2", NULL),
1158 _OMAP3_BALLENTRY(GPMC_D10, "u1", NULL),
1159 _OMAP3_BALLENTRY(GPMC_D11, "r3", NULL),
1160 _OMAP3_BALLENTRY(GPMC_D12, "t3", NULL),
1161 _OMAP3_BALLENTRY(GPMC_D13, "u2", NULL),
1162 _OMAP3_BALLENTRY(GPMC_D14, "v1", NULL),
1163 _OMAP3_BALLENTRY(GPMC_D15, "v2", NULL),
1164 _OMAP3_BALLENTRY(GPMC_D8, "r2", NULL),
1165 _OMAP3_BALLENTRY(GPMC_D9, "t2", NULL),
1166 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k5", NULL),
1167 _OMAP3_BALLENTRY(GPMC_NBE1, "l1", NULL),
1168 _OMAP3_BALLENTRY(GPMC_NCS3, "d2", NULL),
1169 _OMAP3_BALLENTRY(GPMC_NCS4, "f4", NULL),
1170 _OMAP3_BALLENTRY(GPMC_NCS5, "g5", NULL),
1171 _OMAP3_BALLENTRY(GPMC_NCS6, "f3", NULL),
1172 _OMAP3_BALLENTRY(GPMC_NCS7, "g4", NULL),
1173 _OMAP3_BALLENTRY(GPMC_NWP, "e1", NULL),
1174 _OMAP3_BALLENTRY(GPMC_WAIT3, "c2", NULL),
1175 _OMAP3_BALLENTRY(HDQ_SIO, "a24", NULL),
1176 _OMAP3_BALLENTRY(HSUSB0_CLK, "r21", NULL),
1177 _OMAP3_BALLENTRY(HSUSB0_DATA0, "t24", NULL),
1178 _OMAP3_BALLENTRY(HSUSB0_DATA1, "t23", NULL),
1179 _OMAP3_BALLENTRY(HSUSB0_DATA2, "u24", NULL),
1180 _OMAP3_BALLENTRY(HSUSB0_DATA3, "u23", NULL),
1181 _OMAP3_BALLENTRY(HSUSB0_DATA4, "w24", NULL),
1182 _OMAP3_BALLENTRY(HSUSB0_DATA5, "v23", NULL),
1183 _OMAP3_BALLENTRY(HSUSB0_DATA6, "w23", NULL),
1184 _OMAP3_BALLENTRY(HSUSB0_DATA7, "t22", NULL),
1185 _OMAP3_BALLENTRY(HSUSB0_DIR, "p23", NULL),
1186 _OMAP3_BALLENTRY(HSUSB0_NXT, "r22", NULL),
1187 _OMAP3_BALLENTRY(HSUSB0_STP, "r23", NULL),
1188 _OMAP3_BALLENTRY(I2C2_SCL, "ac15", NULL),
1189 _OMAP3_BALLENTRY(I2C2_SDA, "ac14", NULL),
1190 _OMAP3_BALLENTRY(I2C3_SCL, "ac13", NULL),
1191 _OMAP3_BALLENTRY(I2C3_SDA, "ac12", NULL),
1192 _OMAP3_BALLENTRY(I2C4_SCL, "y16", NULL),
1193 _OMAP3_BALLENTRY(I2C4_SDA, "y15", NULL),
1194 _OMAP3_BALLENTRY(JTAG_EMU0, "ac24", NULL),
1195 _OMAP3_BALLENTRY(JTAG_EMU1, "ad24", NULL),
1196 _OMAP3_BALLENTRY(MCBSP1_CLKR, "w19", NULL),
1197 _OMAP3_BALLENTRY(MCBSP1_CLKX, "v18", NULL),
1198 _OMAP3_BALLENTRY(MCBSP1_DR, "y18", NULL),
1199 _OMAP3_BALLENTRY(MCBSP1_DX, "w18", NULL),
1200 _OMAP3_BALLENTRY(MCBSP1_FSR, "ab20", NULL),
1201 _OMAP3_BALLENTRY(MCBSP1_FSX, "aa19", NULL),
1202 _OMAP3_BALLENTRY(MCBSP2_CLKX, "t21", NULL),
1203 _OMAP3_BALLENTRY(MCBSP2_DR, "v19", NULL),
1204 _OMAP3_BALLENTRY(MCBSP2_DX, "r20", NULL),
1205 _OMAP3_BALLENTRY(MCBSP2_FSX, "v20", NULL),
1206 _OMAP3_BALLENTRY(MCBSP3_CLKX, "w4", NULL),
1207 _OMAP3_BALLENTRY(MCBSP3_DR, "v5", NULL),
1208 _OMAP3_BALLENTRY(MCBSP3_DX, "v6", NULL),
1209 _OMAP3_BALLENTRY(MCBSP3_FSX, "v4", NULL),
1210 _OMAP3_BALLENTRY(MCBSP_CLKS, "aa18", NULL),
1211 _OMAP3_BALLENTRY(MCSPI1_CLK, "t5", NULL),
1212 _OMAP3_BALLENTRY(MCSPI1_CS0, "t6", NULL),
1213 _OMAP3_BALLENTRY(MCSPI1_CS3, "r5", NULL),
1214 _OMAP3_BALLENTRY(MCSPI1_SIMO, "r4", NULL),
1215 _OMAP3_BALLENTRY(MCSPI1_SOMI, "t4", NULL),
1216 _OMAP3_BALLENTRY(MCSPI2_CLK, "n5", NULL),
1217 _OMAP3_BALLENTRY(MCSPI2_CS0, "m5", NULL),
1218 _OMAP3_BALLENTRY(MCSPI2_CS1, "m4", NULL),
1219 _OMAP3_BALLENTRY(MCSPI2_SIMO, "n4", NULL),
1220 _OMAP3_BALLENTRY(MCSPI2_SOMI, "n3", NULL),
1221 _OMAP3_BALLENTRY(SDMMC1_CLK, "m23", NULL),
1222 _OMAP3_BALLENTRY(SDMMC1_CMD, "l23", NULL),
1223 _OMAP3_BALLENTRY(SDMMC1_DAT0, "m22", NULL),
1224 _OMAP3_BALLENTRY(SDMMC1_DAT1, "m21", NULL),
1225 _OMAP3_BALLENTRY(SDMMC1_DAT2, "m20", NULL),
1226 _OMAP3_BALLENTRY(SDMMC1_DAT3, "n23", NULL),
1227 _OMAP3_BALLENTRY(SDMMC1_DAT4, "n22", NULL),
1228 _OMAP3_BALLENTRY(SDMMC1_DAT5, "n21", NULL),
1229 _OMAP3_BALLENTRY(SDMMC1_DAT6, "n20", NULL),
1230 _OMAP3_BALLENTRY(SDMMC1_DAT7, "p24", NULL),
1231 _OMAP3_BALLENTRY(SDMMC2_CLK, "y1", NULL),
1232 _OMAP3_BALLENTRY(SDMMC2_CMD, "ab5", NULL),
1233 _OMAP3_BALLENTRY(SDMMC2_DAT0, "ab3", NULL),
1234 _OMAP3_BALLENTRY(SDMMC2_DAT1, "y3", NULL),
1235 _OMAP3_BALLENTRY(SDMMC2_DAT2, "w3", NULL),
1236 _OMAP3_BALLENTRY(SDMMC2_DAT3, "v3", NULL),
1237 _OMAP3_BALLENTRY(SDMMC2_DAT4, "ab2", NULL),
1238 _OMAP3_BALLENTRY(SDMMC2_DAT5, "aa2", NULL),
1239 _OMAP3_BALLENTRY(SDMMC2_DAT6, "y2", NULL),
1240 _OMAP3_BALLENTRY(SDMMC2_DAT7, "aa1", NULL),
1241 _OMAP3_BALLENTRY(SYS_BOOT0, "ab12", NULL),
1242 _OMAP3_BALLENTRY(SYS_BOOT1, "ac16", NULL),
1243 _OMAP3_BALLENTRY(SYS_BOOT2, "ad17", NULL),
1244 _OMAP3_BALLENTRY(SYS_BOOT3, "ad18", NULL),
1245 _OMAP3_BALLENTRY(SYS_BOOT4, "ac17", NULL),
1246 _OMAP3_BALLENTRY(SYS_BOOT5, "ab16", NULL),
1247 _OMAP3_BALLENTRY(SYS_BOOT6, "aa15", NULL),
1248 _OMAP3_BALLENTRY(SYS_CLKOUT1, "y7", NULL),
1249 _OMAP3_BALLENTRY(SYS_CLKOUT2, "aa6", NULL),
1250 _OMAP3_BALLENTRY(SYS_CLKREQ, "y13", NULL),
1251 _OMAP3_BALLENTRY(SYS_NIRQ, "w16", NULL),
1252 _OMAP3_BALLENTRY(SYS_NRESWARM, "y10", NULL),
1253 _OMAP3_BALLENTRY(SYS_OFF_MODE, "ad23", NULL),
1254 _OMAP3_BALLENTRY(UART1_CTS, "ac2", NULL),
1255 _OMAP3_BALLENTRY(UART1_RTS, "w6", NULL),
1256 _OMAP3_BALLENTRY(UART1_RX, "v7", NULL),
1257 _OMAP3_BALLENTRY(UART1_TX, "w7", NULL),
1258 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "a23", NULL),
1259 _OMAP3_BALLENTRY(UART3_RTS_SD, "b23", NULL),
1260 _OMAP3_BALLENTRY(UART3_RX_IRRX, "b24", NULL),
1261 _OMAP3_BALLENTRY(UART3_TX_IRTX, "c23", NULL),
1262 { .reg_offset = OMAP_MUX_TERMINATOR },
1263};
1264#else
1265#define omap3_cus_ball NULL
1266#endif
1267
1268/*
1269 * Signals different on CBB package compared to superset
1270 */
1271#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB)
1272static struct omap_mux __initdata omap3_cbb_subset[] = {
1273 _OMAP3_MUXENTRY(CAM_D10, 109,
1274 "cam_d10", NULL, NULL, NULL,
1275 "gpio_109", NULL, NULL, "safe_mode"),
1276 _OMAP3_MUXENTRY(CAM_D11, 110,
1277 "cam_d11", NULL, NULL, NULL,
1278 "gpio_110", NULL, NULL, "safe_mode"),
1279 _OMAP3_MUXENTRY(CAM_D2, 101,
1280 "cam_d2", NULL, NULL, NULL,
1281 "gpio_101", NULL, NULL, "safe_mode"),
1282 _OMAP3_MUXENTRY(CAM_D3, 102,
1283 "cam_d3", NULL, NULL, NULL,
1284 "gpio_102", NULL, NULL, "safe_mode"),
1285 _OMAP3_MUXENTRY(CAM_D4, 103,
1286 "cam_d4", NULL, NULL, NULL,
1287 "gpio_103", NULL, NULL, "safe_mode"),
1288 _OMAP3_MUXENTRY(CAM_D5, 104,
1289 "cam_d5", NULL, NULL, NULL,
1290 "gpio_104", NULL, NULL, "safe_mode"),
1291 _OMAP3_MUXENTRY(CAM_FLD, 98,
1292 "cam_fld", NULL, "cam_global_reset", NULL,
1293 "gpio_98", NULL, NULL, "safe_mode"),
1294 _OMAP3_MUXENTRY(CAM_HS, 94,
1295 "cam_hs", NULL, NULL, NULL,
1296 "gpio_94", NULL, NULL, "safe_mode"),
1297 _OMAP3_MUXENTRY(CAM_PCLK, 97,
1298 "cam_pclk", NULL, NULL, NULL,
1299 "gpio_97", NULL, NULL, "safe_mode"),
1300 _OMAP3_MUXENTRY(CAM_STROBE, 126,
1301 "cam_strobe", NULL, NULL, NULL,
1302 "gpio_126", NULL, NULL, "safe_mode"),
1303 _OMAP3_MUXENTRY(CAM_VS, 95,
1304 "cam_vs", NULL, NULL, NULL,
1305 "gpio_95", NULL, NULL, "safe_mode"),
1306 _OMAP3_MUXENTRY(CAM_WEN, 167,
1307 "cam_wen", NULL, "cam_shutter", NULL,
1308 "gpio_167", NULL, NULL, "safe_mode"),
1309 _OMAP3_MUXENTRY(DSS_DATA6, 76,
1310 "dss_data6", NULL, "uart1_tx", NULL,
1311 "gpio_76", NULL, NULL, "safe_mode"),
1312 _OMAP3_MUXENTRY(DSS_DATA7, 77,
1313 "dss_data7", NULL, "uart1_rx", NULL,
1314 "gpio_77", NULL, NULL, "safe_mode"),
1315 _OMAP3_MUXENTRY(DSS_DATA8, 78,
1316 "dss_data8", NULL, NULL, NULL,
1317 "gpio_78", NULL, NULL, "safe_mode"),
1318 _OMAP3_MUXENTRY(DSS_DATA9, 79,
1319 "dss_data9", NULL, NULL, NULL,
1320 "gpio_79", NULL, NULL, "safe_mode"),
1321 _OMAP3_MUXENTRY(DSS_HSYNC, 67,
1322 "dss_hsync", NULL, NULL, NULL,
1323 "gpio_67", NULL, NULL, "safe_mode"),
1324 _OMAP3_MUXENTRY(DSS_PCLK, 66,
1325 "dss_pclk", NULL, NULL, NULL,
1326 "gpio_66", NULL, NULL, "safe_mode"),
1327 _OMAP3_MUXENTRY(ETK_CLK, 12,
1328 "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
1329 "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
1330 _OMAP3_MUXENTRY(ETK_CTL, 13,
1331 "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
1332 "gpio_13", NULL, "hsusb1_tll_clk", NULL),
1333 _OMAP3_MUXENTRY(ETK_D0, 14,
1334 "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
1335 "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
1336 _OMAP3_MUXENTRY(ETK_D1, 15,
1337 "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
1338 "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
1339 _OMAP3_MUXENTRY(ETK_D10, 24,
1340 "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
1341 "gpio_24", NULL, "hsusb2_tll_clk", NULL),
1342 _OMAP3_MUXENTRY(ETK_D11, 25,
1343 "etk_d11", NULL, NULL, "hsusb2_stp",
1344 "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
1345 _OMAP3_MUXENTRY(ETK_D12, 26,
1346 "etk_d12", NULL, NULL, "hsusb2_dir",
1347 "gpio_26", NULL, "hsusb2_tll_dir", NULL),
1348 _OMAP3_MUXENTRY(ETK_D13, 27,
1349 "etk_d13", NULL, NULL, "hsusb2_nxt",
1350 "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
1351 _OMAP3_MUXENTRY(ETK_D14, 28,
1352 "etk_d14", NULL, NULL, "hsusb2_data0",
1353 "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
1354 _OMAP3_MUXENTRY(ETK_D15, 29,
1355 "etk_d15", NULL, NULL, "hsusb2_data1",
1356 "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
1357 _OMAP3_MUXENTRY(ETK_D2, 16,
1358 "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
1359 "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
1360 _OMAP3_MUXENTRY(ETK_D3, 17,
1361 "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
1362 "gpio_17", NULL, "hsusb1_tll_data7", NULL),
1363 _OMAP3_MUXENTRY(ETK_D4, 18,
1364 "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
1365 "gpio_18", NULL, "hsusb1_tll_data4", NULL),
1366 _OMAP3_MUXENTRY(ETK_D5, 19,
1367 "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
1368 "gpio_19", NULL, "hsusb1_tll_data5", NULL),
1369 _OMAP3_MUXENTRY(ETK_D6, 20,
1370 "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
1371 "gpio_20", NULL, "hsusb1_tll_data6", NULL),
1372 _OMAP3_MUXENTRY(ETK_D7, 21,
1373 "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
1374 "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
1375 _OMAP3_MUXENTRY(ETK_D8, 22,
1376 "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
1377 "gpio_22", NULL, "hsusb1_tll_dir", NULL),
1378 _OMAP3_MUXENTRY(ETK_D9, 23,
1379 "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
1380 "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
1381 { .reg_offset = OMAP_MUX_TERMINATOR },
1382};
1383#else
1384#define omap3_cbb_subset NULL
1385#endif
1386
1387/*
1388 * Balls for CBB package
1389 * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
1390 */
1391#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1392 && defined(CONFIG_OMAP_PACKAGE_CBB)
1393static struct omap_ball __initdata omap3_cbb_ball[] = {
1394 _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
1395 _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
1396 _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
1397 _OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
1398 _OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
1399 _OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
1400 _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
1401 _OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
1402 _OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
1403 _OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
1404 _OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
1405 _OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
1406 _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
1407 _OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
1408 _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
1409 _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
1410 _OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
1411 _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
1412 _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
1413 _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
1414 _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
1415 _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
1416 _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
1417 _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
1418 _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
1419 _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
1420 _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
1421 _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
1422 _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
1423 _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
1424 _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
1425 _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
1426 _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
1427 _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
1428 _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
1429 _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
1430 _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
1431 _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
1432 _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
1433 _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
1434 _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
1435 _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
1436 _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
1437 _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
1438 _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
1439 _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
1440 _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
1441 _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
1442 _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
1443 _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
1444 _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
1445 _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
1446 _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
1447 _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
1448 _OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
1449 _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
1450 _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
1451 _OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
1452 _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
1453 _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
1454 _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
1455 _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
1456 _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
1457 _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
1458 _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
1459 _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
1460 _OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
1461 _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
1462 _OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
1463 _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
1464 _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
1465 _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
1466 _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
1467 _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
1468 _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
1469 _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
1470 _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
1471 _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
1472 _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
1473 _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
1474 _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
1475 _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
1476 _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
1477 _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
1478 _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
1479 _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
1480 _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
1481 _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"),
1482 _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
1483 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
1484 _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
1485 _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
1486 _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
1487 _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
1488 _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
1489 _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
1490 _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
1491 _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
1492 _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
1493 _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
1494 _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
1495 _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
1496 _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
1497 _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
1498 _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
1499 _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
1500 _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
1501 _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
1502 _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
1503 _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
1504 _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
1505 _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
1506 _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
1507 _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
1508 _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
1509 _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
1510 _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
1511 _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
1512 _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
1513 _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
1514 _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
1515 _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
1516 _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
1517 _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
1518 _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
1519 _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
1520 _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
1521 _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
1522 _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
1523 _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
1524 _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
1525 _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
1526 _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
1527 _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
1528 _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
1529 _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
1530 _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
1531 _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
1532 _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
1533 _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
1534 _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
1535 _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
1536 _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
1537 _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
1538 _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
1539 _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
1540 _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
1541 _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
1542 _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
1543 _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
1544 _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
1545 _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
1546 _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
1547 _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
1548 _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
1549 _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
1550 _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
1551 _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
1552 _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
1553 _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
1554 _OMAP3_BALLENTRY(SDMMC1_DAT4, "p27", NULL),
1555 _OMAP3_BALLENTRY(SDMMC1_DAT5, "p26", NULL),
1556 _OMAP3_BALLENTRY(SDMMC1_DAT6, "r27", NULL),
1557 _OMAP3_BALLENTRY(SDMMC1_DAT7, "r25", NULL),
1558 _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
1559 _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
1560 _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
1561 _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
1562 _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
1563 _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
1564 _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
1565 _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
1566 _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
1567 _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
1568 _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
1569 _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
1570 _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
1571 _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
1572 _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
1573 _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
1574 _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
1575 _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
1576 _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
1577 _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
1578 _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
1579 _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
1580 _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
1581 _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
1582 _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
1583 _OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
1584 _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
1585 _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
1586 _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
1587 _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
1588 _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
1589 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
1590 _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
1591 _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
1592 _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
1593 { .reg_offset = OMAP_MUX_TERMINATOR },
1594};
1595#else
1596#define omap3_cbb_ball NULL
1597#endif
1598
1599/*
1600 * Signals different on 36XX CBP package compared to 34XX CBC package
1601 */
1602#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP)
1603static struct omap_mux __initdata omap36xx_cbp_subset[] = {
1604 _OMAP3_MUXENTRY(CAM_D0, 99,
1605 "cam_d0", NULL, "csi2_dx2", NULL,
1606 "gpio_99", NULL, NULL, "safe_mode"),
1607 _OMAP3_MUXENTRY(CAM_D1, 100,
1608 "cam_d1", NULL, "csi2_dy2", NULL,
1609 "gpio_100", NULL, NULL, "safe_mode"),
1610 _OMAP3_MUXENTRY(CAM_D10, 109,
1611 "cam_d10", "ssi2_wake", NULL, NULL,
1612 "gpio_109", "hw_dbg8", NULL, "safe_mode"),
1613 _OMAP3_MUXENTRY(CAM_D2, 101,
1614 "cam_d2", "ssi2_rdy_tx", NULL, NULL,
1615 "gpio_101", "hw_dbg4", NULL, "safe_mode"),
1616 _OMAP3_MUXENTRY(CAM_D3, 102,
1617 "cam_d3", "ssi2_dat_rx", NULL, NULL,
1618 "gpio_102", "hw_dbg5", NULL, "safe_mode"),
1619 _OMAP3_MUXENTRY(CAM_D4, 103,
1620 "cam_d4", "ssi2_flag_rx", NULL, NULL,
1621 "gpio_103", "hw_dbg6", NULL, "safe_mode"),
1622 _OMAP3_MUXENTRY(CAM_D5, 104,
1623 "cam_d5", "ssi2_rdy_rx", NULL, NULL,
1624 "gpio_104", "hw_dbg7", NULL, "safe_mode"),
1625 _OMAP3_MUXENTRY(CAM_HS, 94,
1626 "cam_hs", "ssi2_dat_tx", NULL, NULL,
1627 "gpio_94", "hw_dbg0", NULL, "safe_mode"),
1628 _OMAP3_MUXENTRY(CAM_VS, 95,
1629 "cam_vs", "ssi2_flag_tx", NULL, NULL,
1630 "gpio_95", "hw_dbg1", NULL, "safe_mode"),
1631 _OMAP3_MUXENTRY(DSS_DATA0, 70,
1632 "dss_data0", "dsi_dx0", "uart1_cts", NULL,
1633 "gpio_70", NULL, NULL, "safe_mode"),
1634 _OMAP3_MUXENTRY(DSS_DATA1, 71,
1635 "dss_data1", "dsi_dy0", "uart1_rts", NULL,
1636 "gpio_71", NULL, NULL, "safe_mode"),
1637 _OMAP3_MUXENTRY(DSS_DATA2, 72,
1638 "dss_data2", "dsi_dx1", NULL, NULL,
1639 "gpio_72", NULL, NULL, "safe_mode"),
1640 _OMAP3_MUXENTRY(DSS_DATA3, 73,
1641 "dss_data3", "dsi_dy1", NULL, NULL,
1642 "gpio_73", NULL, NULL, "safe_mode"),
1643 _OMAP3_MUXENTRY(DSS_DATA4, 74,
1644 "dss_data4", "dsi_dx2", "uart3_rx_irrx", NULL,
1645 "gpio_74", NULL, NULL, "safe_mode"),
1646 _OMAP3_MUXENTRY(DSS_DATA5, 75,
1647 "dss_data5", "dsi_dy2", "uart3_tx_irtx", NULL,
1648 "gpio_75", NULL, NULL, "safe_mode"),
1649 _OMAP3_MUXENTRY(DSS_DATA6, 76,
1650 "dss_data6", NULL, "uart1_tx", "dssvenc656_data6",
1651 "gpio_76", "hw_dbg14", NULL, "safe_mode"),
1652 _OMAP3_MUXENTRY(DSS_DATA7, 77,
1653 "dss_data7", NULL, "uart1_rx", "dssvenc656_data7",
1654 "gpio_77", "hw_dbg15", NULL, "safe_mode"),
1655 _OMAP3_MUXENTRY(DSS_DATA8, 78,
1656 "dss_data8", NULL, "uart3_rx_irrx", NULL,
1657 "gpio_78", "hw_dbg16", NULL, "safe_mode"),
1658 _OMAP3_MUXENTRY(DSS_DATA9, 79,
1659 "dss_data9", NULL, "uart3_tx_irtx", NULL,
1660 "gpio_79", "hw_dbg17", NULL, "safe_mode"),
1661 _OMAP3_MUXENTRY(ETK_D12, 26,
1662 "etk_d12", "sys_drm_msecure", NULL, "hsusb2_dir",
1663 "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
1664 _OMAP3_MUXENTRY(GPMC_A11, 0,
1665 "gpmc_a11", NULL, NULL, NULL,
1666 NULL, NULL, NULL, "safe_mode"),
1667 _OMAP3_MUXENTRY(GPMC_WAIT2, 64,
1668 "gpmc_wait2", NULL, "uart4_tx", NULL,
1669 "gpio_64", NULL, NULL, "safe_mode"),
1670 _OMAP3_MUXENTRY(GPMC_WAIT3, 65,
1671 "gpmc_wait3", "sys_ndmareq1", "uart4_rx", NULL,
1672 "gpio_65", NULL, NULL, "safe_mode"),
1673 _OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
1674 "hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
1675 "gpio_125", "uart2_tx", NULL, "safe_mode"),
1676 _OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
1677 "hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
1678 "gpio_130", "uart2_rx", NULL, "safe_mode"),
1679 _OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
1680 "hsusb0_data2", NULL, "uart3_rts_sd", NULL,
1681 "gpio_131", "uart2_rts", NULL, "safe_mode"),
1682 _OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
1683 "hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
1684 "gpio_169", "uart2_cts", NULL, "safe_mode"),
1685 _OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
1686 "mcbsp1_clkr", "mcspi4_clk", "sim_cd", NULL,
1687 "gpio_156", NULL, NULL, "safe_mode"),
1688 _OMAP3_MUXENTRY(MCBSP1_FSR, 157,
1689 "mcbsp1_fsr", "adpllv2d_dithering_en1",
1690 "cam_global_reset", NULL,
1691 "gpio_157", NULL, NULL, "safe_mode"),
1692 _OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
1693 "mcbsp4_clkx", "ssi1_dat_rx", NULL, NULL,
1694 "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
1695 _OMAP3_MUXENTRY(MCBSP4_DR, 153,
1696 "mcbsp4_dr", "ssi1_flag_rx", NULL, NULL,
1697 "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
1698 _OMAP3_MUXENTRY(MCBSP4_DX, 154,
1699 "mcbsp4_dx", "ssi1_rdy_rx", NULL, NULL,
1700 "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
1701 _OMAP3_MUXENTRY(MCBSP4_FSX, 155,
1702 "mcbsp4_fsx", "ssi1_wake", NULL, NULL,
1703 "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
1704 _OMAP3_MUXENTRY(MCSPI1_CS1, 175,
1705 "mcspi1_cs1", "adpllv2d_dithering_en2", NULL, "sdmmc3_cmd",
1706 "gpio_175", NULL, NULL, "safe_mode"),
1707 _OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
1708 "sad2d_mbusflag", "mad2d_sbusflag", NULL, NULL,
1709 NULL, NULL, NULL, NULL),
1710 _OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
1711 "sad2d_mcad28", "mad2d_mcad28", NULL, NULL,
1712 NULL, NULL, NULL, NULL),
1713 _OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
1714 "sad2d_mcad29", "mad2d_mcad29", NULL, NULL,
1715 NULL, NULL, NULL, NULL),
1716 _OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
1717 "sad2d_mcad32", "mad2d_mcad32", NULL, NULL,
1718 NULL, NULL, NULL, NULL),
1719 _OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
1720 "sad2d_mcad33", "mad2d_mcad33", NULL, NULL,
1721 NULL, NULL, NULL, NULL),
1722 _OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
1723 "sad2d_mcad34", "mad2d_mcad34", NULL, NULL,
1724 NULL, NULL, NULL, NULL),
1725 _OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
1726 "sad2d_mcad35", "mad2d_mcad35", NULL, NULL,
1727 NULL, NULL, NULL, NULL),
1728 _OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
1729 "sad2d_mcad36", "mad2d_mcad36", NULL, NULL,
1730 NULL, NULL, NULL, NULL),
1731 _OMAP3_MUXENTRY(SAD2D_MREAD, 0,
1732 "sad2d_mread", "mad2d_sread", NULL, NULL,
1733 NULL, NULL, NULL, NULL),
1734 _OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
1735 "sad2d_mwrite", "mad2d_swrite", NULL, NULL,
1736 NULL, NULL, NULL, NULL),
1737 _OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
1738 "sad2d_sbusflag", "mad2d_mbusflag", NULL, NULL,
1739 NULL, NULL, NULL, NULL),
1740 _OMAP3_MUXENTRY(SAD2D_SREAD, 0,
1741 "sad2d_sread", "mad2d_mread", NULL, NULL,
1742 NULL, NULL, NULL, NULL),
1743 _OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
1744 "sad2d_swrite", "mad2d_mwrite", NULL, NULL,
1745 NULL, NULL, NULL, NULL),
1746 _OMAP3_MUXENTRY(SDMMC1_CLK, 120,
1747 "sdmmc1_clk", "ms_clk", NULL, NULL,
1748 "gpio_120", NULL, NULL, "safe_mode"),
1749 _OMAP3_MUXENTRY(SDMMC1_CMD, 121,
1750 "sdmmc1_cmd", "ms_bs", NULL, NULL,
1751 "gpio_121", NULL, NULL, "safe_mode"),
1752 _OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
1753 "sdmmc1_dat0", "ms_dat0", NULL, NULL,
1754 "gpio_122", NULL, NULL, "safe_mode"),
1755 _OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
1756 "sdmmc1_dat1", "ms_dat1", NULL, NULL,
1757 "gpio_123", NULL, NULL, "safe_mode"),
1758 _OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
1759 "sdmmc1_dat2", "ms_dat2", NULL, NULL,
1760 "gpio_124", NULL, NULL, "safe_mode"),
1761 _OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
1762 "sdmmc1_dat3", "ms_dat3", NULL, NULL,
1763 "gpio_125", NULL, NULL, "safe_mode"),
1764 _OMAP3_MUXENTRY(SDRC_CKE0, 0,
1765 "sdrc_cke0", NULL, NULL, NULL,
1766 NULL, NULL, NULL, "safe_mode_out1"),
1767 _OMAP3_MUXENTRY(SDRC_CKE1, 0,
1768 "sdrc_cke1", NULL, NULL, NULL,
1769 NULL, NULL, NULL, "safe_mode_out1"),
1770 _OMAP3_MUXENTRY(SIM_IO, 126,
1771 "sim_io", "sim_io_low_impedance", NULL, NULL,
1772 "gpio_126", NULL, NULL, "safe_mode"),
1773 _OMAP3_MUXENTRY(SIM_CLK, 127,
1774 "sim_clk", NULL, NULL, NULL,
1775 "gpio_127", NULL, NULL, "safe_mode"),
1776 _OMAP3_MUXENTRY(SIM_PWRCTRL, 128,
1777 "sim_pwrctrl", NULL, NULL, NULL,
1778 "gpio_128", NULL, NULL, "safe_mode"),
1779 _OMAP3_MUXENTRY(SIM_RST, 129,
1780 "sim_rst", NULL, NULL, NULL,
1781 "gpio_129", NULL, NULL, "safe_mode"),
1782 _OMAP3_MUXENTRY(SYS_BOOT0, 2,
1783 "sys_boot0", NULL, NULL, "dss_data18",
1784 "gpio_2", NULL, NULL, "safe_mode"),
1785 _OMAP3_MUXENTRY(SYS_BOOT1, 3,
1786 "sys_boot1", NULL, NULL, "dss_data19",
1787 "gpio_3", NULL, NULL, "safe_mode"),
1788 _OMAP3_MUXENTRY(SYS_BOOT3, 5,
1789 "sys_boot3", NULL, NULL, "dss_data20",
1790 "gpio_5", NULL, NULL, "safe_mode"),
1791 _OMAP3_MUXENTRY(SYS_BOOT4, 6,
1792 "sys_boot4", "sdmmc2_dir_dat2", NULL, "dss_data21",
1793 "gpio_6", NULL, NULL, "safe_mode"),
1794 _OMAP3_MUXENTRY(SYS_BOOT5, 7,
1795 "sys_boot5", "sdmmc2_dir_dat3", NULL, "dss_data22",
1796 "gpio_7", NULL, NULL, "safe_mode"),
1797 _OMAP3_MUXENTRY(SYS_BOOT6, 8,
1798 "sys_boot6", NULL, NULL, "dss_data23",
1799 "gpio_8", NULL, NULL, "safe_mode"),
1800 _OMAP3_MUXENTRY(UART1_CTS, 150,
1801 "uart1_cts", "ssi1_rdy_tx", NULL, NULL,
1802 "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
1803 _OMAP3_MUXENTRY(UART1_RTS, 149,
1804 "uart1_rts", "ssi1_flag_tx", NULL, NULL,
1805 "gpio_149", NULL, NULL, "safe_mode"),
1806 _OMAP3_MUXENTRY(UART1_TX, 148,
1807 "uart1_tx", "ssi1_dat_tx", NULL, NULL,
1808 "gpio_148", NULL, NULL, "safe_mode"),
1809 { .reg_offset = OMAP_MUX_TERMINATOR },
1810};
1811#else
1812#define omap36xx_cbp_subset NULL
1813#endif
1814
1815/*
1816 * Balls for 36XX CBP package
1817 * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
1818 */
1819#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1820 && defined (CONFIG_OMAP_PACKAGE_CBP)
1821static struct omap_ball __initdata omap36xx_cbp_ball[] = {
1822 _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
1823 _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
1824 _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
1825 _OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
1826 _OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
1827 _OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
1828 _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
1829 _OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
1830 _OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
1831 _OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
1832 _OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
1833 _OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
1834 _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
1835 _OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
1836 _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
1837 _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
1838 _OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
1839 _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
1840 _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
1841 _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
1842 _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
1843 _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
1844 _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
1845 _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
1846 _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
1847 _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
1848 _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
1849 _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
1850 _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
1851 _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
1852 _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
1853 _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
1854 _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
1855 _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
1856 _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
1857 _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
1858 _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
1859 _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
1860 _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
1861 _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
1862 _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
1863 _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
1864 _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
1865 _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
1866 _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
1867 _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
1868 _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
1869 _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
1870 _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
1871 _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
1872 _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
1873 _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
1874 _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
1875 _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
1876 _OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
1877 _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
1878 _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
1879 _OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
1880 _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
1881 _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
1882 _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
1883 _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
1884 _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
1885 _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
1886 _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
1887 _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
1888 _OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
1889 _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
1890 _OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
1891 _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
1892 _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
1893 _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
1894 _OMAP3_BALLENTRY(GPMC_A11, NULL, "ac20"),
1895 _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
1896 _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
1897 _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
1898 _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
1899 _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
1900 _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
1901 _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
1902 _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
1903 _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
1904 _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
1905 _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
1906 _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
1907 _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
1908 _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
1909 _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
1910 _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
1911 _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
1912 _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
1913 _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
1914 _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
1915 _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
1916 _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
1917 _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
1918 _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
1919 _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
1920 _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
1921 _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
1922 _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
1923 _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
1924 _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
1925 _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
1926 _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
1927 _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
1928 _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
1929 _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
1930 _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
1931 _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
1932 _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
1933 _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
1934 _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
1935 _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
1936 _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
1937 _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
1938 _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
1939 _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
1940 _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
1941 _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
1942 _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
1943 _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
1944 _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
1945 _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
1946 _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
1947 _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
1948 _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
1949 _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
1950 _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
1951 _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
1952 _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
1953 _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
1954 _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
1955 _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
1956 _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
1957 _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
1958 _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
1959 _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
1960 _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
1961 _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
1962 _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
1963 _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
1964 _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
1965 _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
1966 _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
1967 _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
1968 _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
1969 _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
1970 _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
1971 _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
1972 _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
1973 _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
1974 _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
1975 _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
1976 _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
1977 _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
1978 _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
1979 _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
1980 _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
1981 _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
1982 _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
1983 _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
1984 _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
1985 _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
1986 _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
1987 _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
1988 _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
1989 _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
1990 _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
1991 _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
1992 _OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"),
1993 _OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"),
1994 _OMAP3_BALLENTRY(SIM_CLK, "p26", NULL),
1995 _OMAP3_BALLENTRY(SIM_IO, "p27", NULL),
1996 _OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL),
1997 _OMAP3_BALLENTRY(SIM_RST, "r25", NULL),
1998 _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
1999 _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
2000 _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
2001 _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
2002 _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
2003 _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
2004 _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
2005 _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
2006 _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
2007 _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
2008 _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
2009 _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
2010 _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
2011 _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
2012 _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
2013 _OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
2014 _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
2015 _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
2016 _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
2017 _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
2018 _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
2019 _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
2020 _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
2021 _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
2022 _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
2023 { .reg_offset = OMAP_MUX_TERMINATOR },
2024};
2025#else
2026#define omap36xx_cbp_ball NULL
2027#endif
2028
2029int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
2030{
2031 struct omap_mux *package_subset;
2032 struct omap_ball *package_balls;
2033
2034 switch (flags & OMAP_PACKAGE_MASK) {
2035 case OMAP_PACKAGE_CBC:
2036 package_subset = omap3_cbc_subset;
2037 package_balls = omap3_cbc_ball;
2038 break;
2039 case OMAP_PACKAGE_CBB:
2040 package_subset = omap3_cbb_subset;
2041 package_balls = omap3_cbb_ball;
2042 break;
2043 case OMAP_PACKAGE_CUS:
2044 package_subset = omap3_cus_subset;
2045 package_balls = omap3_cus_ball;
2046 break;
2047 case OMAP_PACKAGE_CBP:
2048 package_subset = omap36xx_cbp_subset;
2049 package_balls = omap36xx_cbp_ball;
2050 break;
2051 default:
2052 pr_err("%s Unknown omap package, mux disabled\n", __func__);
2053 return -EINVAL;
2054 }
2055
2056 return omap_mux_init("core", OMAP_MUX_GPIO_IN_MODE4,
2057 OMAP3_CONTROL_PADCONF_MUX_PBASE,
2058 OMAP3_CONTROL_PADCONF_MUX_SIZE,
2059 omap3_muxmodes, package_subset, board_subset,
2060 package_balls);
2061}
diff --git a/arch/arm/mach-omap2/mux34xx.h b/arch/arm/mach-omap2/mux34xx.h
deleted file mode 100644
index 3f26d297c082..000000000000
--- a/arch/arm/mach-omap2/mux34xx.h
+++ /dev/null
@@ -1,402 +0,0 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU
11
12#define OMAP3_MUX(mode0, mux_value) \
13{ \
14 .reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \
15 .value = (mux_value), \
16}
17
18/*
19 * OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
20 *
21 * Extracted from the TRM. Add 0x48002030 to these values to get the
22 * absolute addresses. The name in the macro is the mode-0 name of
23 * the pin. NOTE: These registers are 16-bits wide.
24 *
25 * Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
26 * of CHASSIS for some registers. For the defines, we follow the
27 * 36XX naming, and use SDMMC and CHASSIS.
28 */
29#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000
30#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002
31#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004
32#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006
33#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008
34#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a
35#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c
36#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e
37#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010
38#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012
39#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014
40#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016
41#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018
42#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a
43#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c
44#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e
45#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020
46#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022
47#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024
48#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026
49#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028
50#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a
51#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c
52#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e
53#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030
54#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032
55#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034
56#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036
57#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038
58#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a
59#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c
60#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e
61#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040
62#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042
63#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044
64#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046
65#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048
66#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
67#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c
68#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e
69#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050
70#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052
71#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054
72#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056
73#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058
74#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a
75#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c
76#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e
77#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060
78#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062
79#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064
80#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066
81#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068
82#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a
83#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c
84#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e
85#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070
86#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072
87#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074
88#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076
89#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078
90#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a
91#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c
92#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e
93#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080
94#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082
95#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084
96#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086
97#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088
98#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a
99#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c
100#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e
101#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090
102#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092
103#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094
104#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096
105#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098
106#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a
107#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c
108#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e
109#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0
110#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2
111#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4
112#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6
113#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8
114#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa
115#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac
116#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae
117#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0
118#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2
119#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4
120#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6
121#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8
122#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba
123#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc
124#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be
125#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0
126#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2
127#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4
128#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6
129#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8
130#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca
131#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc
132#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce
133#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0
134#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2
135#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4
136#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6
137#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8
138#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da
139#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc
140#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de
141#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0
142#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2
143#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4
144#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6
145#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8
146#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea
147#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec
148#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee
149#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0
150#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2
151#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4
152#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6
153#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8
154#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa
155#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc
156#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe
157#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100
158#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102
159#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104
160#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106
161#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108
162#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a
163#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c
164#define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x10e
165#define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x110
166#define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET 0x112
167#define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET 0x114
168#define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x116
169#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x118
170#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x11a
171#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x11c
172#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x11e
173
174/* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */
175#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET 0x120
176#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET 0x122
177#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET 0x124
178#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET 0x126
179
180#define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET 0x128
181#define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x12a
182#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x12c
183#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x12e
184#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x130
185#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x132
186#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET 0x134
187#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET 0x136
188#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET 0x138
189#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET 0x13a
190#define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13c
191#define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x13e
192#define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140
193#define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x142
194#define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET 0x144
195#define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET 0x146
196#define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET 0x148
197#define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET 0x14a
198#define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET 0x14c
199#define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET 0x14e
200#define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET 0x150
201#define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET 0x152
202#define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET 0x154
203#define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET 0x156
204#define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET 0x158
205#define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET 0x15a
206#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x15c
207#define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x15e
208#define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x160
209#define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x162
210#define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x164
211#define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x166
212#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x168
213#define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x16a
214#define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x16c
215#define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x16e
216#define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x170
217#define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET 0x172
218#define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET 0x174
219#define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET 0x176
220#define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET 0x178
221#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET 0x17a
222#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET 0x17c
223#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET 0x17e
224#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET 0x180
225#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET 0x182
226#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET 0x184
227#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET 0x186
228#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET 0x188
229#define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x18a
230#define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x18c
231#define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x18e
232#define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x190
233#define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET 0x192
234#define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET 0x194
235#define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x196
236#define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET 0x198
237#define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET 0x19a
238#define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET 0x19c
239#define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET 0x19e
240#define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET 0x1a0
241#define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET 0x1a2
242#define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET 0x1a4
243#define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET 0x1a6
244#define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET 0x1a8
245#define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET 0x1aa
246#define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET 0x1ac
247#define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET 0x1ae
248#define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x1b0
249#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET 0x1b2
250#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET 0x1b4
251#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET 0x1b6
252#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET 0x1b8
253#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET 0x1ba
254#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET 0x1bc
255#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET 0x1be
256#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET 0x1c0
257#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET 0x1c2
258#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET 0x1c4
259#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET 0x1c6
260#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET 0x1c8
261#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET 0x1ca
262#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET 0x1cc
263#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET 0x1ce
264#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET 0x1d0
265#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET 0x1d2
266#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET 0x1d4
267#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET 0x1d6
268#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET 0x1d8
269#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET 0x1da
270#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET 0x1dc
271#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET 0x1de
272#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET 0x1e0
273#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET 0x1e2
274#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET 0x1e4
275#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET 0x1e6
276#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET 0x1e8
277#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET 0x1ea
278#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET 0x1ec
279#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET 0x1ee
280#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET 0x1f0
281#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET 0x1f2
282#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET 0x1f4
283#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET 0x1f6
284#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET 0x1f8
285#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET 0x1fa
286#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET 0x1fc
287
288/* Note that 34xx TRM has SAD2D instead of CHASSIS for these */
289#define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET 0x1fe
290#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET 0x200
291#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET 0x202
292#define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET 0x204
293#define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET 0x206
294#define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET 0x208
295#define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET 0x20a
296#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET 0x20c
297#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET 0x20e
298#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET 0x210
299#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET 0x212
300#define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET 0x214
301#define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET 0x216
302#define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET 0x218
303#define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET 0x21a
304#define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET 0x21c
305#define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET 0x21e
306#define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET 0x220
307#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET 0x222
308#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET 0x224
309
310#define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET 0x226
311#define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET 0x228
312#define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET 0x22a
313#define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET 0x22c
314#define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET 0x22e
315#define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET 0x230
316#define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x232
317#define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x234
318
319/* 36xx only */
320#define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET 0x236
321#define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x570
322#define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x572
323#define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET 0x574
324#define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET 0x576
325#define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET 0x578
326#define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET 0x57a
327#define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET 0x57c
328#define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET 0x57e
329#define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET 0x580
330#define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET 0x582
331#define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET 0x584
332#define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET 0x586
333#define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET 0x588
334#define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET 0x58a
335#define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET 0x58c
336#define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET 0x58e
337#define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET 0x590
338#define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x592
339#define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x594
340#define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x596
341#define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x598
342#define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x59a
343#define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x59c
344#define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x59e
345#define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x5a0
346#define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x5a2
347#define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x5a4
348
349/* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */
350#define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET 0x120
351#define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET 0x122
352#define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET 0x124
353#define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET 0x126
354
355#define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET 0x5a8
356#define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET 0x5aa
357#define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET 0x5ac
358#define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET 0x5ae
359#define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET 0x5b0
360#define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET 0x5b2
361#define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET 0x5b4
362#define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET 0x5b6
363#define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET 0x5b8
364#define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET 0x5ba
365#define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET 0x5bc
366#define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET 0x5be
367#define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET 0x5c0
368#define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET 0x5c2
369#define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET 0x5c4
370#define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET 0x5c6
371#define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET 0x5c8
372#define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET 0x5ca
373#define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET 0x9d0
374#define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET 0x9d2
375#define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET 0x9d4
376#define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x9d6
377#define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x9d8
378#define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET 0x9da
379#define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET 0x9dc
380#define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET 0x9de
381#define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET 0x9e0
382#define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET 0x9e2
383#define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET 0x9e4
384#define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET 0x9e6
385#define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET 0x9e8
386#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET 0x9ea
387#define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x9ec
388#define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x9ee
389#define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET 0x9f0
390#define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x9f2
391#define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x9f4
392#define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x9f6
393#define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET 0xa1c
394#define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0xa1e
395#define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET 0xa20
396#define OMAP3_CONTROL_PADCONF_GPIO_127 0xa24
397#define OMAP3_CONTROL_PADCONF_GPIO_126 0xa26
398#define OMAP3_CONTROL_PADCONF_GPIO_128 0xa28
399#define OMAP3_CONTROL_PADCONF_GPIO_129 0xa2a
400
401#define OMAP3_CONTROL_PADCONF_MUX_SIZE \
402 (OMAP3_CONTROL_PADCONF_GPIO_129 + 0x2)
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index d055db32ffcb..3e27bffb352d 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -63,32 +63,6 @@ config OMAP_RESET_CLOCKS
63 probably do not want this option enabled until your 63 probably do not want this option enabled until your
64 device drivers work properly. 64 device drivers work properly.
65 65
66config OMAP_MUX
67 bool "OMAP multiplexing support"
68 depends on ARCH_OMAP
69 default y
70 help
71 Pin multiplexing support for OMAP boards. If your bootloader
72 sets the multiplexing correctly, say N. Otherwise, or if unsure,
73 say Y.
74
75config OMAP_MUX_DEBUG
76 bool "Multiplexing debug output"
77 depends on OMAP_MUX
78 help
79 Makes the multiplexing functions print out a lot of debug info.
80 This is useful if you want to find out the correct values of the
81 multiplexing registers.
82
83config OMAP_MUX_WARNINGS
84 bool "Warn about pins the bootloader didn't set up"
85 depends on OMAP_MUX
86 default y
87 help
88 Choose Y here to warn whenever driver initialization logic needs
89 to change the pin multiplexing setup. When there are no warnings
90 printed, it's safe to deselect OMAP_MUX for your product.
91
92config OMAP_MPU_TIMER 66config OMAP_MPU_TIMER
93 bool "Use mpu timer" 67 bool "Use mpu timer"
94 depends on ARCH_OMAP1 68 depends on ARCH_OMAP1
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 13:09:06 -0400