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authorLinus Torvalds <torvalds@linux-foundation.org>2016-03-20 17:37:22 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-03-20 17:37:22 -0400
commite88fa1b8b00a947299e2415e819301fa52037cf4 (patch)
treec16dc012450345b52e2a8fa2562f3470e2b3c546
parentdae0b74eb7abd7d5c7572414b0c8f91c2dab63c0 (diff)
parent809683ee060de5ea45294d465dc242dee1ff189f (diff)
Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Arnd Bergmann: "A few simple cleanups across multiple platforms, not much standing out: - lpc32xx removes its private implementation of the clk API, after generic code was merged in 4.5 - all unused Makefile.boot files get removed - a number of simplifications for shmobile - asm/clkdev.h gets replaced with the asm-generic version after all mach/clkdev.h implementations are gone" * tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: shmobile: Kconfig: Get rid of old comment ARM: shmobile: Consolidate SCU mapping code arm: lpc32xx: remove direct control of GPIOs from shared mach file arm: lpc32xx: remove selected HAVE_IDE arm: lpc32xx: switch to common clock framework ARM: Use generic clkdev.h header ARM: plat-versatile: Remove unused clock.c file ARM: netx: remove redundant "depends on ARCH_NETX" ARM: integrator: remove redundant select in Kconfig ARM: drop unused Makefile.boot of Multiplatform SoCs ARM: mvebu: add missing of_node_put() ARM: shmobile: r8a7779: Remove remainings of removed SCU boot setup code ARM: shmobile: Typo s/MIPDR/MPIDR/ ARM: shmobile: Add includes providing forward declarations ARM: shmobile: rcar-gen2: Make rcar_gen2_dma_contiguous static ARM: mv78xx0: use "depends on" instead of "if" after prompt
Diffstat
-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/include/asm/Kbuild1
-rw-r--r--arch/arm/include/asm/clkdev.h31
-rw-r--r--arch/arm/mach-cns3xxx/Makefile.boot3
-rw-r--r--arch/arm/mach-exynos/Makefile.boot2
-rw-r--r--arch/arm/mach-integrator/Kconfig6
-rw-r--r--arch/arm/mach-integrator/Makefile.boot4
-rw-r--r--arch/arm/mach-keystone/Makefile.boot1
-rw-r--r--arch/arm/mach-lpc32xx/Makefile3
-rw-r--r--arch/arm/mach-lpc32xx/clock.c1284
-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c53
-rw-r--r--arch/arm/mach-lpc32xx/serial.c3
-rw-r--r--arch/arm/mach-lpc32xx/timer.c144
-rw-r--r--arch/arm/mach-mmp/Makefile.boot1
-rw-r--r--arch/arm/mach-mv78xx0/Kconfig3
-rw-r--r--arch/arm/mach-mv78xx0/Makefile.boot3
-rw-r--r--arch/arm/mach-mvebu/platsmp.c1
-rw-r--r--arch/arm/mach-netx/Kconfig3
-rw-r--r--arch/arm/mach-nspire/Makefile.boot0
-rw-r--r--arch/arm/mach-omap2/Makefile.boot3
-rw-r--r--arch/arm/mach-orion5x/Makefile.boot3
-rw-r--r--arch/arm/mach-prima2/Makefile.boot3
-rw-r--r--arch/arm/mach-realview/Makefile.boot9
-rw-r--r--arch/arm/mach-s3c64xx/Makefile.boot2
-rw-r--r--arch/arm/mach-shmobile/Kconfig2
-rw-r--r--arch/arm/mach-shmobile/common.h5
-rw-r--r--arch/arm/mach-shmobile/cpufreq.c2
-rw-r--r--arch/arm/mach-shmobile/headsmp-scu.S2
-rw-r--r--arch/arm/mach-shmobile/platsmp-scu.c10
-rw-r--r--arch/arm/mach-shmobile/setup-rcar-gen2.c7
-rw-r--r--arch/arm/mach-shmobile/smp-emev2.c3
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7779.c3
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c3
-rw-r--r--arch/arm/mach-shmobile/suspend.c2
-rw-r--r--arch/arm/mach-shmobile/timer.c2
-rw-r--r--arch/arm/mach-spear/Makefile.boot3
-rw-r--r--arch/arm/mach-u300/Makefile.boot4
-rw-r--r--arch/arm/mach-ux500/Makefile.boot3
-rw-r--r--arch/arm/mach-zynq/Makefile.boot3
-rw-r--r--arch/arm/plat-versatile/Kconfig3
-rw-r--r--arch/arm/plat-versatile/Makefile1
-rw-r--r--arch/arm/plat-versatile/clock.c74
42 files changed, 30 insertions, 1672 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 99c11433115e..c18357f4a01a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -527,10 +527,10 @@ config ARCH_LPC32XX
527 select ARCH_REQUIRE_GPIOLIB 527 select ARCH_REQUIRE_GPIOLIB
528 select ARM_AMBA 528 select ARM_AMBA
529 select CLKDEV_LOOKUP 529 select CLKDEV_LOOKUP
530 select CLKSRC_MMIO 530 select CLKSRC_LPC32XX
531 select COMMON_CLK
531 select CPU_ARM926T 532 select CPU_ARM926T
532 select GENERIC_CLOCKEVENTS 533 select GENERIC_CLOCKEVENTS
533 select HAVE_IDE
534 select USE_OF 534 select USE_OF
535 help 535 help
536 Support for the NXP LPC32XX family of processors 536 Support for the NXP LPC32XX family of processors
diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index 3f6616b472af..55e0e3ea9cb6 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -1,6 +1,7 @@
1 1
2 2
3generic-y += bitsperlong.h 3generic-y += bitsperlong.h
4generic-y += clkdev.h
4generic-y += cputime.h 5generic-y += cputime.h
5generic-y += current.h 6generic-y += current.h
6generic-y += early_ioremap.h 7generic-y += early_ioremap.h
diff --git a/arch/arm/include/asm/clkdev.h b/arch/arm/include/asm/clkdev.h
deleted file mode 100644
index 4e8a4b27d7c7..000000000000
--- a/arch/arm/include/asm/clkdev.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * arch/arm/include/asm/clkdev.h
3 *
4 * Copyright (C) 2008 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Helper for the clk API to assist looking up a struct clk.
11 */
12#ifndef __ASM_CLKDEV_H
13#define __ASM_CLKDEV_H
14
15#include <linux/slab.h>
16
17#ifndef CONFIG_COMMON_CLK
18#ifdef CONFIG_HAVE_MACH_CLKDEV
19#include <mach/clkdev.h>
20#else
21#define __clk_get(clk) ({ 1; })
22#define __clk_put(clk) do { } while (0)
23#endif
24#endif
25
26static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
27{
28 return kzalloc(size, GFP_KERNEL);
29}
30
31#endif
diff --git a/arch/arm/mach-cns3xxx/Makefile.boot b/arch/arm/mach-cns3xxx/Makefile.boot
deleted file mode 100644
index d079de0b6e3b..000000000000
--- a/arch/arm/mach-cns3xxx/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y += 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00C00000
diff --git a/arch/arm/mach-exynos/Makefile.boot b/arch/arm/mach-exynos/Makefile.boot
deleted file mode 100644
index b9862e22bf10..000000000000
--- a/arch/arm/mach-exynos/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y += 0x40008000
2params_phys-y := 0x40000100
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index b01bdc9baf89..b2a85ba13f08 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -2,22 +2,16 @@ menuconfig ARCH_INTEGRATOR
2 bool "ARM Ltd. Integrator family" 2 bool "ARM Ltd. Integrator family"
3 depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6 3 depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6
4 select ARM_AMBA 4 select ARM_AMBA
5 select ARM_PATCH_PHYS_VIRT if MMU
6 select AUTO_ZRELADDR
7 select COMMON_CLK
8 select COMMON_CLK_VERSATILE 5 select COMMON_CLK_VERSATILE
9 select GENERIC_CLOCKEVENTS
10 select HAVE_TCM 6 select HAVE_TCM
11 select ICST 7 select ICST
12 select MFD_SYSCON 8 select MFD_SYSCON
13 select MULTI_IRQ_HANDLER
14 select PLAT_VERSATILE 9 select PLAT_VERSATILE
15 select POWER_RESET 10 select POWER_RESET
16 select POWER_RESET_VERSATILE 11 select POWER_RESET_VERSATILE
17 select POWER_SUPPLY 12 select POWER_SUPPLY
18 select SOC_INTEGRATOR_CM 13 select SOC_INTEGRATOR_CM
19 select SPARSE_IRQ 14 select SPARSE_IRQ
20 select USE_OF
21 select VERSATILE_FPGA_IRQ 15 select VERSATILE_FPGA_IRQ
22 help 16 help
23 Support for ARM's Integrator platform. 17 Support for ARM's Integrator platform.
diff --git a/arch/arm/mach-integrator/Makefile.boot b/arch/arm/mach-integrator/Makefile.boot
deleted file mode 100644
index ff0a4b5b0a82..000000000000
--- a/arch/arm/mach-integrator/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
1 zreladdr-y += 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
4
diff --git a/arch/arm/mach-keystone/Makefile.boot b/arch/arm/mach-keystone/Makefile.boot
deleted file mode 100644
index f3835c43af61..000000000000
--- a/arch/arm/mach-keystone/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
1zreladdr-y := 0x80008000
diff --git a/arch/arm/mach-lpc32xx/Makefile b/arch/arm/mach-lpc32xx/Makefile
index f5db805ab958..c70709ada692 100644
--- a/arch/arm/mach-lpc32xx/Makefile
+++ b/arch/arm/mach-lpc32xx/Makefile
@@ -2,7 +2,6 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := timer.o irq.o common.o serial.o clock.o 5obj-y := irq.o common.o serial.o
6obj-y += pm.o suspend.o 6obj-y += pm.o suspend.o
7obj-y += phy3250.o 7obj-y += phy3250.o
8
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
deleted file mode 100644
index 661c8f4b2310..000000000000
--- a/arch/arm/mach-lpc32xx/clock.c
+++ /dev/null
@@ -1,1284 +0,0 @@
1/*
2 * arch/arm/mach-lpc32xx/clock.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19/*
20 * LPC32xx clock management driver overview
21 *
22 * The LPC32XX contains a number of high level system clocks that can be
23 * generated from different sources. These system clocks are used to
24 * generate the CPU and bus rates and the individual peripheral clocks in
25 * the system. When Linux is started by the boot loader, the system
26 * clocks are already running. Stopping a system clock during normal
27 * Linux operation should never be attempted, as peripherals that require
28 * those clocks will quit working (ie, DRAM).
29 *
30 * The LPC32xx high level clock tree looks as follows. Clocks marked with
31 * an asterisk are always on and cannot be disabled. Clocks marked with
32 * an ampersand can only be disabled in CPU suspend mode. Clocks marked
33 * with a caret are always on if it is the selected clock for the SYSCLK
34 * source. The clock that isn't used for SYSCLK can be enabled and
35 * disabled normally.
36 * 32KHz oscillator*
37 * / | \
38 * RTC* PLL397^ TOUCH
39 * /
40 * Main oscillator^ /
41 * | \ /
42 * | SYSCLK&
43 * | \
44 * | \
45 * USB_PLL HCLK_PLL&
46 * | | |
47 * USB host/device PCLK& |
48 * | |
49 * Peripherals
50 *
51 * The CPU and chip bus rates are derived from the HCLK PLL, which can
52 * generate various clock rates up to 266MHz and beyond. The internal bus
53 * rates (PCLK and HCLK) are generated from dividers based on the HCLK
54 * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
55 * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
56 * level clocks are based on either HCLK or PCLK, but have their own
57 * dividers as part of the IP itself. Because of this, the system clock
58 * rates should not be changed.
59 *
60 * The HCLK PLL is clocked from SYSCLK, which can be derived from the
61 * main oscillator or PLL397. PLL397 generates a rate that is 397 times
62 * the 32KHz oscillator rate. The main oscillator runs at the selected
63 * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
64 * is normally 13MHz, but depends on the selection of external crystals
65 * or oscillators. If USB operation is required, the main oscillator must
66 * be used in the system.
67 *
68 * Switching SYSCLK between sources during normal Linux operation is not
69 * supported. SYSCLK is preset in the bootloader. Because of the
70 * complexities of clock management during clock frequency changes,
71 * there are some limitations to the clock driver explained below:
72 * - The PLL397 and main oscillator can be enabled and disabled by the
73 * clk_enable() and clk_disable() functions unless SYSCLK is based
74 * on that clock. This allows the other oscillator that isn't driving
75 * the HCLK PLL to be used as another system clock that can be routed
76 * to an external pin.
77 * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
78 * this driver.
79 * - HCLK and PCLK rates cannot be changed as part of this driver.
80 * - Most peripherals have their own dividers are part of the peripheral
81 * block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
82 * will also impact the individual peripheral rates.
83 */
84
85#include <linux/export.h>
86#include <linux/kernel.h>
87#include <linux/list.h>
88#include <linux/errno.h>
89#include <linux/device.h>
90#include <linux/delay.h>
91#include <linux/err.h>
92#include <linux/clk.h>
93#include <linux/amba/bus.h>
94#include <linux/amba/clcd.h>
95#include <linux/clkdev.h>
96
97#include <mach/hardware.h>
98#include <mach/platform.h>
99#include "clock.h"
100#include "common.h"
101
102static DEFINE_SPINLOCK(global_clkregs_lock);
103
104static int usb_pll_enable, usb_pll_valid;
105
106static struct clk clk_armpll;
107static struct clk clk_usbpll;
108
109/*
110 * Post divider values for PLLs based on selected register value
111 */
112static const u32 pll_postdivs[4] = {1, 2, 4, 8};
113
114static unsigned long local_return_parent_rate(struct clk *clk)
115{
116 /*
117 * If a clock has a rate of 0, then it inherits it's parent
118 * clock rate
119 */
120 while (clk->rate == 0)
121 clk = clk->parent;
122
123 return clk->rate;
124}
125
126/* 32KHz clock has a fixed rate and is not stoppable */
127static struct clk osc_32KHz = {
128 .rate = LPC32XX_CLOCK_OSC_FREQ,
129 .get_rate = local_return_parent_rate,
130};
131
132static int local_pll397_enable(struct clk *clk, int enable)
133{
134 u32 reg;
135 unsigned long timeout = jiffies + msecs_to_jiffies(10);
136
137 reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
138
139 if (enable == 0) {
140 reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
141 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
142 } else {
143 /* Enable PLL397 */
144 reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
145 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
146
147 /* Wait for PLL397 lock */
148 while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
149 LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
150 time_before(jiffies, timeout))
151 cpu_relax();
152
153 if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
154 LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
155 return -ENODEV;
156 }
157
158 return 0;
159}
160
161static int local_oscmain_enable(struct clk *clk, int enable)
162{
163 u32 reg;
164 unsigned long timeout = jiffies + msecs_to_jiffies(10);
165
166 reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
167
168 if (enable == 0) {
169 reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
170 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
171 } else {
172 /* Enable main oscillator */
173 reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
174 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
175
176 /* Wait for main oscillator to start */
177 while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
178 LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
179 time_before(jiffies, timeout))
180 cpu_relax();
181
182 if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
183 LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
184 return -ENODEV;
185 }
186
187 return 0;
188}
189
190static struct clk osc_pll397 = {
191 .parent = &osc_32KHz,
192 .enable = local_pll397_enable,
193 .rate = LPC32XX_CLOCK_OSC_FREQ * 397,
194 .get_rate = local_return_parent_rate,
195};
196
197static struct clk osc_main = {
198 .enable = local_oscmain_enable,
199 .rate = LPC32XX_MAIN_OSC_FREQ,
200 .get_rate = local_return_parent_rate,
201};
202
203static struct clk clk_sys;
204
205/*
206 * Convert a PLL register value to a PLL output frequency
207 */
208u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
209{
210 struct clk_pll_setup pllcfg;
211
212 pllcfg.cco_bypass_b15 = 0;
213 pllcfg.direct_output_b14 = 0;
214 pllcfg.fdbk_div_ctrl_b13 = 0;
215 if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
216 pllcfg.cco_bypass_b15 = 1;
217 if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
218 pllcfg.direct_output_b14 = 1;
219 if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
220 pllcfg.fdbk_div_ctrl_b13 = 1;
221 pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
222 pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
223 pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];
224
225 return clk_check_pll_setup(inputclk, &pllcfg);
226}
227
228/*
229 * Setup the HCLK PLL with a PLL structure
230 */
231static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
232{
233 u32 tv, tmp = 0;
234
235 if (PllSetup->analog_on != 0)
236 tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
237 if (PllSetup->cco_bypass_b15 != 0)
238 tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
239 if (PllSetup->direct_output_b14 != 0)
240 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
241 if (PllSetup->fdbk_div_ctrl_b13 != 0)
242 tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
243
244 tv = ffs(PllSetup->pll_p) - 1;
245 if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3))
246 return 0;
247
248 tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
249 tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
250 tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
251
252 return tmp;
253}
254
255/*
256 * Update the ARM core PLL frequency rate variable from the actual PLL setting
257 */
258static void local_update_armpll_rate(void)
259{
260 u32 clkin, pllreg;
261
262 clkin = clk_armpll.parent->rate;
263 pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
264
265 clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
266}
267
268/*
269 * Find a PLL configuration for the selected input frequency
270 */
271static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq,
272 struct clk_pll_setup *pllsetup)
273{
274 u32 ifreq, freqtol, m, n, p, fclkout;
275
276 /* Determine frequency tolerance limits */
277 freqtol = target_freq / 250;
278 ifreq = pllin_freq;
279
280 /* Is direct bypass mode possible? */
281 if (abs(pllin_freq - target_freq) <= freqtol) {
282 pllsetup->analog_on = 0;
283 pllsetup->cco_bypass_b15 = 1;
284 pllsetup->direct_output_b14 = 1;
285 pllsetup->fdbk_div_ctrl_b13 = 1;
286 pllsetup->pll_p = pll_postdivs[0];
287 pllsetup->pll_n = 1;
288 pllsetup->pll_m = 1;
289 return clk_check_pll_setup(ifreq, pllsetup);
290 } else if (target_freq <= ifreq) {
291 pllsetup->analog_on = 0;
292 pllsetup->cco_bypass_b15 = 1;
293 pllsetup->direct_output_b14 = 0;
294 pllsetup->fdbk_div_ctrl_b13 = 1;
295 pllsetup->pll_n = 1;
296 pllsetup->pll_m = 1;
297 for (p = 0; p <= 3; p++) {
298 pllsetup->pll_p = pll_postdivs[p];
299 fclkout = clk_check_pll_setup(ifreq, pllsetup);
300 if (abs(target_freq - fclkout) <= freqtol)
301 return fclkout;
302 }
303 }
304
305 /* Is direct mode possible? */
306 pllsetup->analog_on = 1;
307 pllsetup->cco_bypass_b15 = 0;
308 pllsetup->direct_output_b14 = 1;
309 pllsetup->fdbk_div_ctrl_b13 = 0;
310 pllsetup->pll_p = pll_postdivs[0];
311 for (m = 1; m <= 256; m++) {
312 for (n = 1; n <= 4; n++) {
313 /* Compute output frequency for this value */
314 pllsetup->pll_n = n;
315 pllsetup->pll_m = m;
316 fclkout = clk_check_pll_setup(ifreq,
317 pllsetup);
318 if (abs(target_freq - fclkout) <=
319 freqtol)
320 return fclkout;
321 }
322 }
323
324 /* Is integer mode possible? */
325 pllsetup->analog_on = 1;
326 pllsetup->cco_bypass_b15 = 0;
327 pllsetup->direct_output_b14 = 0;
328 pllsetup->fdbk_div_ctrl_b13 = 1;
329 for (m = 1; m <= 256; m++) {
330 for (n = 1; n <= 4; n++) {
331 for (p = 0; p < 4; p++) {
332 /* Compute output frequency */
333 pllsetup->pll_p = pll_postdivs[p];
334 pllsetup->pll_n = n;
335 pllsetup->pll_m = m;
336 fclkout = clk_check_pll_setup(
337 ifreq, pllsetup);
338 if (abs(target_freq - fclkout) <= freqtol)
339 return fclkout;
340 }
341 }
342 }
343
344 /* Try non-integer mode */
345 pllsetup->analog_on = 1;
346 pllsetup->cco_bypass_b15 = 0;
347 pllsetup->direct_output_b14 = 0;
348 pllsetup->fdbk_div_ctrl_b13 = 0;
349 for (m = 1; m <= 256; m++) {
350 for (n = 1; n <= 4; n++) {
351 for (p = 0; p < 4; p++) {
352 /* Compute output frequency */
353 pllsetup->pll_p = pll_postdivs[p];
354 pllsetup->pll_n = n;
355 pllsetup->pll_m = m;
356 fclkout = clk_check_pll_setup(
357 ifreq, pllsetup);
358 if (abs(target_freq - fclkout) <= freqtol)
359 return fclkout;
360 }
361 }
362 }
363
364 return 0;
365}
366
367static struct clk clk_armpll = {
368 .parent = &clk_sys,
369 .get_rate = local_return_parent_rate,
370};
371
372/*
373 * Setup the USB PLL with a PLL structure
374 */
375static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
376{
377 u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
378
379 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF;
380 reg |= tmp;
381 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
382
383 return clk_check_pll_setup(clk_usbpll.parent->rate,
384 pHCLKPllSetup);
385}
386
387static int local_usbpll_enable(struct clk *clk, int enable)
388{
389 u32 reg;
390 int ret = 0;
391 unsigned long timeout = jiffies + msecs_to_jiffies(20);
392
393 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
394
395 __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN2 |
396 LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
397 LPC32XX_CLKPWR_USB_CTRL);
398 __raw_writel(reg & ~LPC32XX_CLKPWR_USBCTRL_CLK_EN1,
399 LPC32XX_CLKPWR_USB_CTRL);
400
401 if (enable && usb_pll_valid && usb_pll_enable) {
402 ret = -ENODEV;
403 /*
404 * If the PLL rate has been previously set, then the rate
405 * in the PLL register is valid and can be enabled here.
406 * Otherwise, it needs to be enabled as part of setrate.
407 */
408
409 /*
410 * Gate clock into PLL
411 */
412 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
413 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
414
415 /*
416 * Enable PLL
417 */
418 reg |= LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP;
419 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
420
421 /*
422 * Wait for PLL to lock
423 */
424 while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
425 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
426 if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
427 ret = 0;
428 else
429 udelay(10);
430 }
431
432 /*
433 * Gate clock from PLL if PLL is locked
434 */
435 if (ret == 0) {
436 __raw_writel(reg | LPC32XX_CLKPWR_USBCTRL_CLK_EN2,
437 LPC32XX_CLKPWR_USB_CTRL);
438 } else {
439 __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
440 LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
441 LPC32XX_CLKPWR_USB_CTRL);
442 }
443 } else if ((enable == 0) && usb_pll_valid && usb_pll_enable) {
444 usb_pll_valid = 0;
445 usb_pll_enable = 0;
446 }
447
448 return ret;
449}
450
451static unsigned long local_usbpll_round_rate(struct clk *clk,
452 unsigned long rate)
453{
454 u32 clkin, usbdiv;
455 struct clk_pll_setup pllsetup;
456
457 /*
458 * Unlike other clocks, this clock has a KHz input rate, so bump
459 * it up to work with the PLL function
460 */
461 rate = rate * 1000;
462
463 clkin = clk->get_rate(clk);
464 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
465 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
466 clkin = clkin / usbdiv;
467
468 /* Try to find a good rate setup */
469 if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
470 return 0;
471
472 return clk_check_pll_setup(clkin, &pllsetup);
473}
474
475static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
476{
477 int ret = -ENODEV;
478 u32 clkin, usbdiv;
479 struct clk_pll_setup pllsetup;
480
481 /*
482 * Unlike other clocks, this clock has a KHz input rate, so bump
483 * it up to work with the PLL function
484 */
485 rate = rate * 1000;
486
487 clkin = clk->get_rate(clk->parent);
488 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
489 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
490 clkin = clkin / usbdiv;
491
492 /* Try to find a good rate setup */
493 if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
494 return -EINVAL;
495
496 /*
497 * Disable PLL clocks during PLL change
498 */
499 local_usbpll_enable(clk, 0);
500 pllsetup.analog_on = 0;
501 local_clk_usbpll_setup(&pllsetup);
502
503 /*
504 * Start USB PLL and check PLL status
505 */
506
507 usb_pll_valid = 1;
508 usb_pll_enable = 1;
509
510 ret = local_usbpll_enable(clk, 1);
511 if (ret >= 0)
512 clk->rate = clk_check_pll_setup(clkin, &pllsetup);
513
514 return ret;
515}
516
517static struct clk clk_usbpll = {
518 .parent = &osc_main,
519 .set_rate = local_usbpll_set_rate,
520 .enable = local_usbpll_enable,
521 .rate = 48000, /* In KHz */
522 .get_rate = local_return_parent_rate,
523 .round_rate = local_usbpll_round_rate,
524};
525
526static u32 clk_get_hclk_div(void)
527{
528 static const u32 hclkdivs[4] = {1, 2, 4, 4};
529 return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
530 __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))];
531}
532
533static struct clk clk_hclk = {
534 .parent = &clk_armpll,
535 .get_rate = local_return_parent_rate,
536};
537
538static struct clk clk_pclk = {
539 .parent = &clk_armpll,
540 .get_rate = local_return_parent_rate,
541};
542
543static int local_onoff_enable(struct clk *clk, int enable)
544{
545 u32 tmp;
546
547 tmp = __raw_readl(clk->enable_reg);
548
549 if (enable == 0)
550 tmp &= ~clk->enable_mask;
551 else
552 tmp |= clk->enable_mask;
553
554 __raw_writel(tmp, clk->enable_reg);
555
556 return 0;
557}
558
559/* Peripheral clock sources */
560static struct clk clk_timer0 = {
561 .parent = &clk_pclk,
562 .enable = local_onoff_enable,
563 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
564 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
565 .get_rate = local_return_parent_rate,
566};
567static struct clk clk_timer1 = {
568 .parent = &clk_pclk,
569 .enable = local_onoff_enable,
570 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
571 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
572 .get_rate = local_return_parent_rate,
573};
574static struct clk clk_timer2 = {
575 .parent = &clk_pclk,
576 .enable = local_onoff_enable,
577 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
578 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
579 .get_rate = local_return_parent_rate,
580};
581static struct clk clk_timer3 = {
582 .parent = &clk_pclk,
583 .enable = local_onoff_enable,
584 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
585 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
586 .get_rate = local_return_parent_rate,
587};
588static struct clk clk_mpwm = {
589 .parent = &clk_pclk,
590 .enable = local_onoff_enable,
591 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
592 .enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN,
593 .get_rate = local_return_parent_rate,
594};
595static struct clk clk_wdt = {
596 .parent = &clk_pclk,
597 .enable = local_onoff_enable,
598 .enable_reg = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
599 .enable_mask = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
600 .get_rate = local_return_parent_rate,
601};
602static struct clk clk_vfp9 = {
603 .parent = &clk_pclk,
604 .enable = local_onoff_enable,
605 .enable_reg = LPC32XX_CLKPWR_DEBUG_CTRL,
606 .enable_mask = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
607 .get_rate = local_return_parent_rate,
608};
609static struct clk clk_dma = {
610 .parent = &clk_hclk,
611 .enable = local_onoff_enable,
612 .enable_reg = LPC32XX_CLKPWR_DMA_CLK_CTRL,
613 .enable_mask = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
614 .get_rate = local_return_parent_rate,
615};
616
617static struct clk clk_pwm = {
618 .parent = &clk_pclk,
619 .enable = local_onoff_enable,
620 .enable_reg = LPC32XX_CLKPWR_PWM_CLK_CTRL,
621 .enable_mask = LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN |
622 LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK |
623 LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(1) |
624 LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN |
625 LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK |
626 LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(1),
627 .get_rate = local_return_parent_rate,
628};
629
630static struct clk clk_uart3 = {
631 .parent = &clk_pclk,
632 .enable = local_onoff_enable,
633 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
634 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
635 .get_rate = local_return_parent_rate,
636};
637
638static struct clk clk_uart4 = {
639 .parent = &clk_pclk,
640 .enable = local_onoff_enable,
641 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
642 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
643 .get_rate = local_return_parent_rate,
644};
645
646static struct clk clk_uart5 = {
647 .parent = &clk_pclk,
648 .enable = local_onoff_enable,
649 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
650 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
651 .get_rate = local_return_parent_rate,
652};
653
654static struct clk clk_uart6 = {
655 .parent = &clk_pclk,
656 .enable = local_onoff_enable,
657 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
658 .enable_mask = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
659 .get_rate = local_return_parent_rate,
660};
661
662static struct clk clk_i2c0 = {
663 .parent = &clk_hclk,
664 .enable = local_onoff_enable,
665 .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
666 .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
667 .get_rate = local_return_parent_rate,
668};
669
670static struct clk clk_i2c1 = {
671 .parent = &clk_hclk,
672 .enable = local_onoff_enable,
673 .enable_reg = LPC32XX_CLKPWR_I2C_CLK_CTRL,
674 .enable_mask = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
675 .get_rate = local_return_parent_rate,
676};
677
678static struct clk clk_i2c2 = {
679 .parent = &clk_pclk,
680 .enable = local_onoff_enable,
681 .enable_reg = io_p2v(LPC32XX_USB_BASE + 0xFF4),
682 .enable_mask = 0x4,
683 .get_rate = local_return_parent_rate,
684};
685
686static struct clk clk_ssp0 = {
687 .parent = &clk_hclk,
688 .enable = local_onoff_enable,
689 .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
690 .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
691 .get_rate = local_return_parent_rate,
692};
693
694static struct clk clk_ssp1 = {
695 .parent = &clk_hclk,
696 .enable = local_onoff_enable,
697 .enable_reg = LPC32XX_CLKPWR_SSP_CLK_CTRL,
698 .enable_mask = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
699 .get_rate = local_return_parent_rate,
700};
701
702static struct clk clk_kscan = {
703 .parent = &osc_32KHz,
704 .enable = local_onoff_enable,
705 .enable_reg = LPC32XX_CLKPWR_KEY_CLK_CTRL,
706 .enable_mask = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
707 .get_rate = local_return_parent_rate,
708};
709
710static struct clk clk_nand = {
711 .parent = &clk_hclk,
712 .enable = local_onoff_enable,
713 .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
714 .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN |
715 LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
716 .get_rate = local_return_parent_rate,
717};
718
719static struct clk clk_nand_mlc = {
720 .parent = &clk_hclk,
721 .enable = local_onoff_enable,
722 .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
723 .enable_mask = LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN |
724 LPC32XX_CLKPWR_NANDCLK_DMA_INT |
725 LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC,
726 .get_rate = local_return_parent_rate,
727};
728
729static struct clk clk_i2s0 = {
730 .parent = &clk_hclk,
731 .enable = local_onoff_enable,
732 .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
733 .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
734 .get_rate = local_return_parent_rate,
735};
736
737static struct clk clk_i2s1 = {
738 .parent = &clk_hclk,
739 .enable = local_onoff_enable,
740 .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
741 .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN |
742 LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA,
743 .get_rate = local_return_parent_rate,
744};
745
746static struct clk clk_net = {
747 .parent = &clk_hclk,
748 .enable = local_onoff_enable,
749 .enable_reg = LPC32XX_CLKPWR_MACCLK_CTRL,
750 .enable_mask = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
751 LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
752 LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
753 .get_rate = local_return_parent_rate,
754};
755
756static struct clk clk_rtc = {
757 .parent = &osc_32KHz,
758 .rate = 1, /* 1 Hz */
759 .get_rate = local_return_parent_rate,
760};
761
762static int local_usb_enable(struct clk *clk, int enable)
763{
764 u32 tmp;
765
766 if (enable) {
767 /* Set up I2C pull levels */
768 tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
769 tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE;
770 __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
771 }
772
773 return local_onoff_enable(clk, enable);
774}
775
776static struct clk clk_usbd = {
777 .parent = &clk_usbpll,
778 .enable = local_usb_enable,
779 .enable_reg = LPC32XX_CLKPWR_USB_CTRL,
780 .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
781 .get_rate = local_return_parent_rate,
782};
783
784#define OTG_ALWAYS_MASK (LPC32XX_USB_OTG_OTG_CLOCK_ON | \
785 LPC32XX_USB_OTG_I2C_CLOCK_ON)
786
787static int local_usb_otg_enable(struct clk *clk, int enable)
788{
789 int to = 1000;
790
791 if (enable) {
792 __raw_writel(clk->enable_mask, clk->enable_reg);
793
794 while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) &
795 clk->enable_mask) != clk->enable_mask) && (to > 0))
796 to--;
797 } else {
798 __raw_writel(OTG_ALWAYS_MASK, clk->enable_reg);
799
800 while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) &
801 OTG_ALWAYS_MASK) != OTG_ALWAYS_MASK) && (to > 0))
802 to--;
803 }
804
805 if (to)
806 return 0;
807 else
808 return -1;
809}
810
811static struct clk clk_usb_otg_dev = {
812 .parent = &clk_usbpll,
813 .enable = local_usb_otg_enable,
814 .enable_reg = LPC32XX_USB_OTG_CLK_CTRL,
815 .enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON |
816 LPC32XX_USB_OTG_OTG_CLOCK_ON |
817 LPC32XX_USB_OTG_DEV_CLOCK_ON |
818 LPC32XX_USB_OTG_I2C_CLOCK_ON,
819 .get_rate = local_return_parent_rate,
820};
821
822static struct clk clk_usb_otg_host = {
823 .parent = &clk_usbpll,
824 .enable = local_usb_otg_enable,
825 .enable_reg = LPC32XX_USB_OTG_CLK_CTRL,
826 .enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON |
827 LPC32XX_USB_OTG_OTG_CLOCK_ON |
828 LPC32XX_USB_OTG_HOST_CLOCK_ON |
829 LPC32XX_USB_OTG_I2C_CLOCK_ON,
830 .get_rate = local_return_parent_rate,
831};
832
833static int tsc_onoff_enable(struct clk *clk, int enable)
834{
835 u32 tmp;
836
837 /* Make sure 32KHz clock is the selected clock */
838 tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
839 tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
840 __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
841
842 if (enable == 0)
843 __raw_writel(0, clk->enable_reg);
844 else
845 __raw_writel(clk->enable_mask, clk->enable_reg);
846
847 return 0;
848}
849
850static struct clk clk_tsc = {
851 .parent = &osc_32KHz,
852 .enable = tsc_onoff_enable,
853 .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
854 .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
855 .get_rate = local_return_parent_rate,
856};
857
858static int adc_onoff_enable(struct clk *clk, int enable)
859{
860 u32 tmp;
861 u32 divider;
862
863 /* Use PERIPH_CLOCK */
864 tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
865 tmp |= LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
866 /*
867 * Set clock divider so that we have equal to or less than
868 * 4.5MHz clock at ADC
869 */
870 divider = clk->get_rate(clk) / 4500000 + 1;
871 tmp |= divider;
872 __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
873
874 /* synchronize rate of this clock w/ actual HW setting */
875 clk->rate = clk->get_rate(clk->parent) / divider;
876
877 if (enable == 0)
878 __raw_writel(0, clk->enable_reg);
879 else
880 __raw_writel(clk->enable_mask, clk->enable_reg);
881
882 return 0;
883}
884
885static struct clk clk_adc = {
886 .parent = &clk_pclk,
887 .enable = adc_onoff_enable,
888 .enable_reg = LPC32XX_CLKPWR_ADC_CLK_CTRL,
889 .enable_mask = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
890 .get_rate = local_return_parent_rate,
891};
892
893static int mmc_onoff_enable(struct clk *clk, int enable)
894{
895 u32 tmp;
896
897 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
898 ~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
899 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN |
900 LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS |
901 LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS |
902 LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS |
903 LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS);
904
905 /* If rate is 0, disable clock */
906 if (enable != 0)
907 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
908 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
909
910 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
911
912 return 0;
913}
914
915static unsigned long mmc_get_rate(struct clk *clk)
916{
917 u32 div, rate, oldclk;
918
919 /* The MMC clock must be on when accessing an MMC register */
920 oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
921 __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
922 LPC32XX_CLKPWR_MS_CTRL);
923 div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
924 __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
925
926 /* Get the parent clock rate */
927 rate = clk->parent->get_rate(clk->parent);
928
929 /* Get the MMC controller clock divider value */
930 div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
931
932 if (!div)
933 div = 1;
934
935 return rate / div;
936}
937
938static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
939{
940 unsigned long div, prate;
941
942 /* Get the parent clock rate */
943 prate = clk->parent->get_rate(clk->parent);
944
945 if (rate >= prate)
946 return prate;
947
948 div = prate / rate;
949 if (div > 0xf)
950 div = 0xf;
951
952 return prate / div;
953}
954
955static int mmc_set_rate(struct clk *clk, unsigned long rate)
956{
957 u32 tmp;
958 unsigned long prate, div, crate = mmc_round_rate(clk, rate);
959
960 prate = clk->parent->get_rate(clk->parent);
961
962 div = prate / crate;
963
964 /* The MMC clock must be on when accessing an MMC register */
965 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
966 ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
967 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div) |
968 LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
969 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
970
971 return 0;
972}
973
974static struct clk clk_mmc = {
975 .parent = &clk_armpll,
976 .set_rate = mmc_set_rate,
977 .get_rate = mmc_get_rate,
978 .round_rate = mmc_round_rate,
979 .enable = mmc_onoff_enable,
980 .enable_reg = LPC32XX_CLKPWR_MS_CTRL,
981 .enable_mask = LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
982};
983
984static unsigned long clcd_get_rate(struct clk *clk)
985{
986 u32 tmp, div, rate, oldclk;
987
988 /* The LCD clock must be on when accessing an LCD register */
989 oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
990 __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
991 LPC32XX_CLKPWR_LCDCLK_CTRL);
992 tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
993 __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
994
995 rate = clk->parent->get_rate(clk->parent);
996
997 /* Only supports internal clocking */
998 if (tmp & TIM2_BCD)
999 return rate;
1000
1001 div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22);
1002 tmp = rate / (2 + div);
1003
1004 return tmp;
1005}
1006
1007static int clcd_set_rate(struct clk *clk, unsigned long rate)
1008{
1009 u32 tmp, prate, div, oldclk;
1010
1011 /* The LCD clock must be on when accessing an LCD register */
1012 oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
1013 __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
1014 LPC32XX_CLKPWR_LCDCLK_CTRL);
1015
1016 tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD;
1017 prate = clk->parent->get_rate(clk->parent);
1018
1019 if (rate < prate) {
1020 /* Find closest divider */
1021 div = prate / rate;
1022 if (div >= 2) {
1023 div -= 2;
1024 tmp &= ~TIM2_BCD;
1025 }
1026
1027 tmp &= ~(0xF800001F);
1028 tmp |= (div & 0x1F);
1029 tmp |= (((div >> 5) & 0x1F) << 27);
1030 }
1031
1032 __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
1033 __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
1034
1035 return 0;
1036}
1037
1038static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate)
1039{
1040 u32 prate, div;
1041
1042 prate = clk->parent->get_rate(clk->parent);
1043
1044 if (rate >= prate)
1045 rate = prate;
1046 else {
1047 div = prate / rate;
1048 if (div > 0x3ff)
1049 div = 0x3ff;
1050
1051 rate = prate / div;
1052 }
1053
1054 return rate;
1055}
1056
1057static struct clk clk_lcd = {
1058 .parent = &clk_hclk,
1059 .set_rate = clcd_set_rate,
1060 .get_rate = clcd_get_rate,
1061 .round_rate = clcd_round_rate,
1062 .enable = local_onoff_enable,
1063 .enable_reg = LPC32XX_CLKPWR_LCDCLK_CTRL,
1064 .enable_mask = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
1065};
1066
1067static void local_clk_disable(struct clk *clk)
1068{
1069 /* Don't attempt to disable clock if it has no users */
1070 if (clk->usecount > 0) {
1071 clk->usecount--;
1072
1073 /* Only disable clock when it has no more users */
1074 if ((clk->usecount == 0) && (clk->enable))
1075 clk->enable(clk, 0);
1076
1077 /* Check parent clocks, they may need to be disabled too */
1078 if (clk->parent)
1079 local_clk_disable(clk->parent);
1080 }
1081}
1082
1083static int local_clk_enable(struct clk *clk)
1084{
1085 int ret = 0;
1086
1087 /* Enable parent clocks first and update use counts */
1088 if (clk->parent)
1089 ret = local_clk_enable(clk->parent);
1090
1091 if (!ret) {
1092 /* Only enable clock if it's currently disabled */
1093 if ((clk->usecount == 0) && (clk->enable))
1094 ret = clk->enable(clk, 1);
1095
1096 if (!ret)
1097 clk->usecount++;
1098 else if (clk->parent)
1099 local_clk_disable(clk->parent);
1100 }
1101
1102 return ret;
1103}
1104
1105/*
1106 * clk_enable - inform the system when the clock source should be running.
1107 */
1108int clk_enable(struct clk *clk)
1109{
1110 int ret;
1111 unsigned long flags;
1112
1113 spin_lock_irqsave(&global_clkregs_lock, flags);
1114 ret = local_clk_enable(clk);
1115 spin_unlock_irqrestore(&global_clkregs_lock, flags);
1116
1117 return ret;
1118}
1119EXPORT_SYMBOL(clk_enable);
1120
1121/*
1122 * clk_disable - inform the system when the clock source is no longer required
1123 */
1124void clk_disable(struct clk *clk)
1125{
1126 unsigned long flags;
1127
1128 spin_lock_irqsave(&global_clkregs_lock, flags);
1129 local_clk_disable(clk);
1130 spin_unlock_irqrestore(&global_clkregs_lock, flags);
1131}
1132EXPORT_SYMBOL(clk_disable);
1133
1134/*
1135 * clk_get_rate - obtain the current clock rate (in Hz) for a clock source
1136 */
1137unsigned long clk_get_rate(struct clk *clk)
1138{
1139 return clk->get_rate(clk);
1140}
1141EXPORT_SYMBOL(clk_get_rate);
1142
1143/*
1144 * clk_set_rate - set the clock rate for a clock source
1145 */
1146int clk_set_rate(struct clk *clk, unsigned long rate)
1147{
1148 int ret = -EINVAL;
1149
1150 /*
1151 * Most system clocks can only be enabled or disabled, with
1152 * the actual rate set as part of the peripheral dividers
1153 * instead of high level clock control
1154 */
1155 if (clk->set_rate)
1156 ret = clk->set_rate(clk, rate);
1157
1158 return ret;
1159}
1160EXPORT_SYMBOL(clk_set_rate);
1161
1162/*
1163 * clk_round_rate - adjust a rate to the exact rate a clock can provide
1164 */
1165long clk_round_rate(struct clk *clk, unsigned long rate)
1166{
1167 if (clk->round_rate)
1168 rate = clk->round_rate(clk, rate);
1169 else
1170 rate = clk->get_rate(clk);
1171
1172 return rate;
1173}
1174EXPORT_SYMBOL(clk_round_rate);
1175
1176/*
1177 * clk_set_parent - set the parent clock source for this clock
1178 */
1179int clk_set_parent(struct clk *clk, struct clk *parent)
1180{
1181 /* Clock re-parenting is not supported */
1182 return -EINVAL;
1183}
1184EXPORT_SYMBOL(clk_set_parent);
1185
1186/*
1187 * clk_get_parent - get the parent clock source for this clock
1188 */
1189struct clk *clk_get_parent(struct clk *clk)
1190{
1191 return clk->parent;
1192}
1193EXPORT_SYMBOL(clk_get_parent);
1194
1195static struct clk_lookup lookups[] = {
1196 CLKDEV_INIT(NULL, "osc_32KHz", &osc_32KHz),
1197 CLKDEV_INIT(NULL, "osc_pll397", &osc_pll397),
1198 CLKDEV_INIT(NULL, "osc_main", &osc_main),
1199 CLKDEV_INIT(NULL, "sys_ck", &clk_sys),
1200 CLKDEV_INIT(NULL, "arm_pll_ck", &clk_armpll),
1201 CLKDEV_INIT(NULL, "ck_pll5", &clk_usbpll),
1202 CLKDEV_INIT(NULL, "hclk_ck", &clk_hclk),
1203 CLKDEV_INIT(NULL, "pclk_ck", &clk_pclk),
1204 CLKDEV_INIT(NULL, "timer0_ck", &clk_timer0),
1205 CLKDEV_INIT(NULL, "timer1_ck", &clk_timer1),
1206 CLKDEV_INIT(NULL, "timer2_ck", &clk_timer2),
1207 CLKDEV_INIT(NULL, "timer3_ck", &clk_timer3),
1208 CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9),
1209 CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
1210 CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
1211 CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
1212 CLKDEV_INIT("400e8000.mpwm", NULL, &clk_mpwm),
1213 CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
1214 CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
1215 CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),
1216 CLKDEV_INIT(NULL, "uart6_ck", &clk_uart6),
1217 CLKDEV_INIT("400a0000.i2c", NULL, &clk_i2c0),
1218 CLKDEV_INIT("400a8000.i2c", NULL, &clk_i2c1),
1219 CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2),
1220 CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
1221 CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
1222 CLKDEV_INIT("40050000.key", NULL, &clk_kscan),
1223 CLKDEV_INIT("20020000.flash", NULL, &clk_nand),
1224 CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc),
1225 CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
1226 CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0),
1227 CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1),
1228 CLKDEV_INIT("40048000.tsc", NULL, &clk_tsc),
1229 CLKDEV_INIT("20098000.sd", NULL, &clk_mmc),
1230 CLKDEV_INIT("31060000.ethernet", NULL, &clk_net),
1231 CLKDEV_INIT("dev:clcd", NULL, &clk_lcd),
1232 CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd),
1233 CLKDEV_INIT("31020000.ohci", "ck_usbd", &clk_usbd),
1234 CLKDEV_INIT("31020000.usbd", "ck_usb_otg", &clk_usb_otg_dev),
1235 CLKDEV_INIT("31020000.ohci", "ck_usb_otg", &clk_usb_otg_host),
1236 CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc),
1237};
1238
1239static int __init clk_init(void)
1240{
1241 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
1242
1243 /*
1244 * Setup muxed SYSCLK for HCLK PLL base -this selects the
1245 * parent clock used for the ARM PLL and is used to derive
1246 * the many system clock rates in the device.
1247 */
1248 if (clk_is_sysclk_mainosc() != 0)
1249 clk_sys.parent = &osc_main;
1250 else
1251 clk_sys.parent = &osc_pll397;
1252
1253 clk_sys.rate = clk_sys.parent->rate;
1254
1255 /* Compute the current ARM PLL and USB PLL frequencies */
1256 local_update_armpll_rate();
1257
1258 /* Compute HCLK and PCLK bus rates */
1259 clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div();
1260 clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div();
1261
1262 /*
1263 * Enable system clocks - this step is somewhat formal, as the
1264 * clocks are already running, but it does get the clock data
1265 * inline with the actual system state. Never disable these
1266 * clocks as they will only stop if the system is going to sleep.
1267 * In that case, the chip/system power management functions will
1268 * handle clock gating.
1269 */
1270 if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk))
1271 printk(KERN_ERR "Error enabling system HCLK and PCLK\n");
1272
1273 /*
1274 * Timers 0 and 1 were enabled and are being used by the high
1275 * resolution tick function prior to this driver being initialized.
1276 * Tag them now as used.
1277 */
1278 if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1))
1279 printk(KERN_ERR "Error enabling timer tick clocks\n");
1280
1281 return 0;
1282}
1283core_initcall(clk_init);
1284
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index e6f03783ad73..b2f9e226febe 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -36,7 +36,6 @@
36#include <linux/clk.h> 36#include <linux/clk.h>
37#include <linux/mtd/lpc32xx_slc.h> 37#include <linux/mtd/lpc32xx_slc.h>
38#include <linux/mtd/lpc32xx_mlc.h> 38#include <linux/mtd/lpc32xx_mlc.h>
39#include <linux/platform_data/gpio-lpc32xx.h>
40 39
41#include <asm/setup.h> 40#include <asm/setup.h>
42#include <asm/mach-types.h> 41#include <asm/mach-types.h>
@@ -48,13 +47,6 @@
48#include "common.h" 47#include "common.h"
49 48
50/* 49/*
51 * Mapped GPIOLIB GPIOs
52 */
53#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
54#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
55#define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
56
57/*
58 * AMBA LCD controller 50 * AMBA LCD controller
59 */ 51 */
60static struct clcd_panel conn_lcd_panel = { 52static struct clcd_panel conn_lcd_panel = {
@@ -97,20 +89,6 @@ static int lpc32xx_clcd_setup(struct clcd_fb *fb)
97 fb->fb.fix.smem_len = PANEL_SIZE; 89 fb->fb.fix.smem_len = PANEL_SIZE;
98 fb->panel = &conn_lcd_panel; 90 fb->panel = &conn_lcd_panel;
99 91
100 if (gpio_request(LCD_POWER_GPIO, "LCD power"))
101 printk(KERN_ERR "Error requesting gpio %u",
102 LCD_POWER_GPIO);
103 else if (gpio_direction_output(LCD_POWER_GPIO, 1))
104 printk(KERN_ERR "Error setting gpio %u to output",
105 LCD_POWER_GPIO);
106
107 if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
108 printk(KERN_ERR "Error requesting gpio %u",
109 BKL_POWER_GPIO);
110 else if (gpio_direction_output(BKL_POWER_GPIO, 1))
111 printk(KERN_ERR "Error setting gpio %u to output",
112 BKL_POWER_GPIO);
113
114 return 0; 92 return 0;
115} 93}
116 94
@@ -126,29 +104,10 @@ static void lpc32xx_clcd_remove(struct clcd_fb *fb)
126 fb->fb.fix.smem_start); 104 fb->fb.fix.smem_start);
127} 105}
128 106
129/*
130 * On some early LCD modules (1307.0), the backlight logic is inverted.
131 * For those board variants, swap the disable and enable states for
132 * BKL_POWER_GPIO.
133*/
134static void clcd_disable(struct clcd_fb *fb)
135{
136 gpio_set_value(BKL_POWER_GPIO, 0);
137 gpio_set_value(LCD_POWER_GPIO, 0);
138}
139
140static void clcd_enable(struct clcd_fb *fb)
141{
142 gpio_set_value(BKL_POWER_GPIO, 1);
143 gpio_set_value(LCD_POWER_GPIO, 1);
144}
145
146static struct clcd_board lpc32xx_clcd_data = { 107static struct clcd_board lpc32xx_clcd_data = {
147 .name = "Phytec LCD", 108 .name = "Phytec LCD",
148 .check = clcdfb_check, 109 .check = clcdfb_check,
149 .decode = clcdfb_decode, 110 .decode = clcdfb_decode,
150 .disable = clcd_disable,
151 .enable = clcd_enable,
152 .setup = lpc32xx_clcd_setup, 111 .setup = lpc32xx_clcd_setup,
153 .mmap = lpc32xx_clcd_mmap, 112 .mmap = lpc32xx_clcd_mmap,
154 .remove = lpc32xx_clcd_remove, 113 .remove = lpc32xx_clcd_remove,
@@ -187,20 +146,9 @@ static struct pl08x_platform_data pl08x_pd = {
187 .mem_buses = PL08X_AHB1, 146 .mem_buses = PL08X_AHB1,
188}; 147};
189 148
190static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios)
191{
192 /* Only on and off are supported */
193 if (ios->power_mode == MMC_POWER_OFF)
194 gpio_set_value(MMC_PWR_ENABLE_GPIO, 0);
195 else
196 gpio_set_value(MMC_PWR_ENABLE_GPIO, 1);
197 return 0;
198}
199
200static struct mmci_platform_data lpc32xx_mmci_data = { 149static struct mmci_platform_data lpc32xx_mmci_data = {
201 .ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 | 150 .ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 |
202 MMC_VDD_32_33 | MMC_VDD_33_34, 151 MMC_VDD_32_33 | MMC_VDD_33_34,
203 .ios_handler = mmc_handle_ios,
204}; 152};
205 153
206static struct lpc32xx_slc_platform_data lpc32xx_slc_data = { 154static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
@@ -259,7 +207,6 @@ DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
259 .atag_offset = 0x100, 207 .atag_offset = 0x100,
260 .map_io = lpc32xx_map_io, 208 .map_io = lpc32xx_map_io,
261 .init_irq = lpc32xx_init_irq, 209 .init_irq = lpc32xx_init_irq,
262 .init_time = lpc32xx_timer_init,
263 .init_machine = lpc3250_machine_init, 210 .init_machine = lpc3250_machine_init,
264 .dt_compat = lpc32xx_dt_compat, 211 .dt_compat = lpc32xx_dt_compat,
265MACHINE_END 212MACHINE_END
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index 05621a29fba2..1931229a1eaa 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -76,9 +76,6 @@ void __init lpc32xx_serial_init(void)
76 unsigned int puart; 76 unsigned int puart;
77 int i, j; 77 int i, j;
78 78
79 /* UART clocks are off, let clock driver manage them */
80 __raw_writel(0, LPC32XX_CLKPWR_UART_CLK_CTRL);
81
82 for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { 79 for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
83 clk = clk_get(NULL, uartinit_data[i].uart_ck_name); 80 clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
84 if (!IS_ERR(clk)) { 81 if (!IS_ERR(clk)) {
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
deleted file mode 100644
index ff3499d1fb1a..000000000000
--- a/arch/arm/mach-lpc32xx/timer.c
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 * arch/arm/mach-lpc32xx/timer.c
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2009 - 2010 NXP Semiconductors
7 * Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven
8 * Ed Schouten <e.schouten@fontys.nl>
9 * Laurens Timmermans <l.timmermans@fontys.nl>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/time.h>
25#include <linux/err.h>
26#include <linux/clockchips.h>
27
28#include <asm/mach/time.h>
29
30#include <mach/hardware.h>
31#include <mach/platform.h>
32#include "common.h"
33
34static int lpc32xx_clkevt_next_event(unsigned long delta,
35 struct clock_event_device *dev)
36{
37 __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
38 LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
39 __raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
40 __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
41 LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
42
43 return 0;
44}
45
46static int lpc32xx_shutdown(struct clock_event_device *evt)
47{
48 /*
49 * Disable the timer. When using oneshot, we must also
50 * disable the timer to wait for the first call to
51 * set_next_event().
52 */
53 __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
54 return 0;
55}
56
57static struct clock_event_device lpc32xx_clkevt = {
58 .name = "lpc32xx_clkevt",
59 .features = CLOCK_EVT_FEAT_ONESHOT,
60 .rating = 300,
61 .set_next_event = lpc32xx_clkevt_next_event,
62 .set_state_shutdown = lpc32xx_shutdown,
63 .set_state_oneshot = lpc32xx_shutdown,
64};
65
66static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
67{
68 struct clock_event_device *evt = &lpc32xx_clkevt;
69
70 /* Clear match */
71 __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
72 LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
73
74 evt->event_handler(evt);
75
76 return IRQ_HANDLED;
77}
78
79static struct irqaction lpc32xx_timer_irq = {
80 .name = "LPC32XX Timer Tick",
81 .flags = IRQF_TIMER | IRQF_IRQPOLL,
82 .handler = lpc32xx_timer_interrupt,
83};
84
85/*
86 * The clock management driver isn't initialized at this point, so the
87 * clocks need to be enabled here manually and then tagged as used in
88 * the clock driver initialization
89 */
90void __init lpc32xx_timer_init(void)
91{
92 u32 clkrate, pllreg;
93
94 /* Enable timer clock */
95 __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
96 LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
97 LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1);
98
99 /*
100 * The clock driver isn't initialized at this point. So determine if
101 * the SYSCLK is driven from the PLL397 or main oscillator and then use
102 * it to compute the PLL frequency and the PCLK divider to get the base
103 * timer rates. This rate is needed to compute the tick rate.
104 */
105 if (clk_is_sysclk_mainosc() != 0)
106 clkrate = LPC32XX_MAIN_OSC_FREQ;
107 else
108 clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
109
110 /* Get ARM HCLKPLL register and convert it into a frequency */
111 pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
112 clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
113
114 /* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
115 clkrate = clkrate / clk_get_pclk_div();
116
117 /* Initial timer setup */
118 __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
119 __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
120 LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
121 __raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
122 __raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) |
123 LPC32XX_TIMER_CNTR_MCR_STOP(0) |
124 LPC32XX_TIMER_CNTR_MCR_RESET(0),
125 LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
126
127 /* Setup tick interrupt */
128 setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
129
130 /* Setup the clockevent structure. */
131 lpc32xx_clkevt.cpumask = cpumask_of(0);
132 clockevents_config_and_register(&lpc32xx_clkevt, clkrate, 1, -1);
133
134 /* Use timer1 as clock source. */
135 __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
136 LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
137 __raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
138 __raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
139 __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
140 LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
141
142 clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
143 "lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
144}
diff --git a/arch/arm/mach-mmp/Makefile.boot b/arch/arm/mach-mmp/Makefile.boot
deleted file mode 100644
index 5edf03e2beed..000000000000
--- a/arch/arm/mach-mmp/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
1 zreladdr-y += 0x00008000
diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig
index a32575fa3fba..c32f85559c65 100644
--- a/arch/arm/mach-mv78xx0/Kconfig
+++ b/arch/arm/mach-mv78xx0/Kconfig
@@ -1,5 +1,6 @@
1menuconfig ARCH_MV78XX0 1menuconfig ARCH_MV78XX0
2 bool "Marvell MV78xx0" if ARCH_MULTI_V5 2 bool "Marvell MV78xx0"
3 depends on ARCH_MULTI_V5
3 select ARCH_REQUIRE_GPIOLIB 4 select ARCH_REQUIRE_GPIOLIB
4 select CPU_FEROCEON 5 select CPU_FEROCEON
5 select MVEBU_MBUS 6 select MVEBU_MBUS
diff --git a/arch/arm/mach-mv78xx0/Makefile.boot b/arch/arm/mach-mv78xx0/Makefile.boot
deleted file mode 100644
index 760a0efe7580..000000000000
--- a/arch/arm/mach-mv78xx0/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y += 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index f9597b701028..46c742d3bd41 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -140,6 +140,7 @@ static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
140 panic("Cannot find 'marvell,bootrom' compatible node"); 140 panic("Cannot find 'marvell,bootrom' compatible node");
141 141
142 err = of_address_to_resource(node, 0, &res); 142 err = of_address_to_resource(node, 0, &res);
143 of_node_put(node);
143 if (err < 0) 144 if (err < 0)
144 panic("Cannot get 'bootrom' node address"); 145 panic("Cannot get 'bootrom' node address");
145 146
diff --git a/arch/arm/mach-netx/Kconfig b/arch/arm/mach-netx/Kconfig
index 3d90ef19be2b..2da8e5dfcf24 100644
--- a/arch/arm/mach-netx/Kconfig
+++ b/arch/arm/mach-netx/Kconfig
@@ -3,20 +3,17 @@ menu "NetX Implementations"
3 3
4config MACH_NXDKN 4config MACH_NXDKN
5 bool "Enable Hilscher nxdkn Eval Board support" 5 bool "Enable Hilscher nxdkn Eval Board support"
6 depends on ARCH_NETX
7 help 6 help
8 Board support for the Hilscher NetX Eval Board 7 Board support for the Hilscher NetX Eval Board
9 8
10config MACH_NXDB500 9config MACH_NXDB500
11 bool "Enable Hilscher nxdb500 Eval Board support" 10 bool "Enable Hilscher nxdb500 Eval Board support"
12 depends on ARCH_NETX
13 select ARM_AMBA 11 select ARM_AMBA
14 help 12 help
15 Board support for the Hilscher nxdb500 Eval Board 13 Board support for the Hilscher nxdb500 Eval Board
16 14
17config MACH_NXEB500HMI 15config MACH_NXEB500HMI
18 bool "Enable Hilscher nxeb500hmi Eval Board support" 16 bool "Enable Hilscher nxeb500hmi Eval Board support"
19 depends on ARCH_NETX
20 select ARM_AMBA 17 select ARM_AMBA
21 help 18 help
22 Board support for the Hilscher nxeb500hmi Eval Board 19 Board support for the Hilscher nxeb500hmi Eval Board
diff --git a/arch/arm/mach-nspire/Makefile.boot b/arch/arm/mach-nspire/Makefile.boot
deleted file mode 100644
index e69de29bb2d1..000000000000
--- a/arch/arm/mach-nspire/Makefile.boot
+++ /dev/null
diff --git a/arch/arm/mach-omap2/Makefile.boot b/arch/arm/mach-omap2/Makefile.boot
deleted file mode 100644
index b03e562acc60..000000000000
--- a/arch/arm/mach-omap2/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y += 0x80008000
2params_phys-y := 0x80000100
3initrd_phys-y := 0x80800000
diff --git a/arch/arm/mach-orion5x/Makefile.boot b/arch/arm/mach-orion5x/Makefile.boot
deleted file mode 100644
index 760a0efe7580..000000000000
--- a/arch/arm/mach-orion5x/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y += 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-prima2/Makefile.boot b/arch/arm/mach-prima2/Makefile.boot
deleted file mode 100644
index c77a4883a4ee..000000000000
--- a/arch/arm/mach-prima2/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1zreladdr-y += 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-realview/Makefile.boot b/arch/arm/mach-realview/Makefile.boot
deleted file mode 100644
index d2c3d788f688..000000000000
--- a/arch/arm/mach-realview/Makefile.boot
+++ /dev/null
@@ -1,9 +0,0 @@
1ifeq ($(CONFIG_REALVIEW_HIGH_PHYS_OFFSET),y)
2 zreladdr-y += 0x70008000
3params_phys-y := 0x70000100
4initrd_phys-y := 0x70800000
5else
6 zreladdr-y += 0x00008000
7params_phys-y := 0x00000100
8initrd_phys-y := 0x00800000
9endif
diff --git a/arch/arm/mach-s3c64xx/Makefile.boot b/arch/arm/mach-s3c64xx/Makefile.boot
deleted file mode 100644
index c642333af3ed..000000000000
--- a/arch/arm/mach-s3c64xx/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y += 0x50008000
2params_phys-y := 0x50000100
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index cd5f171f83ce..aa0b1a177d3e 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -99,6 +99,4 @@ config ARCH_SH73A0
99 bool "SH-Mobile AG5 (R8A73A00)" 99 bool "SH-Mobile AG5 (R8A73A00)"
100 select ARCH_RMOBILE 100 select ARCH_RMOBILE
101 select RENESAS_INTC_IRQPIN 101 select RENESAS_INTC_IRQPIN
102
103comment "Renesas ARM SoCs System Configuration"
104endif 102endif
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index b3a4ed5289ec..5464b7a75e30 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -11,7 +11,8 @@ extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
11 unsigned long arg); 11 unsigned long arg);
12extern bool shmobile_smp_cpu_can_disable(unsigned int cpu); 12extern bool shmobile_smp_cpu_can_disable(unsigned int cpu);
13extern void shmobile_boot_scu(void); 13extern void shmobile_boot_scu(void);
14extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); 14extern void shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys,
15 unsigned int max_cpus);
15extern void shmobile_smp_scu_cpu_die(unsigned int cpu); 16extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
16extern int shmobile_smp_scu_cpu_kill(unsigned int cpu); 17extern int shmobile_smp_scu_cpu_kill(unsigned int cpu);
17extern struct platform_suspend_ops shmobile_suspend_ops; 18extern struct platform_suspend_ops shmobile_suspend_ops;
@@ -30,8 +31,6 @@ int shmobile_cpufreq_init(void);
30static inline int shmobile_cpufreq_init(void) { return 0; } 31static inline int shmobile_cpufreq_init(void) { return 0; }
31#endif 32#endif
32 33
33extern void __iomem *shmobile_scu_base;
34
35static inline void __init shmobile_init_late(void) 34static inline void __init shmobile_init_late(void)
36{ 35{
37 shmobile_suspend_init(); 36 shmobile_suspend_init();
diff --git a/arch/arm/mach-shmobile/cpufreq.c b/arch/arm/mach-shmobile/cpufreq.c
index 57fbff024dcd..634d701c56a7 100644
--- a/arch/arm/mach-shmobile/cpufreq.c
+++ b/arch/arm/mach-shmobile/cpufreq.c
@@ -10,6 +10,8 @@
10 10
11#include <linux/platform_device.h> 11#include <linux/platform_device.h>
12 12
13#include "common.h"
14
13int __init shmobile_cpufreq_init(void) 15int __init shmobile_cpufreq_init(void)
14{ 16{
15 platform_device_register_simple("cpufreq-dt", -1, NULL, 0); 17 platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S
index 5e503d91ad70..936d7011c314 100644
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -27,7 +27,7 @@
27 */ 27 */
28ENTRY(shmobile_boot_scu) 28ENTRY(shmobile_boot_scu)
29 @ r0 = SCU base address 29 @ r0 = SCU base address
30 mrc p15, 0, r1, c0, c0, 5 @ read MIPDR 30 mrc p15, 0, r1, c0, c0, 5 @ read MPIDR
31 and r1, r1, #3 @ mask out cpu ID 31 and r1, r1, #3 @ mask out cpu ID
32 lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits 32 lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
33 ldr r2, [r0, #8] @ SCU Power Status Register 33 ldr r2, [r0, #8] @ SCU Power Status Register
diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c
index 081a097c9219..8d478f1da265 100644
--- a/arch/arm/mach-shmobile/platsmp-scu.c
+++ b/arch/arm/mach-shmobile/platsmp-scu.c
@@ -18,7 +18,8 @@
18#include "common.h" 18#include "common.h"
19 19
20 20
21void __iomem *shmobile_scu_base; 21static phys_addr_t shmobile_scu_base_phys;
22static void __iomem *shmobile_scu_base;
22 23
23static int shmobile_smp_scu_notifier_call(struct notifier_block *nfb, 24static int shmobile_smp_scu_notifier_call(struct notifier_block *nfb,
24 unsigned long action, void *hcpu) 25 unsigned long action, void *hcpu)
@@ -29,7 +30,7 @@ static int shmobile_smp_scu_notifier_call(struct notifier_block *nfb,
29 case CPU_UP_PREPARE: 30 case CPU_UP_PREPARE:
30 /* For this particular CPU register SCU SMP boot vector */ 31 /* For this particular CPU register SCU SMP boot vector */
31 shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu), 32 shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu),
32 (unsigned long)shmobile_scu_base); 33 shmobile_scu_base_phys);
33 break; 34 break;
34 }; 35 };
35 36
@@ -40,12 +41,15 @@ static struct notifier_block shmobile_smp_scu_notifier = {
40 .notifier_call = shmobile_smp_scu_notifier_call, 41 .notifier_call = shmobile_smp_scu_notifier_call,
41}; 42};
42 43
43void __init shmobile_smp_scu_prepare_cpus(unsigned int max_cpus) 44void __init shmobile_smp_scu_prepare_cpus(phys_addr_t scu_base_phys,
45 unsigned int max_cpus)
44{ 46{
45 /* install boot code shared by all CPUs */ 47 /* install boot code shared by all CPUs */
46 shmobile_boot_fn = virt_to_phys(shmobile_smp_boot); 48 shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
47 49
48 /* enable SCU and cache coherency on booting CPU */ 50 /* enable SCU and cache coherency on booting CPU */
51 shmobile_scu_base_phys = scu_base_phys;
52 shmobile_scu_base = ioremap(scu_base_phys, PAGE_SIZE);
49 scu_enable(shmobile_scu_base); 53 scu_enable(shmobile_scu_base);
50 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); 54 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
51 55
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 9eccde3c7b13..6d0ebdfb03a2 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -182,8 +182,6 @@ static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname,
182 return 0; 182 return 0;
183} 183}
184 184
185struct cma *rcar_gen2_dma_contiguous;
186
187void __init rcar_gen2_reserve(void) 185void __init rcar_gen2_reserve(void)
188{ 186{
189 struct memory_reserve_config mrc; 187 struct memory_reserve_config mrc;
@@ -194,8 +192,11 @@ void __init rcar_gen2_reserve(void)
194 192
195 of_scan_flat_dt(rcar_gen2_scan_mem, &mrc); 193 of_scan_flat_dt(rcar_gen2_scan_mem, &mrc);
196#ifdef CONFIG_DMA_CMA 194#ifdef CONFIG_DMA_CMA
197 if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size)) 195 if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size)) {
196 static struct cma *rcar_gen2_dma_contiguous;
197
198 dma_contiguous_reserve_area(mrc.size, mrc.base, 0, 198 dma_contiguous_reserve_area(mrc.size, mrc.base, 0,
199 &rcar_gen2_dma_contiguous, true); 199 &rcar_gen2_dma_contiguous, true);
200 }
200#endif 201#endif
201} 202}
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index adbac6963f2b..4dfafd845452 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -45,8 +45,7 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
45 } 45 }
46 46
47 /* setup EMEV2 specific SCU bits */ 47 /* setup EMEV2 specific SCU bits */
48 shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); 48 shmobile_smp_scu_prepare_cpus(EMEV2_SCU_BASE, max_cpus);
49 shmobile_smp_scu_prepare_cpus(max_cpus);
50} 49}
51 50
52const struct smp_operations emev2_smp_ops __initconst = { 51const struct smp_operations emev2_smp_ops __initconst = {
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 0b024a9dbd43..f5c31fbc10b2 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -94,8 +94,7 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
94 __raw_writel(__pa(shmobile_boot_vector), AVECR); 94 __raw_writel(__pa(shmobile_boot_vector), AVECR);
95 95
96 /* setup r8a7779 specific SCU bits */ 96 /* setup r8a7779 specific SCU bits */
97 shmobile_scu_base = IOMEM(R8A7779_SCU_BASE); 97 shmobile_smp_scu_prepare_cpus(R8A7779_SCU_BASE, max_cpus);
98 shmobile_smp_scu_prepare_cpus(max_cpus);
99 98
100 r8a7779_pm_init(); 99 r8a7779_pm_init();
101 100
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index ee1a4b70604b..41137404382e 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -52,8 +52,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
52 __raw_writel(__pa(shmobile_boot_vector), SBAR); 52 __raw_writel(__pa(shmobile_boot_vector), SBAR);
53 53
54 /* setup sh73a0 specific SCU bits */ 54 /* setup sh73a0 specific SCU bits */
55 shmobile_scu_base = IOMEM(SH73A0_SCU_BASE); 55 shmobile_smp_scu_prepare_cpus(SH73A0_SCU_BASE, max_cpus);
56 shmobile_smp_scu_prepare_cpus(max_cpus);
57} 56}
58 57
59const struct smp_operations sh73a0_smp_ops __initconst = { 58const struct smp_operations sh73a0_smp_ops __initconst = {
diff --git a/arch/arm/mach-shmobile/suspend.c b/arch/arm/mach-shmobile/suspend.c
index 5d92b5dd486b..74b30bade2c1 100644
--- a/arch/arm/mach-shmobile/suspend.c
+++ b/arch/arm/mach-shmobile/suspend.c
@@ -17,6 +17,8 @@
17#include <asm/io.h> 17#include <asm/io.h>
18#include <asm/system_misc.h> 18#include <asm/system_misc.h>
19 19
20#include "common.h"
21
20static int shmobile_suspend_default_enter(suspend_state_t suspend_state) 22static int shmobile_suspend_default_enter(suspend_state_t suspend_state)
21{ 23{
22 cpu_do_idle(); 24 cpu_do_idle();
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index c17d4d3881ff..ad008e4b0c49 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -18,6 +18,8 @@
18#include <linux/delay.h> 18#include <linux/delay.h>
19#include <linux/of_address.h> 19#include <linux/of_address.h>
20 20
21#include "common.h"
22
21static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz, 23static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
22 unsigned int mult, unsigned int div) 24 unsigned int mult, unsigned int div)
23{ 25{
diff --git a/arch/arm/mach-spear/Makefile.boot b/arch/arm/mach-spear/Makefile.boot
deleted file mode 100644
index 4674a4c221db..000000000000
--- a/arch/arm/mach-spear/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1zreladdr-y += 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-u300/Makefile.boot b/arch/arm/mach-u300/Makefile.boot
deleted file mode 100644
index 87811de0bd94..000000000000
--- a/arch/arm/mach-u300/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
1 zreladdr-y += 0x48008000
2params_phys-y := 0x48000100
3# This isn't used.
4#initrd_phys-y := 0x48800000
diff --git a/arch/arm/mach-ux500/Makefile.boot b/arch/arm/mach-ux500/Makefile.boot
deleted file mode 100644
index 760a0efe7580..000000000000
--- a/arch/arm/mach-ux500/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y += 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-zynq/Makefile.boot b/arch/arm/mach-zynq/Makefile.boot
deleted file mode 100644
index 760a0efe7580..000000000000
--- a/arch/arm/mach-zynq/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y += 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index 49b8ef91584a..98b9b8e9f698 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -1,8 +1,5 @@
1if PLAT_VERSATILE 1if PLAT_VERSATILE
2 2
3config PLAT_VERSATILE_CLOCK
4 bool
5
6config PLAT_VERSATILE_SCHED_CLOCK 3config PLAT_VERSATILE_SCHED_CLOCK
7 bool 4 bool
8 5
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 03c4900ac3f4..bff3ba889882 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,5 +1,4 @@
1ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include 1ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
2 2
3obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
4obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o 3obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o
5obj-$(CONFIG_SMP) += headsmp.o platsmp.o 4obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/plat-versatile/clock.c b/arch/arm/plat-versatile/clock.c
deleted file mode 100644
index 5c8b6564fdc2..000000000000
--- a/arch/arm/plat-versatile/clock.c
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * linux/arch/arm/plat-versatile/clock.c
3 *
4 * Copyright (C) 2004 ARM Limited.
5 * Written by Deep Blue Solutions Limited.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/clk.h>
15#include <linux/mutex.h>
16
17#include <asm/hardware/icst.h>
18
19#include <mach/clkdev.h>
20
21int clk_enable(struct clk *clk)
22{
23 return 0;
24}
25EXPORT_SYMBOL(clk_enable);
26
27void clk_disable(struct clk *clk)
28{
29}
30EXPORT_SYMBOL(clk_disable);
31
32unsigned long clk_get_rate(struct clk *clk)
33{
34 return clk->rate;
35}
36EXPORT_SYMBOL(clk_get_rate);
37
38long clk_round_rate(struct clk *clk, unsigned long rate)
39{
40 long ret = -EIO;
41 if (clk->ops && clk->ops->round)
42 ret = clk->ops->round(clk, rate);
43 return ret;
44}
45EXPORT_SYMBOL(clk_round_rate);
46
47int clk_set_rate(struct clk *clk, unsigned long rate)
48{
49 int ret = -EIO;
50 if (clk->ops && clk->ops->set)
51 ret = clk->ops->set(clk, rate);
52 return ret;
53}
54EXPORT_SYMBOL(clk_set_rate);
55
56long icst_clk_round(struct clk *clk, unsigned long rate)
57{
58 struct icst_vco vco;
59 vco = icst_hz_to_vco(clk->params, rate);
60 return icst_hz(clk->params, vco);
61}
62EXPORT_SYMBOL(icst_clk_round);
63
64int icst_clk_set(struct clk *clk, unsigned long rate)
65{
66 struct icst_vco vco;
67
68 vco = icst_hz_to_vco(clk->params, rate);
69 clk->rate = icst_hz(clk->params, vco);
70 clk->ops->setvco(clk, vco);
71
72 return 0;
73}
74EXPORT_SYMBOL(icst_clk_set);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-10 14:48:28 -0400